1 /* 2 * Marvell MV88W8618 / Freecom MusicPal emulation. 3 * 4 * Copyright (c) 2008 Jan Kiszka 5 * 6 * This code is licensed under the GNU GPL v2. 7 * 8 * Contributions after 2012-01-13 are licensed under the terms of the 9 * GNU GPL, version 2 or (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "cpu.h" 15 #include "hw/sysbus.h" 16 #include "migration/vmstate.h" 17 #include "hw/arm/boot.h" 18 #include "net/net.h" 19 #include "sysemu/sysemu.h" 20 #include "hw/boards.h" 21 #include "hw/char/serial.h" 22 #include "hw/hw.h" 23 #include "qemu/timer.h" 24 #include "hw/ptimer.h" 25 #include "hw/block/flash.h" 26 #include "ui/console.h" 27 #include "hw/i2c/i2c.h" 28 #include "hw/irq.h" 29 #include "hw/audio/wm8750.h" 30 #include "sysemu/block-backend.h" 31 #include "exec/address-spaces.h" 32 #include "ui/pixel_ops.h" 33 34 #define MP_MISC_BASE 0x80002000 35 #define MP_MISC_SIZE 0x00001000 36 37 #define MP_ETH_BASE 0x80008000 38 #define MP_ETH_SIZE 0x00001000 39 40 #define MP_WLAN_BASE 0x8000C000 41 #define MP_WLAN_SIZE 0x00000800 42 43 #define MP_UART1_BASE 0x8000C840 44 #define MP_UART2_BASE 0x8000C940 45 46 #define MP_GPIO_BASE 0x8000D000 47 #define MP_GPIO_SIZE 0x00001000 48 49 #define MP_FLASHCFG_BASE 0x90006000 50 #define MP_FLASHCFG_SIZE 0x00001000 51 52 #define MP_AUDIO_BASE 0x90007000 53 54 #define MP_PIC_BASE 0x90008000 55 #define MP_PIC_SIZE 0x00001000 56 57 #define MP_PIT_BASE 0x90009000 58 #define MP_PIT_SIZE 0x00001000 59 60 #define MP_LCD_BASE 0x9000c000 61 #define MP_LCD_SIZE 0x00001000 62 63 #define MP_SRAM_BASE 0xC0000000 64 #define MP_SRAM_SIZE 0x00020000 65 66 #define MP_RAM_DEFAULT_SIZE 32*1024*1024 67 #define MP_FLASH_SIZE_MAX 32*1024*1024 68 69 #define MP_TIMER1_IRQ 4 70 #define MP_TIMER2_IRQ 5 71 #define MP_TIMER3_IRQ 6 72 #define MP_TIMER4_IRQ 7 73 #define MP_EHCI_IRQ 8 74 #define MP_ETH_IRQ 9 75 #define MP_UART1_IRQ 11 76 #define MP_UART2_IRQ 11 77 #define MP_GPIO_IRQ 12 78 #define MP_RTC_IRQ 28 79 #define MP_AUDIO_IRQ 30 80 81 /* Wolfson 8750 I2C address */ 82 #define MP_WM_ADDR 0x1A 83 84 /* Ethernet register offsets */ 85 #define MP_ETH_SMIR 0x010 86 #define MP_ETH_PCXR 0x408 87 #define MP_ETH_SDCMR 0x448 88 #define MP_ETH_ICR 0x450 89 #define MP_ETH_IMR 0x458 90 #define MP_ETH_FRDP0 0x480 91 #define MP_ETH_FRDP1 0x484 92 #define MP_ETH_FRDP2 0x488 93 #define MP_ETH_FRDP3 0x48C 94 #define MP_ETH_CRDP0 0x4A0 95 #define MP_ETH_CRDP1 0x4A4 96 #define MP_ETH_CRDP2 0x4A8 97 #define MP_ETH_CRDP3 0x4AC 98 #define MP_ETH_CTDP0 0x4E0 99 #define MP_ETH_CTDP1 0x4E4 100 101 /* MII PHY access */ 102 #define MP_ETH_SMIR_DATA 0x0000FFFF 103 #define MP_ETH_SMIR_ADDR 0x03FF0000 104 #define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */ 105 #define MP_ETH_SMIR_RDVALID (1 << 27) 106 107 /* PHY registers */ 108 #define MP_ETH_PHY1_BMSR 0x00210000 109 #define MP_ETH_PHY1_PHYSID1 0x00410000 110 #define MP_ETH_PHY1_PHYSID2 0x00610000 111 112 #define MP_PHY_BMSR_LINK 0x0004 113 #define MP_PHY_BMSR_AUTONEG 0x0008 114 115 #define MP_PHY_88E3015 0x01410E20 116 117 /* TX descriptor status */ 118 #define MP_ETH_TX_OWN (1U << 31) 119 120 /* RX descriptor status */ 121 #define MP_ETH_RX_OWN (1U << 31) 122 123 /* Interrupt cause/mask bits */ 124 #define MP_ETH_IRQ_RX_BIT 0 125 #define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT) 126 #define MP_ETH_IRQ_TXHI_BIT 2 127 #define MP_ETH_IRQ_TXLO_BIT 3 128 129 /* Port config bits */ 130 #define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */ 131 132 /* SDMA command bits */ 133 #define MP_ETH_CMD_TXHI (1 << 23) 134 #define MP_ETH_CMD_TXLO (1 << 22) 135 136 typedef struct mv88w8618_tx_desc { 137 uint32_t cmdstat; 138 uint16_t res; 139 uint16_t bytes; 140 uint32_t buffer; 141 uint32_t next; 142 } mv88w8618_tx_desc; 143 144 typedef struct mv88w8618_rx_desc { 145 uint32_t cmdstat; 146 uint16_t bytes; 147 uint16_t buffer_size; 148 uint32_t buffer; 149 uint32_t next; 150 } mv88w8618_rx_desc; 151 152 #define TYPE_MV88W8618_ETH "mv88w8618_eth" 153 #define MV88W8618_ETH(obj) \ 154 OBJECT_CHECK(mv88w8618_eth_state, (obj), TYPE_MV88W8618_ETH) 155 156 typedef struct mv88w8618_eth_state { 157 /*< private >*/ 158 SysBusDevice parent_obj; 159 /*< public >*/ 160 161 MemoryRegion iomem; 162 qemu_irq irq; 163 uint32_t smir; 164 uint32_t icr; 165 uint32_t imr; 166 int mmio_index; 167 uint32_t vlan_header; 168 uint32_t tx_queue[2]; 169 uint32_t rx_queue[4]; 170 uint32_t frx_queue[4]; 171 uint32_t cur_rx[4]; 172 NICState *nic; 173 NICConf conf; 174 } mv88w8618_eth_state; 175 176 static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc) 177 { 178 cpu_to_le32s(&desc->cmdstat); 179 cpu_to_le16s(&desc->bytes); 180 cpu_to_le16s(&desc->buffer_size); 181 cpu_to_le32s(&desc->buffer); 182 cpu_to_le32s(&desc->next); 183 cpu_physical_memory_write(addr, desc, sizeof(*desc)); 184 } 185 186 static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc) 187 { 188 cpu_physical_memory_read(addr, desc, sizeof(*desc)); 189 le32_to_cpus(&desc->cmdstat); 190 le16_to_cpus(&desc->bytes); 191 le16_to_cpus(&desc->buffer_size); 192 le32_to_cpus(&desc->buffer); 193 le32_to_cpus(&desc->next); 194 } 195 196 static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size) 197 { 198 mv88w8618_eth_state *s = qemu_get_nic_opaque(nc); 199 uint32_t desc_addr; 200 mv88w8618_rx_desc desc; 201 int i; 202 203 for (i = 0; i < 4; i++) { 204 desc_addr = s->cur_rx[i]; 205 if (!desc_addr) { 206 continue; 207 } 208 do { 209 eth_rx_desc_get(desc_addr, &desc); 210 if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) { 211 cpu_physical_memory_write(desc.buffer + s->vlan_header, 212 buf, size); 213 desc.bytes = size + s->vlan_header; 214 desc.cmdstat &= ~MP_ETH_RX_OWN; 215 s->cur_rx[i] = desc.next; 216 217 s->icr |= MP_ETH_IRQ_RX; 218 if (s->icr & s->imr) { 219 qemu_irq_raise(s->irq); 220 } 221 eth_rx_desc_put(desc_addr, &desc); 222 return size; 223 } 224 desc_addr = desc.next; 225 } while (desc_addr != s->rx_queue[i]); 226 } 227 return size; 228 } 229 230 static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc) 231 { 232 cpu_to_le32s(&desc->cmdstat); 233 cpu_to_le16s(&desc->res); 234 cpu_to_le16s(&desc->bytes); 235 cpu_to_le32s(&desc->buffer); 236 cpu_to_le32s(&desc->next); 237 cpu_physical_memory_write(addr, desc, sizeof(*desc)); 238 } 239 240 static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc) 241 { 242 cpu_physical_memory_read(addr, desc, sizeof(*desc)); 243 le32_to_cpus(&desc->cmdstat); 244 le16_to_cpus(&desc->res); 245 le16_to_cpus(&desc->bytes); 246 le32_to_cpus(&desc->buffer); 247 le32_to_cpus(&desc->next); 248 } 249 250 static void eth_send(mv88w8618_eth_state *s, int queue_index) 251 { 252 uint32_t desc_addr = s->tx_queue[queue_index]; 253 mv88w8618_tx_desc desc; 254 uint32_t next_desc; 255 uint8_t buf[2048]; 256 int len; 257 258 do { 259 eth_tx_desc_get(desc_addr, &desc); 260 next_desc = desc.next; 261 if (desc.cmdstat & MP_ETH_TX_OWN) { 262 len = desc.bytes; 263 if (len < 2048) { 264 cpu_physical_memory_read(desc.buffer, buf, len); 265 qemu_send_packet(qemu_get_queue(s->nic), buf, len); 266 } 267 desc.cmdstat &= ~MP_ETH_TX_OWN; 268 s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index); 269 eth_tx_desc_put(desc_addr, &desc); 270 } 271 desc_addr = next_desc; 272 } while (desc_addr != s->tx_queue[queue_index]); 273 } 274 275 static uint64_t mv88w8618_eth_read(void *opaque, hwaddr offset, 276 unsigned size) 277 { 278 mv88w8618_eth_state *s = opaque; 279 280 switch (offset) { 281 case MP_ETH_SMIR: 282 if (s->smir & MP_ETH_SMIR_OPCODE) { 283 switch (s->smir & MP_ETH_SMIR_ADDR) { 284 case MP_ETH_PHY1_BMSR: 285 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG | 286 MP_ETH_SMIR_RDVALID; 287 case MP_ETH_PHY1_PHYSID1: 288 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID; 289 case MP_ETH_PHY1_PHYSID2: 290 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID; 291 default: 292 return MP_ETH_SMIR_RDVALID; 293 } 294 } 295 return 0; 296 297 case MP_ETH_ICR: 298 return s->icr; 299 300 case MP_ETH_IMR: 301 return s->imr; 302 303 case MP_ETH_FRDP0 ... MP_ETH_FRDP3: 304 return s->frx_queue[(offset - MP_ETH_FRDP0)/4]; 305 306 case MP_ETH_CRDP0 ... MP_ETH_CRDP3: 307 return s->rx_queue[(offset - MP_ETH_CRDP0)/4]; 308 309 case MP_ETH_CTDP0 ... MP_ETH_CTDP1: 310 return s->tx_queue[(offset - MP_ETH_CTDP0)/4]; 311 312 default: 313 return 0; 314 } 315 } 316 317 static void mv88w8618_eth_write(void *opaque, hwaddr offset, 318 uint64_t value, unsigned size) 319 { 320 mv88w8618_eth_state *s = opaque; 321 322 switch (offset) { 323 case MP_ETH_SMIR: 324 s->smir = value; 325 break; 326 327 case MP_ETH_PCXR: 328 s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2; 329 break; 330 331 case MP_ETH_SDCMR: 332 if (value & MP_ETH_CMD_TXHI) { 333 eth_send(s, 1); 334 } 335 if (value & MP_ETH_CMD_TXLO) { 336 eth_send(s, 0); 337 } 338 if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) { 339 qemu_irq_raise(s->irq); 340 } 341 break; 342 343 case MP_ETH_ICR: 344 s->icr &= value; 345 break; 346 347 case MP_ETH_IMR: 348 s->imr = value; 349 if (s->icr & s->imr) { 350 qemu_irq_raise(s->irq); 351 } 352 break; 353 354 case MP_ETH_FRDP0 ... MP_ETH_FRDP3: 355 s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value; 356 break; 357 358 case MP_ETH_CRDP0 ... MP_ETH_CRDP3: 359 s->rx_queue[(offset - MP_ETH_CRDP0)/4] = 360 s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value; 361 break; 362 363 case MP_ETH_CTDP0 ... MP_ETH_CTDP1: 364 s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value; 365 break; 366 } 367 } 368 369 static const MemoryRegionOps mv88w8618_eth_ops = { 370 .read = mv88w8618_eth_read, 371 .write = mv88w8618_eth_write, 372 .endianness = DEVICE_NATIVE_ENDIAN, 373 }; 374 375 static void eth_cleanup(NetClientState *nc) 376 { 377 mv88w8618_eth_state *s = qemu_get_nic_opaque(nc); 378 379 s->nic = NULL; 380 } 381 382 static NetClientInfo net_mv88w8618_info = { 383 .type = NET_CLIENT_DRIVER_NIC, 384 .size = sizeof(NICState), 385 .receive = eth_receive, 386 .cleanup = eth_cleanup, 387 }; 388 389 static void mv88w8618_eth_init(Object *obj) 390 { 391 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 392 DeviceState *dev = DEVICE(sbd); 393 mv88w8618_eth_state *s = MV88W8618_ETH(dev); 394 395 sysbus_init_irq(sbd, &s->irq); 396 memory_region_init_io(&s->iomem, obj, &mv88w8618_eth_ops, s, 397 "mv88w8618-eth", MP_ETH_SIZE); 398 sysbus_init_mmio(sbd, &s->iomem); 399 } 400 401 static void mv88w8618_eth_realize(DeviceState *dev, Error **errp) 402 { 403 mv88w8618_eth_state *s = MV88W8618_ETH(dev); 404 405 s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf, 406 object_get_typename(OBJECT(dev)), dev->id, s); 407 } 408 409 static const VMStateDescription mv88w8618_eth_vmsd = { 410 .name = "mv88w8618_eth", 411 .version_id = 1, 412 .minimum_version_id = 1, 413 .fields = (VMStateField[]) { 414 VMSTATE_UINT32(smir, mv88w8618_eth_state), 415 VMSTATE_UINT32(icr, mv88w8618_eth_state), 416 VMSTATE_UINT32(imr, mv88w8618_eth_state), 417 VMSTATE_UINT32(vlan_header, mv88w8618_eth_state), 418 VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2), 419 VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4), 420 VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4), 421 VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4), 422 VMSTATE_END_OF_LIST() 423 } 424 }; 425 426 static Property mv88w8618_eth_properties[] = { 427 DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf), 428 DEFINE_PROP_END_OF_LIST(), 429 }; 430 431 static void mv88w8618_eth_class_init(ObjectClass *klass, void *data) 432 { 433 DeviceClass *dc = DEVICE_CLASS(klass); 434 435 dc->vmsd = &mv88w8618_eth_vmsd; 436 dc->props = mv88w8618_eth_properties; 437 dc->realize = mv88w8618_eth_realize; 438 } 439 440 static const TypeInfo mv88w8618_eth_info = { 441 .name = TYPE_MV88W8618_ETH, 442 .parent = TYPE_SYS_BUS_DEVICE, 443 .instance_size = sizeof(mv88w8618_eth_state), 444 .instance_init = mv88w8618_eth_init, 445 .class_init = mv88w8618_eth_class_init, 446 }; 447 448 /* LCD register offsets */ 449 #define MP_LCD_IRQCTRL 0x180 450 #define MP_LCD_IRQSTAT 0x184 451 #define MP_LCD_SPICTRL 0x1ac 452 #define MP_LCD_INST 0x1bc 453 #define MP_LCD_DATA 0x1c0 454 455 /* Mode magics */ 456 #define MP_LCD_SPI_DATA 0x00100011 457 #define MP_LCD_SPI_CMD 0x00104011 458 #define MP_LCD_SPI_INVALID 0x00000000 459 460 /* Commmands */ 461 #define MP_LCD_INST_SETPAGE0 0xB0 462 /* ... */ 463 #define MP_LCD_INST_SETPAGE7 0xB7 464 465 #define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */ 466 467 #define TYPE_MUSICPAL_LCD "musicpal_lcd" 468 #define MUSICPAL_LCD(obj) \ 469 OBJECT_CHECK(musicpal_lcd_state, (obj), TYPE_MUSICPAL_LCD) 470 471 typedef struct musicpal_lcd_state { 472 /*< private >*/ 473 SysBusDevice parent_obj; 474 /*< public >*/ 475 476 MemoryRegion iomem; 477 uint32_t brightness; 478 uint32_t mode; 479 uint32_t irqctrl; 480 uint32_t page; 481 uint32_t page_off; 482 QemuConsole *con; 483 uint8_t video_ram[128*64/8]; 484 } musicpal_lcd_state; 485 486 static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col) 487 { 488 switch (s->brightness) { 489 case 7: 490 return col; 491 case 0: 492 return 0; 493 default: 494 return (col * s->brightness) / 7; 495 } 496 } 497 498 #define SET_LCD_PIXEL(depth, type) \ 499 static inline void glue(set_lcd_pixel, depth) \ 500 (musicpal_lcd_state *s, int x, int y, type col) \ 501 { \ 502 int dx, dy; \ 503 DisplaySurface *surface = qemu_console_surface(s->con); \ 504 type *pixel = &((type *) surface_data(surface))[(y * 128 * 3 + x) * 3]; \ 505 \ 506 for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \ 507 for (dx = 0; dx < 3; dx++, pixel++) \ 508 *pixel = col; \ 509 } 510 SET_LCD_PIXEL(8, uint8_t) 511 SET_LCD_PIXEL(16, uint16_t) 512 SET_LCD_PIXEL(32, uint32_t) 513 514 static void lcd_refresh(void *opaque) 515 { 516 musicpal_lcd_state *s = opaque; 517 DisplaySurface *surface = qemu_console_surface(s->con); 518 int x, y, col; 519 520 switch (surface_bits_per_pixel(surface)) { 521 case 0: 522 return; 523 #define LCD_REFRESH(depth, func) \ 524 case depth: \ 525 col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \ 526 scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \ 527 scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \ 528 for (x = 0; x < 128; x++) { \ 529 for (y = 0; y < 64; y++) { \ 530 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \ 531 glue(set_lcd_pixel, depth)(s, x, y, col); \ 532 } else { \ 533 glue(set_lcd_pixel, depth)(s, x, y, 0); \ 534 } \ 535 } \ 536 } \ 537 break; 538 LCD_REFRESH(8, rgb_to_pixel8) 539 LCD_REFRESH(16, rgb_to_pixel16) 540 LCD_REFRESH(32, (is_surface_bgr(surface) ? 541 rgb_to_pixel32bgr : rgb_to_pixel32)) 542 default: 543 hw_error("unsupported colour depth %i\n", 544 surface_bits_per_pixel(surface)); 545 } 546 547 dpy_gfx_update(s->con, 0, 0, 128*3, 64*3); 548 } 549 550 static void lcd_invalidate(void *opaque) 551 { 552 } 553 554 static void musicpal_lcd_gpio_brightness_in(void *opaque, int irq, int level) 555 { 556 musicpal_lcd_state *s = opaque; 557 s->brightness &= ~(1 << irq); 558 s->brightness |= level << irq; 559 } 560 561 static uint64_t musicpal_lcd_read(void *opaque, hwaddr offset, 562 unsigned size) 563 { 564 musicpal_lcd_state *s = opaque; 565 566 switch (offset) { 567 case MP_LCD_IRQCTRL: 568 return s->irqctrl; 569 570 default: 571 return 0; 572 } 573 } 574 575 static void musicpal_lcd_write(void *opaque, hwaddr offset, 576 uint64_t value, unsigned size) 577 { 578 musicpal_lcd_state *s = opaque; 579 580 switch (offset) { 581 case MP_LCD_IRQCTRL: 582 s->irqctrl = value; 583 break; 584 585 case MP_LCD_SPICTRL: 586 if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) { 587 s->mode = value; 588 } else { 589 s->mode = MP_LCD_SPI_INVALID; 590 } 591 break; 592 593 case MP_LCD_INST: 594 if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) { 595 s->page = value - MP_LCD_INST_SETPAGE0; 596 s->page_off = 0; 597 } 598 break; 599 600 case MP_LCD_DATA: 601 if (s->mode == MP_LCD_SPI_CMD) { 602 if (value >= MP_LCD_INST_SETPAGE0 && 603 value <= MP_LCD_INST_SETPAGE7) { 604 s->page = value - MP_LCD_INST_SETPAGE0; 605 s->page_off = 0; 606 } 607 } else if (s->mode == MP_LCD_SPI_DATA) { 608 s->video_ram[s->page*128 + s->page_off] = value; 609 s->page_off = (s->page_off + 1) & 127; 610 } 611 break; 612 } 613 } 614 615 static const MemoryRegionOps musicpal_lcd_ops = { 616 .read = musicpal_lcd_read, 617 .write = musicpal_lcd_write, 618 .endianness = DEVICE_NATIVE_ENDIAN, 619 }; 620 621 static const GraphicHwOps musicpal_gfx_ops = { 622 .invalidate = lcd_invalidate, 623 .gfx_update = lcd_refresh, 624 }; 625 626 static void musicpal_lcd_realize(DeviceState *dev, Error **errp) 627 { 628 musicpal_lcd_state *s = MUSICPAL_LCD(dev); 629 s->con = graphic_console_init(dev, 0, &musicpal_gfx_ops, s); 630 qemu_console_resize(s->con, 128 * 3, 64 * 3); 631 } 632 633 static void musicpal_lcd_init(Object *obj) 634 { 635 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 636 DeviceState *dev = DEVICE(sbd); 637 musicpal_lcd_state *s = MUSICPAL_LCD(dev); 638 639 s->brightness = 7; 640 641 memory_region_init_io(&s->iomem, obj, &musicpal_lcd_ops, s, 642 "musicpal-lcd", MP_LCD_SIZE); 643 sysbus_init_mmio(sbd, &s->iomem); 644 645 qdev_init_gpio_in(dev, musicpal_lcd_gpio_brightness_in, 3); 646 } 647 648 static const VMStateDescription musicpal_lcd_vmsd = { 649 .name = "musicpal_lcd", 650 .version_id = 1, 651 .minimum_version_id = 1, 652 .fields = (VMStateField[]) { 653 VMSTATE_UINT32(brightness, musicpal_lcd_state), 654 VMSTATE_UINT32(mode, musicpal_lcd_state), 655 VMSTATE_UINT32(irqctrl, musicpal_lcd_state), 656 VMSTATE_UINT32(page, musicpal_lcd_state), 657 VMSTATE_UINT32(page_off, musicpal_lcd_state), 658 VMSTATE_BUFFER(video_ram, musicpal_lcd_state), 659 VMSTATE_END_OF_LIST() 660 } 661 }; 662 663 static void musicpal_lcd_class_init(ObjectClass *klass, void *data) 664 { 665 DeviceClass *dc = DEVICE_CLASS(klass); 666 667 dc->vmsd = &musicpal_lcd_vmsd; 668 dc->realize = musicpal_lcd_realize; 669 } 670 671 static const TypeInfo musicpal_lcd_info = { 672 .name = TYPE_MUSICPAL_LCD, 673 .parent = TYPE_SYS_BUS_DEVICE, 674 .instance_size = sizeof(musicpal_lcd_state), 675 .instance_init = musicpal_lcd_init, 676 .class_init = musicpal_lcd_class_init, 677 }; 678 679 /* PIC register offsets */ 680 #define MP_PIC_STATUS 0x00 681 #define MP_PIC_ENABLE_SET 0x08 682 #define MP_PIC_ENABLE_CLR 0x0C 683 684 #define TYPE_MV88W8618_PIC "mv88w8618_pic" 685 #define MV88W8618_PIC(obj) \ 686 OBJECT_CHECK(mv88w8618_pic_state, (obj), TYPE_MV88W8618_PIC) 687 688 typedef struct mv88w8618_pic_state { 689 /*< private >*/ 690 SysBusDevice parent_obj; 691 /*< public >*/ 692 693 MemoryRegion iomem; 694 uint32_t level; 695 uint32_t enabled; 696 qemu_irq parent_irq; 697 } mv88w8618_pic_state; 698 699 static void mv88w8618_pic_update(mv88w8618_pic_state *s) 700 { 701 qemu_set_irq(s->parent_irq, (s->level & s->enabled)); 702 } 703 704 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level) 705 { 706 mv88w8618_pic_state *s = opaque; 707 708 if (level) { 709 s->level |= 1 << irq; 710 } else { 711 s->level &= ~(1 << irq); 712 } 713 mv88w8618_pic_update(s); 714 } 715 716 static uint64_t mv88w8618_pic_read(void *opaque, hwaddr offset, 717 unsigned size) 718 { 719 mv88w8618_pic_state *s = opaque; 720 721 switch (offset) { 722 case MP_PIC_STATUS: 723 return s->level & s->enabled; 724 725 default: 726 return 0; 727 } 728 } 729 730 static void mv88w8618_pic_write(void *opaque, hwaddr offset, 731 uint64_t value, unsigned size) 732 { 733 mv88w8618_pic_state *s = opaque; 734 735 switch (offset) { 736 case MP_PIC_ENABLE_SET: 737 s->enabled |= value; 738 break; 739 740 case MP_PIC_ENABLE_CLR: 741 s->enabled &= ~value; 742 s->level &= ~value; 743 break; 744 } 745 mv88w8618_pic_update(s); 746 } 747 748 static void mv88w8618_pic_reset(DeviceState *d) 749 { 750 mv88w8618_pic_state *s = MV88W8618_PIC(d); 751 752 s->level = 0; 753 s->enabled = 0; 754 } 755 756 static const MemoryRegionOps mv88w8618_pic_ops = { 757 .read = mv88w8618_pic_read, 758 .write = mv88w8618_pic_write, 759 .endianness = DEVICE_NATIVE_ENDIAN, 760 }; 761 762 static void mv88w8618_pic_init(Object *obj) 763 { 764 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 765 mv88w8618_pic_state *s = MV88W8618_PIC(dev); 766 767 qdev_init_gpio_in(DEVICE(dev), mv88w8618_pic_set_irq, 32); 768 sysbus_init_irq(dev, &s->parent_irq); 769 memory_region_init_io(&s->iomem, obj, &mv88w8618_pic_ops, s, 770 "musicpal-pic", MP_PIC_SIZE); 771 sysbus_init_mmio(dev, &s->iomem); 772 } 773 774 static const VMStateDescription mv88w8618_pic_vmsd = { 775 .name = "mv88w8618_pic", 776 .version_id = 1, 777 .minimum_version_id = 1, 778 .fields = (VMStateField[]) { 779 VMSTATE_UINT32(level, mv88w8618_pic_state), 780 VMSTATE_UINT32(enabled, mv88w8618_pic_state), 781 VMSTATE_END_OF_LIST() 782 } 783 }; 784 785 static void mv88w8618_pic_class_init(ObjectClass *klass, void *data) 786 { 787 DeviceClass *dc = DEVICE_CLASS(klass); 788 789 dc->reset = mv88w8618_pic_reset; 790 dc->vmsd = &mv88w8618_pic_vmsd; 791 } 792 793 static const TypeInfo mv88w8618_pic_info = { 794 .name = TYPE_MV88W8618_PIC, 795 .parent = TYPE_SYS_BUS_DEVICE, 796 .instance_size = sizeof(mv88w8618_pic_state), 797 .instance_init = mv88w8618_pic_init, 798 .class_init = mv88w8618_pic_class_init, 799 }; 800 801 /* PIT register offsets */ 802 #define MP_PIT_TIMER1_LENGTH 0x00 803 /* ... */ 804 #define MP_PIT_TIMER4_LENGTH 0x0C 805 #define MP_PIT_CONTROL 0x10 806 #define MP_PIT_TIMER1_VALUE 0x14 807 /* ... */ 808 #define MP_PIT_TIMER4_VALUE 0x20 809 #define MP_BOARD_RESET 0x34 810 811 /* Magic board reset value (probably some watchdog behind it) */ 812 #define MP_BOARD_RESET_MAGIC 0x10000 813 814 typedef struct mv88w8618_timer_state { 815 ptimer_state *ptimer; 816 uint32_t limit; 817 int freq; 818 qemu_irq irq; 819 } mv88w8618_timer_state; 820 821 #define TYPE_MV88W8618_PIT "mv88w8618_pit" 822 #define MV88W8618_PIT(obj) \ 823 OBJECT_CHECK(mv88w8618_pit_state, (obj), TYPE_MV88W8618_PIT) 824 825 typedef struct mv88w8618_pit_state { 826 /*< private >*/ 827 SysBusDevice parent_obj; 828 /*< public >*/ 829 830 MemoryRegion iomem; 831 mv88w8618_timer_state timer[4]; 832 } mv88w8618_pit_state; 833 834 static void mv88w8618_timer_tick(void *opaque) 835 { 836 mv88w8618_timer_state *s = opaque; 837 838 qemu_irq_raise(s->irq); 839 } 840 841 static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s, 842 uint32_t freq) 843 { 844 QEMUBH *bh; 845 846 sysbus_init_irq(dev, &s->irq); 847 s->freq = freq; 848 849 bh = qemu_bh_new(mv88w8618_timer_tick, s); 850 s->ptimer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); 851 } 852 853 static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset, 854 unsigned size) 855 { 856 mv88w8618_pit_state *s = opaque; 857 mv88w8618_timer_state *t; 858 859 switch (offset) { 860 case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE: 861 t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2]; 862 return ptimer_get_count(t->ptimer); 863 864 default: 865 return 0; 866 } 867 } 868 869 static void mv88w8618_pit_write(void *opaque, hwaddr offset, 870 uint64_t value, unsigned size) 871 { 872 mv88w8618_pit_state *s = opaque; 873 mv88w8618_timer_state *t; 874 int i; 875 876 switch (offset) { 877 case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH: 878 t = &s->timer[offset >> 2]; 879 t->limit = value; 880 if (t->limit > 0) { 881 ptimer_set_limit(t->ptimer, t->limit, 1); 882 } else { 883 ptimer_stop(t->ptimer); 884 } 885 break; 886 887 case MP_PIT_CONTROL: 888 for (i = 0; i < 4; i++) { 889 t = &s->timer[i]; 890 if (value & 0xf && t->limit > 0) { 891 ptimer_set_limit(t->ptimer, t->limit, 0); 892 ptimer_set_freq(t->ptimer, t->freq); 893 ptimer_run(t->ptimer, 0); 894 } else { 895 ptimer_stop(t->ptimer); 896 } 897 value >>= 4; 898 } 899 break; 900 901 case MP_BOARD_RESET: 902 if (value == MP_BOARD_RESET_MAGIC) { 903 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 904 } 905 break; 906 } 907 } 908 909 static void mv88w8618_pit_reset(DeviceState *d) 910 { 911 mv88w8618_pit_state *s = MV88W8618_PIT(d); 912 int i; 913 914 for (i = 0; i < 4; i++) { 915 ptimer_stop(s->timer[i].ptimer); 916 s->timer[i].limit = 0; 917 } 918 } 919 920 static const MemoryRegionOps mv88w8618_pit_ops = { 921 .read = mv88w8618_pit_read, 922 .write = mv88w8618_pit_write, 923 .endianness = DEVICE_NATIVE_ENDIAN, 924 }; 925 926 static void mv88w8618_pit_init(Object *obj) 927 { 928 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 929 mv88w8618_pit_state *s = MV88W8618_PIT(dev); 930 int i; 931 932 /* Letting them all run at 1 MHz is likely just a pragmatic 933 * simplification. */ 934 for (i = 0; i < 4; i++) { 935 mv88w8618_timer_init(dev, &s->timer[i], 1000000); 936 } 937 938 memory_region_init_io(&s->iomem, obj, &mv88w8618_pit_ops, s, 939 "musicpal-pit", MP_PIT_SIZE); 940 sysbus_init_mmio(dev, &s->iomem); 941 } 942 943 static const VMStateDescription mv88w8618_timer_vmsd = { 944 .name = "timer", 945 .version_id = 1, 946 .minimum_version_id = 1, 947 .fields = (VMStateField[]) { 948 VMSTATE_PTIMER(ptimer, mv88w8618_timer_state), 949 VMSTATE_UINT32(limit, mv88w8618_timer_state), 950 VMSTATE_END_OF_LIST() 951 } 952 }; 953 954 static const VMStateDescription mv88w8618_pit_vmsd = { 955 .name = "mv88w8618_pit", 956 .version_id = 1, 957 .minimum_version_id = 1, 958 .fields = (VMStateField[]) { 959 VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1, 960 mv88w8618_timer_vmsd, mv88w8618_timer_state), 961 VMSTATE_END_OF_LIST() 962 } 963 }; 964 965 static void mv88w8618_pit_class_init(ObjectClass *klass, void *data) 966 { 967 DeviceClass *dc = DEVICE_CLASS(klass); 968 969 dc->reset = mv88w8618_pit_reset; 970 dc->vmsd = &mv88w8618_pit_vmsd; 971 } 972 973 static const TypeInfo mv88w8618_pit_info = { 974 .name = TYPE_MV88W8618_PIT, 975 .parent = TYPE_SYS_BUS_DEVICE, 976 .instance_size = sizeof(mv88w8618_pit_state), 977 .instance_init = mv88w8618_pit_init, 978 .class_init = mv88w8618_pit_class_init, 979 }; 980 981 /* Flash config register offsets */ 982 #define MP_FLASHCFG_CFGR0 0x04 983 984 #define TYPE_MV88W8618_FLASHCFG "mv88w8618_flashcfg" 985 #define MV88W8618_FLASHCFG(obj) \ 986 OBJECT_CHECK(mv88w8618_flashcfg_state, (obj), TYPE_MV88W8618_FLASHCFG) 987 988 typedef struct mv88w8618_flashcfg_state { 989 /*< private >*/ 990 SysBusDevice parent_obj; 991 /*< public >*/ 992 993 MemoryRegion iomem; 994 uint32_t cfgr0; 995 } mv88w8618_flashcfg_state; 996 997 static uint64_t mv88w8618_flashcfg_read(void *opaque, 998 hwaddr offset, 999 unsigned size) 1000 { 1001 mv88w8618_flashcfg_state *s = opaque; 1002 1003 switch (offset) { 1004 case MP_FLASHCFG_CFGR0: 1005 return s->cfgr0; 1006 1007 default: 1008 return 0; 1009 } 1010 } 1011 1012 static void mv88w8618_flashcfg_write(void *opaque, hwaddr offset, 1013 uint64_t value, unsigned size) 1014 { 1015 mv88w8618_flashcfg_state *s = opaque; 1016 1017 switch (offset) { 1018 case MP_FLASHCFG_CFGR0: 1019 s->cfgr0 = value; 1020 break; 1021 } 1022 } 1023 1024 static const MemoryRegionOps mv88w8618_flashcfg_ops = { 1025 .read = mv88w8618_flashcfg_read, 1026 .write = mv88w8618_flashcfg_write, 1027 .endianness = DEVICE_NATIVE_ENDIAN, 1028 }; 1029 1030 static void mv88w8618_flashcfg_init(Object *obj) 1031 { 1032 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 1033 mv88w8618_flashcfg_state *s = MV88W8618_FLASHCFG(dev); 1034 1035 s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */ 1036 memory_region_init_io(&s->iomem, obj, &mv88w8618_flashcfg_ops, s, 1037 "musicpal-flashcfg", MP_FLASHCFG_SIZE); 1038 sysbus_init_mmio(dev, &s->iomem); 1039 } 1040 1041 static const VMStateDescription mv88w8618_flashcfg_vmsd = { 1042 .name = "mv88w8618_flashcfg", 1043 .version_id = 1, 1044 .minimum_version_id = 1, 1045 .fields = (VMStateField[]) { 1046 VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state), 1047 VMSTATE_END_OF_LIST() 1048 } 1049 }; 1050 1051 static void mv88w8618_flashcfg_class_init(ObjectClass *klass, void *data) 1052 { 1053 DeviceClass *dc = DEVICE_CLASS(klass); 1054 1055 dc->vmsd = &mv88w8618_flashcfg_vmsd; 1056 } 1057 1058 static const TypeInfo mv88w8618_flashcfg_info = { 1059 .name = TYPE_MV88W8618_FLASHCFG, 1060 .parent = TYPE_SYS_BUS_DEVICE, 1061 .instance_size = sizeof(mv88w8618_flashcfg_state), 1062 .instance_init = mv88w8618_flashcfg_init, 1063 .class_init = mv88w8618_flashcfg_class_init, 1064 }; 1065 1066 /* Misc register offsets */ 1067 #define MP_MISC_BOARD_REVISION 0x18 1068 1069 #define MP_BOARD_REVISION 0x31 1070 1071 typedef struct { 1072 SysBusDevice parent_obj; 1073 MemoryRegion iomem; 1074 } MusicPalMiscState; 1075 1076 #define TYPE_MUSICPAL_MISC "musicpal-misc" 1077 #define MUSICPAL_MISC(obj) \ 1078 OBJECT_CHECK(MusicPalMiscState, (obj), TYPE_MUSICPAL_MISC) 1079 1080 static uint64_t musicpal_misc_read(void *opaque, hwaddr offset, 1081 unsigned size) 1082 { 1083 switch (offset) { 1084 case MP_MISC_BOARD_REVISION: 1085 return MP_BOARD_REVISION; 1086 1087 default: 1088 return 0; 1089 } 1090 } 1091 1092 static void musicpal_misc_write(void *opaque, hwaddr offset, 1093 uint64_t value, unsigned size) 1094 { 1095 } 1096 1097 static const MemoryRegionOps musicpal_misc_ops = { 1098 .read = musicpal_misc_read, 1099 .write = musicpal_misc_write, 1100 .endianness = DEVICE_NATIVE_ENDIAN, 1101 }; 1102 1103 static void musicpal_misc_init(Object *obj) 1104 { 1105 SysBusDevice *sd = SYS_BUS_DEVICE(obj); 1106 MusicPalMiscState *s = MUSICPAL_MISC(obj); 1107 1108 memory_region_init_io(&s->iomem, OBJECT(s), &musicpal_misc_ops, NULL, 1109 "musicpal-misc", MP_MISC_SIZE); 1110 sysbus_init_mmio(sd, &s->iomem); 1111 } 1112 1113 static const TypeInfo musicpal_misc_info = { 1114 .name = TYPE_MUSICPAL_MISC, 1115 .parent = TYPE_SYS_BUS_DEVICE, 1116 .instance_init = musicpal_misc_init, 1117 .instance_size = sizeof(MusicPalMiscState), 1118 }; 1119 1120 /* WLAN register offsets */ 1121 #define MP_WLAN_MAGIC1 0x11c 1122 #define MP_WLAN_MAGIC2 0x124 1123 1124 static uint64_t mv88w8618_wlan_read(void *opaque, hwaddr offset, 1125 unsigned size) 1126 { 1127 switch (offset) { 1128 /* Workaround to allow loading the binary-only wlandrv.ko crap 1129 * from the original Freecom firmware. */ 1130 case MP_WLAN_MAGIC1: 1131 return ~3; 1132 case MP_WLAN_MAGIC2: 1133 return -1; 1134 1135 default: 1136 return 0; 1137 } 1138 } 1139 1140 static void mv88w8618_wlan_write(void *opaque, hwaddr offset, 1141 uint64_t value, unsigned size) 1142 { 1143 } 1144 1145 static const MemoryRegionOps mv88w8618_wlan_ops = { 1146 .read = mv88w8618_wlan_read, 1147 .write =mv88w8618_wlan_write, 1148 .endianness = DEVICE_NATIVE_ENDIAN, 1149 }; 1150 1151 static void mv88w8618_wlan_realize(DeviceState *dev, Error **errp) 1152 { 1153 MemoryRegion *iomem = g_new(MemoryRegion, 1); 1154 1155 memory_region_init_io(iomem, OBJECT(dev), &mv88w8618_wlan_ops, NULL, 1156 "musicpal-wlan", MP_WLAN_SIZE); 1157 sysbus_init_mmio(SYS_BUS_DEVICE(dev), iomem); 1158 } 1159 1160 /* GPIO register offsets */ 1161 #define MP_GPIO_OE_LO 0x008 1162 #define MP_GPIO_OUT_LO 0x00c 1163 #define MP_GPIO_IN_LO 0x010 1164 #define MP_GPIO_IER_LO 0x014 1165 #define MP_GPIO_IMR_LO 0x018 1166 #define MP_GPIO_ISR_LO 0x020 1167 #define MP_GPIO_OE_HI 0x508 1168 #define MP_GPIO_OUT_HI 0x50c 1169 #define MP_GPIO_IN_HI 0x510 1170 #define MP_GPIO_IER_HI 0x514 1171 #define MP_GPIO_IMR_HI 0x518 1172 #define MP_GPIO_ISR_HI 0x520 1173 1174 /* GPIO bits & masks */ 1175 #define MP_GPIO_LCD_BRIGHTNESS 0x00070000 1176 #define MP_GPIO_I2C_DATA_BIT 29 1177 #define MP_GPIO_I2C_CLOCK_BIT 30 1178 1179 /* LCD brightness bits in GPIO_OE_HI */ 1180 #define MP_OE_LCD_BRIGHTNESS 0x0007 1181 1182 #define TYPE_MUSICPAL_GPIO "musicpal_gpio" 1183 #define MUSICPAL_GPIO(obj) \ 1184 OBJECT_CHECK(musicpal_gpio_state, (obj), TYPE_MUSICPAL_GPIO) 1185 1186 typedef struct musicpal_gpio_state { 1187 /*< private >*/ 1188 SysBusDevice parent_obj; 1189 /*< public >*/ 1190 1191 MemoryRegion iomem; 1192 uint32_t lcd_brightness; 1193 uint32_t out_state; 1194 uint32_t in_state; 1195 uint32_t ier; 1196 uint32_t imr; 1197 uint32_t isr; 1198 qemu_irq irq; 1199 qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */ 1200 } musicpal_gpio_state; 1201 1202 static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) { 1203 int i; 1204 uint32_t brightness; 1205 1206 /* compute brightness ratio */ 1207 switch (s->lcd_brightness) { 1208 case 0x00000007: 1209 brightness = 0; 1210 break; 1211 1212 case 0x00020000: 1213 brightness = 1; 1214 break; 1215 1216 case 0x00020001: 1217 brightness = 2; 1218 break; 1219 1220 case 0x00040000: 1221 brightness = 3; 1222 break; 1223 1224 case 0x00010006: 1225 brightness = 4; 1226 break; 1227 1228 case 0x00020005: 1229 brightness = 5; 1230 break; 1231 1232 case 0x00040003: 1233 brightness = 6; 1234 break; 1235 1236 case 0x00030004: 1237 default: 1238 brightness = 7; 1239 } 1240 1241 /* set lcd brightness GPIOs */ 1242 for (i = 0; i <= 2; i++) { 1243 qemu_set_irq(s->out[i], (brightness >> i) & 1); 1244 } 1245 } 1246 1247 static void musicpal_gpio_pin_event(void *opaque, int pin, int level) 1248 { 1249 musicpal_gpio_state *s = opaque; 1250 uint32_t mask = 1 << pin; 1251 uint32_t delta = level << pin; 1252 uint32_t old = s->in_state & mask; 1253 1254 s->in_state &= ~mask; 1255 s->in_state |= delta; 1256 1257 if ((old ^ delta) && 1258 ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) { 1259 s->isr = mask; 1260 qemu_irq_raise(s->irq); 1261 } 1262 } 1263 1264 static uint64_t musicpal_gpio_read(void *opaque, hwaddr offset, 1265 unsigned size) 1266 { 1267 musicpal_gpio_state *s = opaque; 1268 1269 switch (offset) { 1270 case MP_GPIO_OE_HI: /* used for LCD brightness control */ 1271 return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS; 1272 1273 case MP_GPIO_OUT_LO: 1274 return s->out_state & 0xFFFF; 1275 case MP_GPIO_OUT_HI: 1276 return s->out_state >> 16; 1277 1278 case MP_GPIO_IN_LO: 1279 return s->in_state & 0xFFFF; 1280 case MP_GPIO_IN_HI: 1281 return s->in_state >> 16; 1282 1283 case MP_GPIO_IER_LO: 1284 return s->ier & 0xFFFF; 1285 case MP_GPIO_IER_HI: 1286 return s->ier >> 16; 1287 1288 case MP_GPIO_IMR_LO: 1289 return s->imr & 0xFFFF; 1290 case MP_GPIO_IMR_HI: 1291 return s->imr >> 16; 1292 1293 case MP_GPIO_ISR_LO: 1294 return s->isr & 0xFFFF; 1295 case MP_GPIO_ISR_HI: 1296 return s->isr >> 16; 1297 1298 default: 1299 return 0; 1300 } 1301 } 1302 1303 static void musicpal_gpio_write(void *opaque, hwaddr offset, 1304 uint64_t value, unsigned size) 1305 { 1306 musicpal_gpio_state *s = opaque; 1307 switch (offset) { 1308 case MP_GPIO_OE_HI: /* used for LCD brightness control */ 1309 s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) | 1310 (value & MP_OE_LCD_BRIGHTNESS); 1311 musicpal_gpio_brightness_update(s); 1312 break; 1313 1314 case MP_GPIO_OUT_LO: 1315 s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF); 1316 break; 1317 case MP_GPIO_OUT_HI: 1318 s->out_state = (s->out_state & 0xFFFF) | (value << 16); 1319 s->lcd_brightness = (s->lcd_brightness & 0xFFFF) | 1320 (s->out_state & MP_GPIO_LCD_BRIGHTNESS); 1321 musicpal_gpio_brightness_update(s); 1322 qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1); 1323 qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1); 1324 break; 1325 1326 case MP_GPIO_IER_LO: 1327 s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF); 1328 break; 1329 case MP_GPIO_IER_HI: 1330 s->ier = (s->ier & 0xFFFF) | (value << 16); 1331 break; 1332 1333 case MP_GPIO_IMR_LO: 1334 s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF); 1335 break; 1336 case MP_GPIO_IMR_HI: 1337 s->imr = (s->imr & 0xFFFF) | (value << 16); 1338 break; 1339 } 1340 } 1341 1342 static const MemoryRegionOps musicpal_gpio_ops = { 1343 .read = musicpal_gpio_read, 1344 .write = musicpal_gpio_write, 1345 .endianness = DEVICE_NATIVE_ENDIAN, 1346 }; 1347 1348 static void musicpal_gpio_reset(DeviceState *d) 1349 { 1350 musicpal_gpio_state *s = MUSICPAL_GPIO(d); 1351 1352 s->lcd_brightness = 0; 1353 s->out_state = 0; 1354 s->in_state = 0xffffffff; 1355 s->ier = 0; 1356 s->imr = 0; 1357 s->isr = 0; 1358 } 1359 1360 static void musicpal_gpio_init(Object *obj) 1361 { 1362 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1363 DeviceState *dev = DEVICE(sbd); 1364 musicpal_gpio_state *s = MUSICPAL_GPIO(dev); 1365 1366 sysbus_init_irq(sbd, &s->irq); 1367 1368 memory_region_init_io(&s->iomem, obj, &musicpal_gpio_ops, s, 1369 "musicpal-gpio", MP_GPIO_SIZE); 1370 sysbus_init_mmio(sbd, &s->iomem); 1371 1372 qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out)); 1373 1374 qdev_init_gpio_in(dev, musicpal_gpio_pin_event, 32); 1375 } 1376 1377 static const VMStateDescription musicpal_gpio_vmsd = { 1378 .name = "musicpal_gpio", 1379 .version_id = 1, 1380 .minimum_version_id = 1, 1381 .fields = (VMStateField[]) { 1382 VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state), 1383 VMSTATE_UINT32(out_state, musicpal_gpio_state), 1384 VMSTATE_UINT32(in_state, musicpal_gpio_state), 1385 VMSTATE_UINT32(ier, musicpal_gpio_state), 1386 VMSTATE_UINT32(imr, musicpal_gpio_state), 1387 VMSTATE_UINT32(isr, musicpal_gpio_state), 1388 VMSTATE_END_OF_LIST() 1389 } 1390 }; 1391 1392 static void musicpal_gpio_class_init(ObjectClass *klass, void *data) 1393 { 1394 DeviceClass *dc = DEVICE_CLASS(klass); 1395 1396 dc->reset = musicpal_gpio_reset; 1397 dc->vmsd = &musicpal_gpio_vmsd; 1398 } 1399 1400 static const TypeInfo musicpal_gpio_info = { 1401 .name = TYPE_MUSICPAL_GPIO, 1402 .parent = TYPE_SYS_BUS_DEVICE, 1403 .instance_size = sizeof(musicpal_gpio_state), 1404 .instance_init = musicpal_gpio_init, 1405 .class_init = musicpal_gpio_class_init, 1406 }; 1407 1408 /* Keyboard codes & masks */ 1409 #define KEY_RELEASED 0x80 1410 #define KEY_CODE 0x7f 1411 1412 #define KEYCODE_TAB 0x0f 1413 #define KEYCODE_ENTER 0x1c 1414 #define KEYCODE_F 0x21 1415 #define KEYCODE_M 0x32 1416 1417 #define KEYCODE_EXTENDED 0xe0 1418 #define KEYCODE_UP 0x48 1419 #define KEYCODE_DOWN 0x50 1420 #define KEYCODE_LEFT 0x4b 1421 #define KEYCODE_RIGHT 0x4d 1422 1423 #define MP_KEY_WHEEL_VOL (1 << 0) 1424 #define MP_KEY_WHEEL_VOL_INV (1 << 1) 1425 #define MP_KEY_WHEEL_NAV (1 << 2) 1426 #define MP_KEY_WHEEL_NAV_INV (1 << 3) 1427 #define MP_KEY_BTN_FAVORITS (1 << 4) 1428 #define MP_KEY_BTN_MENU (1 << 5) 1429 #define MP_KEY_BTN_VOLUME (1 << 6) 1430 #define MP_KEY_BTN_NAVIGATION (1 << 7) 1431 1432 #define TYPE_MUSICPAL_KEY "musicpal_key" 1433 #define MUSICPAL_KEY(obj) \ 1434 OBJECT_CHECK(musicpal_key_state, (obj), TYPE_MUSICPAL_KEY) 1435 1436 typedef struct musicpal_key_state { 1437 /*< private >*/ 1438 SysBusDevice parent_obj; 1439 /*< public >*/ 1440 1441 MemoryRegion iomem; 1442 uint32_t kbd_extended; 1443 uint32_t pressed_keys; 1444 qemu_irq out[8]; 1445 } musicpal_key_state; 1446 1447 static void musicpal_key_event(void *opaque, int keycode) 1448 { 1449 musicpal_key_state *s = opaque; 1450 uint32_t event = 0; 1451 int i; 1452 1453 if (keycode == KEYCODE_EXTENDED) { 1454 s->kbd_extended = 1; 1455 return; 1456 } 1457 1458 if (s->kbd_extended) { 1459 switch (keycode & KEY_CODE) { 1460 case KEYCODE_UP: 1461 event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV; 1462 break; 1463 1464 case KEYCODE_DOWN: 1465 event = MP_KEY_WHEEL_NAV; 1466 break; 1467 1468 case KEYCODE_LEFT: 1469 event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV; 1470 break; 1471 1472 case KEYCODE_RIGHT: 1473 event = MP_KEY_WHEEL_VOL; 1474 break; 1475 } 1476 } else { 1477 switch (keycode & KEY_CODE) { 1478 case KEYCODE_F: 1479 event = MP_KEY_BTN_FAVORITS; 1480 break; 1481 1482 case KEYCODE_TAB: 1483 event = MP_KEY_BTN_VOLUME; 1484 break; 1485 1486 case KEYCODE_ENTER: 1487 event = MP_KEY_BTN_NAVIGATION; 1488 break; 1489 1490 case KEYCODE_M: 1491 event = MP_KEY_BTN_MENU; 1492 break; 1493 } 1494 /* Do not repeat already pressed buttons */ 1495 if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) { 1496 event = 0; 1497 } 1498 } 1499 1500 if (event) { 1501 /* Raise GPIO pin first if repeating a key */ 1502 if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) { 1503 for (i = 0; i <= 7; i++) { 1504 if (event & (1 << i)) { 1505 qemu_set_irq(s->out[i], 1); 1506 } 1507 } 1508 } 1509 for (i = 0; i <= 7; i++) { 1510 if (event & (1 << i)) { 1511 qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED)); 1512 } 1513 } 1514 if (keycode & KEY_RELEASED) { 1515 s->pressed_keys &= ~event; 1516 } else { 1517 s->pressed_keys |= event; 1518 } 1519 } 1520 1521 s->kbd_extended = 0; 1522 } 1523 1524 static void musicpal_key_init(Object *obj) 1525 { 1526 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1527 DeviceState *dev = DEVICE(sbd); 1528 musicpal_key_state *s = MUSICPAL_KEY(dev); 1529 1530 memory_region_init(&s->iomem, obj, "dummy", 0); 1531 sysbus_init_mmio(sbd, &s->iomem); 1532 1533 s->kbd_extended = 0; 1534 s->pressed_keys = 0; 1535 1536 qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out)); 1537 1538 qemu_add_kbd_event_handler(musicpal_key_event, s); 1539 } 1540 1541 static const VMStateDescription musicpal_key_vmsd = { 1542 .name = "musicpal_key", 1543 .version_id = 1, 1544 .minimum_version_id = 1, 1545 .fields = (VMStateField[]) { 1546 VMSTATE_UINT32(kbd_extended, musicpal_key_state), 1547 VMSTATE_UINT32(pressed_keys, musicpal_key_state), 1548 VMSTATE_END_OF_LIST() 1549 } 1550 }; 1551 1552 static void musicpal_key_class_init(ObjectClass *klass, void *data) 1553 { 1554 DeviceClass *dc = DEVICE_CLASS(klass); 1555 1556 dc->vmsd = &musicpal_key_vmsd; 1557 } 1558 1559 static const TypeInfo musicpal_key_info = { 1560 .name = TYPE_MUSICPAL_KEY, 1561 .parent = TYPE_SYS_BUS_DEVICE, 1562 .instance_size = sizeof(musicpal_key_state), 1563 .instance_init = musicpal_key_init, 1564 .class_init = musicpal_key_class_init, 1565 }; 1566 1567 static struct arm_boot_info musicpal_binfo = { 1568 .loader_start = 0x0, 1569 .board_id = 0x20e, 1570 }; 1571 1572 static void musicpal_init(MachineState *machine) 1573 { 1574 const char *kernel_filename = machine->kernel_filename; 1575 const char *kernel_cmdline = machine->kernel_cmdline; 1576 const char *initrd_filename = machine->initrd_filename; 1577 ARMCPU *cpu; 1578 qemu_irq pic[32]; 1579 DeviceState *dev; 1580 DeviceState *i2c_dev; 1581 DeviceState *lcd_dev; 1582 DeviceState *key_dev; 1583 DeviceState *wm8750_dev; 1584 SysBusDevice *s; 1585 I2CBus *i2c; 1586 int i; 1587 unsigned long flash_size; 1588 DriveInfo *dinfo; 1589 MemoryRegion *address_space_mem = get_system_memory(); 1590 MemoryRegion *ram = g_new(MemoryRegion, 1); 1591 MemoryRegion *sram = g_new(MemoryRegion, 1); 1592 1593 cpu = ARM_CPU(cpu_create(machine->cpu_type)); 1594 1595 /* For now we use a fixed - the original - RAM size */ 1596 memory_region_allocate_system_memory(ram, NULL, "musicpal.ram", 1597 MP_RAM_DEFAULT_SIZE); 1598 memory_region_add_subregion(address_space_mem, 0, ram); 1599 1600 memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE, 1601 &error_fatal); 1602 memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram); 1603 1604 dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE, 1605 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); 1606 for (i = 0; i < 32; i++) { 1607 pic[i] = qdev_get_gpio_in(dev, i); 1608 } 1609 sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ], 1610 pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], 1611 pic[MP_TIMER4_IRQ], NULL); 1612 1613 if (serial_hd(0)) { 1614 serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1615 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN); 1616 } 1617 if (serial_hd(1)) { 1618 serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1619 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN); 1620 } 1621 1622 /* Register flash */ 1623 dinfo = drive_get(IF_PFLASH, 0, 0); 1624 if (dinfo) { 1625 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 1626 1627 flash_size = blk_getlength(blk); 1628 if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 && 1629 flash_size != 32*1024*1024) { 1630 error_report("Invalid flash image size"); 1631 exit(1); 1632 } 1633 1634 /* 1635 * The original U-Boot accesses the flash at 0xFE000000 instead of 1636 * 0xFF800000 (if there is 8 MB flash). So remap flash access if the 1637 * image is smaller than 32 MB. 1638 */ 1639 #ifdef TARGET_WORDS_BIGENDIAN 1640 pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX, 1641 "musicpal.flash", flash_size, 1642 blk, 0x10000, 1643 MP_FLASH_SIZE_MAX / flash_size, 1644 2, 0x00BF, 0x236D, 0x0000, 0x0000, 1645 0x5555, 0x2AAA, 1); 1646 #else 1647 pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX, 1648 "musicpal.flash", flash_size, 1649 blk, 0x10000, 1650 MP_FLASH_SIZE_MAX / flash_size, 1651 2, 0x00BF, 0x236D, 0x0000, 0x0000, 1652 0x5555, 0x2AAA, 0); 1653 #endif 1654 1655 } 1656 sysbus_create_simple(TYPE_MV88W8618_FLASHCFG, MP_FLASHCFG_BASE, NULL); 1657 1658 qemu_check_nic_model(&nd_table[0], "mv88w8618"); 1659 dev = qdev_create(NULL, TYPE_MV88W8618_ETH); 1660 qdev_set_nic_properties(dev, &nd_table[0]); 1661 qdev_init_nofail(dev); 1662 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE); 1663 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]); 1664 1665 sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); 1666 1667 sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL); 1668 1669 dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE, 1670 pic[MP_GPIO_IRQ]); 1671 i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL); 1672 i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c"); 1673 1674 lcd_dev = sysbus_create_simple(TYPE_MUSICPAL_LCD, MP_LCD_BASE, NULL); 1675 key_dev = sysbus_create_simple(TYPE_MUSICPAL_KEY, -1, NULL); 1676 1677 /* I2C read data */ 1678 qdev_connect_gpio_out(i2c_dev, 0, 1679 qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT)); 1680 /* I2C data */ 1681 qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0)); 1682 /* I2C clock */ 1683 qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1)); 1684 1685 for (i = 0; i < 3; i++) { 1686 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i)); 1687 } 1688 for (i = 0; i < 4; i++) { 1689 qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8)); 1690 } 1691 for (i = 4; i < 8; i++) { 1692 qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15)); 1693 } 1694 1695 wm8750_dev = i2c_create_slave(i2c, TYPE_WM8750, MP_WM_ADDR); 1696 dev = qdev_create(NULL, TYPE_MV88W8618_AUDIO); 1697 s = SYS_BUS_DEVICE(dev); 1698 object_property_set_link(OBJECT(dev), OBJECT(wm8750_dev), 1699 "wm8750", NULL); 1700 qdev_init_nofail(dev); 1701 sysbus_mmio_map(s, 0, MP_AUDIO_BASE); 1702 sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]); 1703 1704 musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; 1705 musicpal_binfo.kernel_filename = kernel_filename; 1706 musicpal_binfo.kernel_cmdline = kernel_cmdline; 1707 musicpal_binfo.initrd_filename = initrd_filename; 1708 arm_load_kernel(cpu, &musicpal_binfo); 1709 } 1710 1711 static void musicpal_machine_init(MachineClass *mc) 1712 { 1713 mc->desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)"; 1714 mc->init = musicpal_init; 1715 mc->ignore_memory_transaction_failures = true; 1716 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 1717 } 1718 1719 DEFINE_MACHINE("musicpal", musicpal_machine_init) 1720 1721 static void mv88w8618_wlan_class_init(ObjectClass *klass, void *data) 1722 { 1723 DeviceClass *dc = DEVICE_CLASS(klass); 1724 1725 dc->realize = mv88w8618_wlan_realize; 1726 } 1727 1728 static const TypeInfo mv88w8618_wlan_info = { 1729 .name = "mv88w8618_wlan", 1730 .parent = TYPE_SYS_BUS_DEVICE, 1731 .instance_size = sizeof(SysBusDevice), 1732 .class_init = mv88w8618_wlan_class_init, 1733 }; 1734 1735 static void musicpal_register_types(void) 1736 { 1737 type_register_static(&mv88w8618_pic_info); 1738 type_register_static(&mv88w8618_pit_info); 1739 type_register_static(&mv88w8618_flashcfg_info); 1740 type_register_static(&mv88w8618_eth_info); 1741 type_register_static(&mv88w8618_wlan_info); 1742 type_register_static(&musicpal_lcd_info); 1743 type_register_static(&musicpal_gpio_info); 1744 type_register_static(&musicpal_key_info); 1745 type_register_static(&musicpal_misc_info); 1746 } 1747 1748 type_init(musicpal_register_types) 1749