1 /* 2 * Marvell MV88W8618 / Freecom MusicPal emulation. 3 * 4 * Copyright (c) 2008 Jan Kiszka 5 * 6 * This code is licensed under the GNU GPL v2. 7 * 8 * Contributions after 2012-01-13 are licensed under the terms of the 9 * GNU GPL, version 2 or (at your option) any later version. 10 */ 11 12 #include "hw/sysbus.h" 13 #include "hw/arm/arm.h" 14 #include "hw/devices.h" 15 #include "net/net.h" 16 #include "sysemu/sysemu.h" 17 #include "hw/boards.h" 18 #include "hw/char/serial.h" 19 #include "qemu/timer.h" 20 #include "hw/ptimer.h" 21 #include "block/block.h" 22 #include "hw/block/flash.h" 23 #include "ui/console.h" 24 #include "hw/i2c/i2c.h" 25 #include "sysemu/blockdev.h" 26 #include "exec/address-spaces.h" 27 #include "ui/pixel_ops.h" 28 29 #define MP_MISC_BASE 0x80002000 30 #define MP_MISC_SIZE 0x00001000 31 32 #define MP_ETH_BASE 0x80008000 33 #define MP_ETH_SIZE 0x00001000 34 35 #define MP_WLAN_BASE 0x8000C000 36 #define MP_WLAN_SIZE 0x00000800 37 38 #define MP_UART1_BASE 0x8000C840 39 #define MP_UART2_BASE 0x8000C940 40 41 #define MP_GPIO_BASE 0x8000D000 42 #define MP_GPIO_SIZE 0x00001000 43 44 #define MP_FLASHCFG_BASE 0x90006000 45 #define MP_FLASHCFG_SIZE 0x00001000 46 47 #define MP_AUDIO_BASE 0x90007000 48 49 #define MP_PIC_BASE 0x90008000 50 #define MP_PIC_SIZE 0x00001000 51 52 #define MP_PIT_BASE 0x90009000 53 #define MP_PIT_SIZE 0x00001000 54 55 #define MP_LCD_BASE 0x9000c000 56 #define MP_LCD_SIZE 0x00001000 57 58 #define MP_SRAM_BASE 0xC0000000 59 #define MP_SRAM_SIZE 0x00020000 60 61 #define MP_RAM_DEFAULT_SIZE 32*1024*1024 62 #define MP_FLASH_SIZE_MAX 32*1024*1024 63 64 #define MP_TIMER1_IRQ 4 65 #define MP_TIMER2_IRQ 5 66 #define MP_TIMER3_IRQ 6 67 #define MP_TIMER4_IRQ 7 68 #define MP_EHCI_IRQ 8 69 #define MP_ETH_IRQ 9 70 #define MP_UART1_IRQ 11 71 #define MP_UART2_IRQ 11 72 #define MP_GPIO_IRQ 12 73 #define MP_RTC_IRQ 28 74 #define MP_AUDIO_IRQ 30 75 76 /* Wolfson 8750 I2C address */ 77 #define MP_WM_ADDR 0x1A 78 79 /* Ethernet register offsets */ 80 #define MP_ETH_SMIR 0x010 81 #define MP_ETH_PCXR 0x408 82 #define MP_ETH_SDCMR 0x448 83 #define MP_ETH_ICR 0x450 84 #define MP_ETH_IMR 0x458 85 #define MP_ETH_FRDP0 0x480 86 #define MP_ETH_FRDP1 0x484 87 #define MP_ETH_FRDP2 0x488 88 #define MP_ETH_FRDP3 0x48C 89 #define MP_ETH_CRDP0 0x4A0 90 #define MP_ETH_CRDP1 0x4A4 91 #define MP_ETH_CRDP2 0x4A8 92 #define MP_ETH_CRDP3 0x4AC 93 #define MP_ETH_CTDP0 0x4E0 94 #define MP_ETH_CTDP1 0x4E4 95 96 /* MII PHY access */ 97 #define MP_ETH_SMIR_DATA 0x0000FFFF 98 #define MP_ETH_SMIR_ADDR 0x03FF0000 99 #define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */ 100 #define MP_ETH_SMIR_RDVALID (1 << 27) 101 102 /* PHY registers */ 103 #define MP_ETH_PHY1_BMSR 0x00210000 104 #define MP_ETH_PHY1_PHYSID1 0x00410000 105 #define MP_ETH_PHY1_PHYSID2 0x00610000 106 107 #define MP_PHY_BMSR_LINK 0x0004 108 #define MP_PHY_BMSR_AUTONEG 0x0008 109 110 #define MP_PHY_88E3015 0x01410E20 111 112 /* TX descriptor status */ 113 #define MP_ETH_TX_OWN (1 << 31) 114 115 /* RX descriptor status */ 116 #define MP_ETH_RX_OWN (1 << 31) 117 118 /* Interrupt cause/mask bits */ 119 #define MP_ETH_IRQ_RX_BIT 0 120 #define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT) 121 #define MP_ETH_IRQ_TXHI_BIT 2 122 #define MP_ETH_IRQ_TXLO_BIT 3 123 124 /* Port config bits */ 125 #define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */ 126 127 /* SDMA command bits */ 128 #define MP_ETH_CMD_TXHI (1 << 23) 129 #define MP_ETH_CMD_TXLO (1 << 22) 130 131 typedef struct mv88w8618_tx_desc { 132 uint32_t cmdstat; 133 uint16_t res; 134 uint16_t bytes; 135 uint32_t buffer; 136 uint32_t next; 137 } mv88w8618_tx_desc; 138 139 typedef struct mv88w8618_rx_desc { 140 uint32_t cmdstat; 141 uint16_t bytes; 142 uint16_t buffer_size; 143 uint32_t buffer; 144 uint32_t next; 145 } mv88w8618_rx_desc; 146 147 #define TYPE_MV88W8618_ETH "mv88w8618_eth" 148 #define MV88W8618_ETH(obj) \ 149 OBJECT_CHECK(mv88w8618_eth_state, (obj), TYPE_MV88W8618_ETH) 150 151 typedef struct mv88w8618_eth_state { 152 /*< private >*/ 153 SysBusDevice parent_obj; 154 /*< public >*/ 155 156 MemoryRegion iomem; 157 qemu_irq irq; 158 uint32_t smir; 159 uint32_t icr; 160 uint32_t imr; 161 int mmio_index; 162 uint32_t vlan_header; 163 uint32_t tx_queue[2]; 164 uint32_t rx_queue[4]; 165 uint32_t frx_queue[4]; 166 uint32_t cur_rx[4]; 167 NICState *nic; 168 NICConf conf; 169 } mv88w8618_eth_state; 170 171 static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc) 172 { 173 cpu_to_le32s(&desc->cmdstat); 174 cpu_to_le16s(&desc->bytes); 175 cpu_to_le16s(&desc->buffer_size); 176 cpu_to_le32s(&desc->buffer); 177 cpu_to_le32s(&desc->next); 178 cpu_physical_memory_write(addr, desc, sizeof(*desc)); 179 } 180 181 static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc) 182 { 183 cpu_physical_memory_read(addr, desc, sizeof(*desc)); 184 le32_to_cpus(&desc->cmdstat); 185 le16_to_cpus(&desc->bytes); 186 le16_to_cpus(&desc->buffer_size); 187 le32_to_cpus(&desc->buffer); 188 le32_to_cpus(&desc->next); 189 } 190 191 static int eth_can_receive(NetClientState *nc) 192 { 193 return 1; 194 } 195 196 static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size) 197 { 198 mv88w8618_eth_state *s = qemu_get_nic_opaque(nc); 199 uint32_t desc_addr; 200 mv88w8618_rx_desc desc; 201 int i; 202 203 for (i = 0; i < 4; i++) { 204 desc_addr = s->cur_rx[i]; 205 if (!desc_addr) { 206 continue; 207 } 208 do { 209 eth_rx_desc_get(desc_addr, &desc); 210 if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) { 211 cpu_physical_memory_write(desc.buffer + s->vlan_header, 212 buf, size); 213 desc.bytes = size + s->vlan_header; 214 desc.cmdstat &= ~MP_ETH_RX_OWN; 215 s->cur_rx[i] = desc.next; 216 217 s->icr |= MP_ETH_IRQ_RX; 218 if (s->icr & s->imr) { 219 qemu_irq_raise(s->irq); 220 } 221 eth_rx_desc_put(desc_addr, &desc); 222 return size; 223 } 224 desc_addr = desc.next; 225 } while (desc_addr != s->rx_queue[i]); 226 } 227 return size; 228 } 229 230 static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc) 231 { 232 cpu_to_le32s(&desc->cmdstat); 233 cpu_to_le16s(&desc->res); 234 cpu_to_le16s(&desc->bytes); 235 cpu_to_le32s(&desc->buffer); 236 cpu_to_le32s(&desc->next); 237 cpu_physical_memory_write(addr, desc, sizeof(*desc)); 238 } 239 240 static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc) 241 { 242 cpu_physical_memory_read(addr, desc, sizeof(*desc)); 243 le32_to_cpus(&desc->cmdstat); 244 le16_to_cpus(&desc->res); 245 le16_to_cpus(&desc->bytes); 246 le32_to_cpus(&desc->buffer); 247 le32_to_cpus(&desc->next); 248 } 249 250 static void eth_send(mv88w8618_eth_state *s, int queue_index) 251 { 252 uint32_t desc_addr = s->tx_queue[queue_index]; 253 mv88w8618_tx_desc desc; 254 uint32_t next_desc; 255 uint8_t buf[2048]; 256 int len; 257 258 do { 259 eth_tx_desc_get(desc_addr, &desc); 260 next_desc = desc.next; 261 if (desc.cmdstat & MP_ETH_TX_OWN) { 262 len = desc.bytes; 263 if (len < 2048) { 264 cpu_physical_memory_read(desc.buffer, buf, len); 265 qemu_send_packet(qemu_get_queue(s->nic), buf, len); 266 } 267 desc.cmdstat &= ~MP_ETH_TX_OWN; 268 s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index); 269 eth_tx_desc_put(desc_addr, &desc); 270 } 271 desc_addr = next_desc; 272 } while (desc_addr != s->tx_queue[queue_index]); 273 } 274 275 static uint64_t mv88w8618_eth_read(void *opaque, hwaddr offset, 276 unsigned size) 277 { 278 mv88w8618_eth_state *s = opaque; 279 280 switch (offset) { 281 case MP_ETH_SMIR: 282 if (s->smir & MP_ETH_SMIR_OPCODE) { 283 switch (s->smir & MP_ETH_SMIR_ADDR) { 284 case MP_ETH_PHY1_BMSR: 285 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG | 286 MP_ETH_SMIR_RDVALID; 287 case MP_ETH_PHY1_PHYSID1: 288 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID; 289 case MP_ETH_PHY1_PHYSID2: 290 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID; 291 default: 292 return MP_ETH_SMIR_RDVALID; 293 } 294 } 295 return 0; 296 297 case MP_ETH_ICR: 298 return s->icr; 299 300 case MP_ETH_IMR: 301 return s->imr; 302 303 case MP_ETH_FRDP0 ... MP_ETH_FRDP3: 304 return s->frx_queue[(offset - MP_ETH_FRDP0)/4]; 305 306 case MP_ETH_CRDP0 ... MP_ETH_CRDP3: 307 return s->rx_queue[(offset - MP_ETH_CRDP0)/4]; 308 309 case MP_ETH_CTDP0 ... MP_ETH_CTDP1: 310 return s->tx_queue[(offset - MP_ETH_CTDP0)/4]; 311 312 default: 313 return 0; 314 } 315 } 316 317 static void mv88w8618_eth_write(void *opaque, hwaddr offset, 318 uint64_t value, unsigned size) 319 { 320 mv88w8618_eth_state *s = opaque; 321 322 switch (offset) { 323 case MP_ETH_SMIR: 324 s->smir = value; 325 break; 326 327 case MP_ETH_PCXR: 328 s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2; 329 break; 330 331 case MP_ETH_SDCMR: 332 if (value & MP_ETH_CMD_TXHI) { 333 eth_send(s, 1); 334 } 335 if (value & MP_ETH_CMD_TXLO) { 336 eth_send(s, 0); 337 } 338 if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) { 339 qemu_irq_raise(s->irq); 340 } 341 break; 342 343 case MP_ETH_ICR: 344 s->icr &= value; 345 break; 346 347 case MP_ETH_IMR: 348 s->imr = value; 349 if (s->icr & s->imr) { 350 qemu_irq_raise(s->irq); 351 } 352 break; 353 354 case MP_ETH_FRDP0 ... MP_ETH_FRDP3: 355 s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value; 356 break; 357 358 case MP_ETH_CRDP0 ... MP_ETH_CRDP3: 359 s->rx_queue[(offset - MP_ETH_CRDP0)/4] = 360 s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value; 361 break; 362 363 case MP_ETH_CTDP0 ... MP_ETH_CTDP1: 364 s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value; 365 break; 366 } 367 } 368 369 static const MemoryRegionOps mv88w8618_eth_ops = { 370 .read = mv88w8618_eth_read, 371 .write = mv88w8618_eth_write, 372 .endianness = DEVICE_NATIVE_ENDIAN, 373 }; 374 375 static void eth_cleanup(NetClientState *nc) 376 { 377 mv88w8618_eth_state *s = qemu_get_nic_opaque(nc); 378 379 s->nic = NULL; 380 } 381 382 static NetClientInfo net_mv88w8618_info = { 383 .type = NET_CLIENT_OPTIONS_KIND_NIC, 384 .size = sizeof(NICState), 385 .can_receive = eth_can_receive, 386 .receive = eth_receive, 387 .cleanup = eth_cleanup, 388 }; 389 390 static int mv88w8618_eth_init(SysBusDevice *sbd) 391 { 392 DeviceState *dev = DEVICE(sbd); 393 mv88w8618_eth_state *s = MV88W8618_ETH(dev); 394 395 sysbus_init_irq(sbd, &s->irq); 396 s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf, 397 object_get_typename(OBJECT(dev)), dev->id, s); 398 memory_region_init_io(&s->iomem, OBJECT(s), &mv88w8618_eth_ops, s, 399 "mv88w8618-eth", MP_ETH_SIZE); 400 sysbus_init_mmio(sbd, &s->iomem); 401 return 0; 402 } 403 404 static const VMStateDescription mv88w8618_eth_vmsd = { 405 .name = "mv88w8618_eth", 406 .version_id = 1, 407 .minimum_version_id = 1, 408 .minimum_version_id_old = 1, 409 .fields = (VMStateField[]) { 410 VMSTATE_UINT32(smir, mv88w8618_eth_state), 411 VMSTATE_UINT32(icr, mv88w8618_eth_state), 412 VMSTATE_UINT32(imr, mv88w8618_eth_state), 413 VMSTATE_UINT32(vlan_header, mv88w8618_eth_state), 414 VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2), 415 VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4), 416 VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4), 417 VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4), 418 VMSTATE_END_OF_LIST() 419 } 420 }; 421 422 static Property mv88w8618_eth_properties[] = { 423 DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf), 424 DEFINE_PROP_END_OF_LIST(), 425 }; 426 427 static void mv88w8618_eth_class_init(ObjectClass *klass, void *data) 428 { 429 DeviceClass *dc = DEVICE_CLASS(klass); 430 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 431 432 k->init = mv88w8618_eth_init; 433 dc->vmsd = &mv88w8618_eth_vmsd; 434 dc->props = mv88w8618_eth_properties; 435 } 436 437 static const TypeInfo mv88w8618_eth_info = { 438 .name = TYPE_MV88W8618_ETH, 439 .parent = TYPE_SYS_BUS_DEVICE, 440 .instance_size = sizeof(mv88w8618_eth_state), 441 .class_init = mv88w8618_eth_class_init, 442 }; 443 444 /* LCD register offsets */ 445 #define MP_LCD_IRQCTRL 0x180 446 #define MP_LCD_IRQSTAT 0x184 447 #define MP_LCD_SPICTRL 0x1ac 448 #define MP_LCD_INST 0x1bc 449 #define MP_LCD_DATA 0x1c0 450 451 /* Mode magics */ 452 #define MP_LCD_SPI_DATA 0x00100011 453 #define MP_LCD_SPI_CMD 0x00104011 454 #define MP_LCD_SPI_INVALID 0x00000000 455 456 /* Commmands */ 457 #define MP_LCD_INST_SETPAGE0 0xB0 458 /* ... */ 459 #define MP_LCD_INST_SETPAGE7 0xB7 460 461 #define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */ 462 463 #define TYPE_MUSICPAL_LCD "musicpal_lcd" 464 #define MUSICPAL_LCD(obj) \ 465 OBJECT_CHECK(musicpal_lcd_state, (obj), TYPE_MUSICPAL_LCD) 466 467 typedef struct musicpal_lcd_state { 468 /*< private >*/ 469 SysBusDevice parent_obj; 470 /*< public >*/ 471 472 MemoryRegion iomem; 473 uint32_t brightness; 474 uint32_t mode; 475 uint32_t irqctrl; 476 uint32_t page; 477 uint32_t page_off; 478 QemuConsole *con; 479 uint8_t video_ram[128*64/8]; 480 } musicpal_lcd_state; 481 482 static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col) 483 { 484 switch (s->brightness) { 485 case 7: 486 return col; 487 case 0: 488 return 0; 489 default: 490 return (col * s->brightness) / 7; 491 } 492 } 493 494 #define SET_LCD_PIXEL(depth, type) \ 495 static inline void glue(set_lcd_pixel, depth) \ 496 (musicpal_lcd_state *s, int x, int y, type col) \ 497 { \ 498 int dx, dy; \ 499 DisplaySurface *surface = qemu_console_surface(s->con); \ 500 type *pixel = &((type *) surface_data(surface))[(y * 128 * 3 + x) * 3]; \ 501 \ 502 for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \ 503 for (dx = 0; dx < 3; dx++, pixel++) \ 504 *pixel = col; \ 505 } 506 SET_LCD_PIXEL(8, uint8_t) 507 SET_LCD_PIXEL(16, uint16_t) 508 SET_LCD_PIXEL(32, uint32_t) 509 510 static void lcd_refresh(void *opaque) 511 { 512 musicpal_lcd_state *s = opaque; 513 DisplaySurface *surface = qemu_console_surface(s->con); 514 int x, y, col; 515 516 switch (surface_bits_per_pixel(surface)) { 517 case 0: 518 return; 519 #define LCD_REFRESH(depth, func) \ 520 case depth: \ 521 col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \ 522 scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \ 523 scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \ 524 for (x = 0; x < 128; x++) { \ 525 for (y = 0; y < 64; y++) { \ 526 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \ 527 glue(set_lcd_pixel, depth)(s, x, y, col); \ 528 } else { \ 529 glue(set_lcd_pixel, depth)(s, x, y, 0); \ 530 } \ 531 } \ 532 } \ 533 break; 534 LCD_REFRESH(8, rgb_to_pixel8) 535 LCD_REFRESH(16, rgb_to_pixel16) 536 LCD_REFRESH(32, (is_surface_bgr(surface) ? 537 rgb_to_pixel32bgr : rgb_to_pixel32)) 538 default: 539 hw_error("unsupported colour depth %i\n", 540 surface_bits_per_pixel(surface)); 541 } 542 543 dpy_gfx_update(s->con, 0, 0, 128*3, 64*3); 544 } 545 546 static void lcd_invalidate(void *opaque) 547 { 548 } 549 550 static void musicpal_lcd_gpio_brightness_in(void *opaque, int irq, int level) 551 { 552 musicpal_lcd_state *s = opaque; 553 s->brightness &= ~(1 << irq); 554 s->brightness |= level << irq; 555 } 556 557 static uint64_t musicpal_lcd_read(void *opaque, hwaddr offset, 558 unsigned size) 559 { 560 musicpal_lcd_state *s = opaque; 561 562 switch (offset) { 563 case MP_LCD_IRQCTRL: 564 return s->irqctrl; 565 566 default: 567 return 0; 568 } 569 } 570 571 static void musicpal_lcd_write(void *opaque, hwaddr offset, 572 uint64_t value, unsigned size) 573 { 574 musicpal_lcd_state *s = opaque; 575 576 switch (offset) { 577 case MP_LCD_IRQCTRL: 578 s->irqctrl = value; 579 break; 580 581 case MP_LCD_SPICTRL: 582 if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) { 583 s->mode = value; 584 } else { 585 s->mode = MP_LCD_SPI_INVALID; 586 } 587 break; 588 589 case MP_LCD_INST: 590 if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) { 591 s->page = value - MP_LCD_INST_SETPAGE0; 592 s->page_off = 0; 593 } 594 break; 595 596 case MP_LCD_DATA: 597 if (s->mode == MP_LCD_SPI_CMD) { 598 if (value >= MP_LCD_INST_SETPAGE0 && 599 value <= MP_LCD_INST_SETPAGE7) { 600 s->page = value - MP_LCD_INST_SETPAGE0; 601 s->page_off = 0; 602 } 603 } else if (s->mode == MP_LCD_SPI_DATA) { 604 s->video_ram[s->page*128 + s->page_off] = value; 605 s->page_off = (s->page_off + 1) & 127; 606 } 607 break; 608 } 609 } 610 611 static const MemoryRegionOps musicpal_lcd_ops = { 612 .read = musicpal_lcd_read, 613 .write = musicpal_lcd_write, 614 .endianness = DEVICE_NATIVE_ENDIAN, 615 }; 616 617 static const GraphicHwOps musicpal_gfx_ops = { 618 .invalidate = lcd_invalidate, 619 .gfx_update = lcd_refresh, 620 }; 621 622 static int musicpal_lcd_init(SysBusDevice *sbd) 623 { 624 DeviceState *dev = DEVICE(sbd); 625 musicpal_lcd_state *s = MUSICPAL_LCD(dev); 626 627 s->brightness = 7; 628 629 memory_region_init_io(&s->iomem, OBJECT(s), &musicpal_lcd_ops, s, 630 "musicpal-lcd", MP_LCD_SIZE); 631 sysbus_init_mmio(sbd, &s->iomem); 632 633 s->con = graphic_console_init(dev, &musicpal_gfx_ops, s); 634 qemu_console_resize(s->con, 128*3, 64*3); 635 636 qdev_init_gpio_in(dev, musicpal_lcd_gpio_brightness_in, 3); 637 638 return 0; 639 } 640 641 static const VMStateDescription musicpal_lcd_vmsd = { 642 .name = "musicpal_lcd", 643 .version_id = 1, 644 .minimum_version_id = 1, 645 .minimum_version_id_old = 1, 646 .fields = (VMStateField[]) { 647 VMSTATE_UINT32(brightness, musicpal_lcd_state), 648 VMSTATE_UINT32(mode, musicpal_lcd_state), 649 VMSTATE_UINT32(irqctrl, musicpal_lcd_state), 650 VMSTATE_UINT32(page, musicpal_lcd_state), 651 VMSTATE_UINT32(page_off, musicpal_lcd_state), 652 VMSTATE_BUFFER(video_ram, musicpal_lcd_state), 653 VMSTATE_END_OF_LIST() 654 } 655 }; 656 657 static void musicpal_lcd_class_init(ObjectClass *klass, void *data) 658 { 659 DeviceClass *dc = DEVICE_CLASS(klass); 660 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 661 662 k->init = musicpal_lcd_init; 663 dc->vmsd = &musicpal_lcd_vmsd; 664 } 665 666 static const TypeInfo musicpal_lcd_info = { 667 .name = TYPE_MUSICPAL_LCD, 668 .parent = TYPE_SYS_BUS_DEVICE, 669 .instance_size = sizeof(musicpal_lcd_state), 670 .class_init = musicpal_lcd_class_init, 671 }; 672 673 /* PIC register offsets */ 674 #define MP_PIC_STATUS 0x00 675 #define MP_PIC_ENABLE_SET 0x08 676 #define MP_PIC_ENABLE_CLR 0x0C 677 678 #define TYPE_MV88W8618_PIC "mv88w8618_pic" 679 #define MV88W8618_PIC(obj) \ 680 OBJECT_CHECK(mv88w8618_pic_state, (obj), TYPE_MV88W8618_PIC) 681 682 typedef struct mv88w8618_pic_state { 683 /*< private >*/ 684 SysBusDevice parent_obj; 685 /*< public >*/ 686 687 MemoryRegion iomem; 688 uint32_t level; 689 uint32_t enabled; 690 qemu_irq parent_irq; 691 } mv88w8618_pic_state; 692 693 static void mv88w8618_pic_update(mv88w8618_pic_state *s) 694 { 695 qemu_set_irq(s->parent_irq, (s->level & s->enabled)); 696 } 697 698 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level) 699 { 700 mv88w8618_pic_state *s = opaque; 701 702 if (level) { 703 s->level |= 1 << irq; 704 } else { 705 s->level &= ~(1 << irq); 706 } 707 mv88w8618_pic_update(s); 708 } 709 710 static uint64_t mv88w8618_pic_read(void *opaque, hwaddr offset, 711 unsigned size) 712 { 713 mv88w8618_pic_state *s = opaque; 714 715 switch (offset) { 716 case MP_PIC_STATUS: 717 return s->level & s->enabled; 718 719 default: 720 return 0; 721 } 722 } 723 724 static void mv88w8618_pic_write(void *opaque, hwaddr offset, 725 uint64_t value, unsigned size) 726 { 727 mv88w8618_pic_state *s = opaque; 728 729 switch (offset) { 730 case MP_PIC_ENABLE_SET: 731 s->enabled |= value; 732 break; 733 734 case MP_PIC_ENABLE_CLR: 735 s->enabled &= ~value; 736 s->level &= ~value; 737 break; 738 } 739 mv88w8618_pic_update(s); 740 } 741 742 static void mv88w8618_pic_reset(DeviceState *d) 743 { 744 mv88w8618_pic_state *s = MV88W8618_PIC(d); 745 746 s->level = 0; 747 s->enabled = 0; 748 } 749 750 static const MemoryRegionOps mv88w8618_pic_ops = { 751 .read = mv88w8618_pic_read, 752 .write = mv88w8618_pic_write, 753 .endianness = DEVICE_NATIVE_ENDIAN, 754 }; 755 756 static int mv88w8618_pic_init(SysBusDevice *dev) 757 { 758 mv88w8618_pic_state *s = MV88W8618_PIC(dev); 759 760 qdev_init_gpio_in(DEVICE(dev), mv88w8618_pic_set_irq, 32); 761 sysbus_init_irq(dev, &s->parent_irq); 762 memory_region_init_io(&s->iomem, OBJECT(s), &mv88w8618_pic_ops, s, 763 "musicpal-pic", MP_PIC_SIZE); 764 sysbus_init_mmio(dev, &s->iomem); 765 return 0; 766 } 767 768 static const VMStateDescription mv88w8618_pic_vmsd = { 769 .name = "mv88w8618_pic", 770 .version_id = 1, 771 .minimum_version_id = 1, 772 .minimum_version_id_old = 1, 773 .fields = (VMStateField[]) { 774 VMSTATE_UINT32(level, mv88w8618_pic_state), 775 VMSTATE_UINT32(enabled, mv88w8618_pic_state), 776 VMSTATE_END_OF_LIST() 777 } 778 }; 779 780 static void mv88w8618_pic_class_init(ObjectClass *klass, void *data) 781 { 782 DeviceClass *dc = DEVICE_CLASS(klass); 783 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 784 785 k->init = mv88w8618_pic_init; 786 dc->reset = mv88w8618_pic_reset; 787 dc->vmsd = &mv88w8618_pic_vmsd; 788 } 789 790 static const TypeInfo mv88w8618_pic_info = { 791 .name = TYPE_MV88W8618_PIC, 792 .parent = TYPE_SYS_BUS_DEVICE, 793 .instance_size = sizeof(mv88w8618_pic_state), 794 .class_init = mv88w8618_pic_class_init, 795 }; 796 797 /* PIT register offsets */ 798 #define MP_PIT_TIMER1_LENGTH 0x00 799 /* ... */ 800 #define MP_PIT_TIMER4_LENGTH 0x0C 801 #define MP_PIT_CONTROL 0x10 802 #define MP_PIT_TIMER1_VALUE 0x14 803 /* ... */ 804 #define MP_PIT_TIMER4_VALUE 0x20 805 #define MP_BOARD_RESET 0x34 806 807 /* Magic board reset value (probably some watchdog behind it) */ 808 #define MP_BOARD_RESET_MAGIC 0x10000 809 810 typedef struct mv88w8618_timer_state { 811 ptimer_state *ptimer; 812 uint32_t limit; 813 int freq; 814 qemu_irq irq; 815 } mv88w8618_timer_state; 816 817 #define TYPE_MV88W8618_PIT "mv88w8618_pit" 818 #define MV88W8618_PIT(obj) \ 819 OBJECT_CHECK(mv88w8618_pit_state, (obj), TYPE_MV88W8618_PIT) 820 821 typedef struct mv88w8618_pit_state { 822 /*< private >*/ 823 SysBusDevice parent_obj; 824 /*< public >*/ 825 826 MemoryRegion iomem; 827 mv88w8618_timer_state timer[4]; 828 } mv88w8618_pit_state; 829 830 static void mv88w8618_timer_tick(void *opaque) 831 { 832 mv88w8618_timer_state *s = opaque; 833 834 qemu_irq_raise(s->irq); 835 } 836 837 static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s, 838 uint32_t freq) 839 { 840 QEMUBH *bh; 841 842 sysbus_init_irq(dev, &s->irq); 843 s->freq = freq; 844 845 bh = qemu_bh_new(mv88w8618_timer_tick, s); 846 s->ptimer = ptimer_init(bh); 847 } 848 849 static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset, 850 unsigned size) 851 { 852 mv88w8618_pit_state *s = opaque; 853 mv88w8618_timer_state *t; 854 855 switch (offset) { 856 case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE: 857 t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2]; 858 return ptimer_get_count(t->ptimer); 859 860 default: 861 return 0; 862 } 863 } 864 865 static void mv88w8618_pit_write(void *opaque, hwaddr offset, 866 uint64_t value, unsigned size) 867 { 868 mv88w8618_pit_state *s = opaque; 869 mv88w8618_timer_state *t; 870 int i; 871 872 switch (offset) { 873 case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH: 874 t = &s->timer[offset >> 2]; 875 t->limit = value; 876 if (t->limit > 0) { 877 ptimer_set_limit(t->ptimer, t->limit, 1); 878 } else { 879 ptimer_stop(t->ptimer); 880 } 881 break; 882 883 case MP_PIT_CONTROL: 884 for (i = 0; i < 4; i++) { 885 t = &s->timer[i]; 886 if (value & 0xf && t->limit > 0) { 887 ptimer_set_limit(t->ptimer, t->limit, 0); 888 ptimer_set_freq(t->ptimer, t->freq); 889 ptimer_run(t->ptimer, 0); 890 } else { 891 ptimer_stop(t->ptimer); 892 } 893 value >>= 4; 894 } 895 break; 896 897 case MP_BOARD_RESET: 898 if (value == MP_BOARD_RESET_MAGIC) { 899 qemu_system_reset_request(); 900 } 901 break; 902 } 903 } 904 905 static void mv88w8618_pit_reset(DeviceState *d) 906 { 907 mv88w8618_pit_state *s = MV88W8618_PIT(d); 908 int i; 909 910 for (i = 0; i < 4; i++) { 911 ptimer_stop(s->timer[i].ptimer); 912 s->timer[i].limit = 0; 913 } 914 } 915 916 static const MemoryRegionOps mv88w8618_pit_ops = { 917 .read = mv88w8618_pit_read, 918 .write = mv88w8618_pit_write, 919 .endianness = DEVICE_NATIVE_ENDIAN, 920 }; 921 922 static int mv88w8618_pit_init(SysBusDevice *dev) 923 { 924 mv88w8618_pit_state *s = MV88W8618_PIT(dev); 925 int i; 926 927 /* Letting them all run at 1 MHz is likely just a pragmatic 928 * simplification. */ 929 for (i = 0; i < 4; i++) { 930 mv88w8618_timer_init(dev, &s->timer[i], 1000000); 931 } 932 933 memory_region_init_io(&s->iomem, OBJECT(s), &mv88w8618_pit_ops, s, 934 "musicpal-pit", MP_PIT_SIZE); 935 sysbus_init_mmio(dev, &s->iomem); 936 return 0; 937 } 938 939 static const VMStateDescription mv88w8618_timer_vmsd = { 940 .name = "timer", 941 .version_id = 1, 942 .minimum_version_id = 1, 943 .minimum_version_id_old = 1, 944 .fields = (VMStateField[]) { 945 VMSTATE_PTIMER(ptimer, mv88w8618_timer_state), 946 VMSTATE_UINT32(limit, mv88w8618_timer_state), 947 VMSTATE_END_OF_LIST() 948 } 949 }; 950 951 static const VMStateDescription mv88w8618_pit_vmsd = { 952 .name = "mv88w8618_pit", 953 .version_id = 1, 954 .minimum_version_id = 1, 955 .minimum_version_id_old = 1, 956 .fields = (VMStateField[]) { 957 VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1, 958 mv88w8618_timer_vmsd, mv88w8618_timer_state), 959 VMSTATE_END_OF_LIST() 960 } 961 }; 962 963 static void mv88w8618_pit_class_init(ObjectClass *klass, void *data) 964 { 965 DeviceClass *dc = DEVICE_CLASS(klass); 966 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 967 968 k->init = mv88w8618_pit_init; 969 dc->reset = mv88w8618_pit_reset; 970 dc->vmsd = &mv88w8618_pit_vmsd; 971 } 972 973 static const TypeInfo mv88w8618_pit_info = { 974 .name = TYPE_MV88W8618_PIT, 975 .parent = TYPE_SYS_BUS_DEVICE, 976 .instance_size = sizeof(mv88w8618_pit_state), 977 .class_init = mv88w8618_pit_class_init, 978 }; 979 980 /* Flash config register offsets */ 981 #define MP_FLASHCFG_CFGR0 0x04 982 983 #define TYPE_MV88W8618_FLASHCFG "mv88w8618_flashcfg" 984 #define MV88W8618_FLASHCFG(obj) \ 985 OBJECT_CHECK(mv88w8618_flashcfg_state, (obj), TYPE_MV88W8618_FLASHCFG) 986 987 typedef struct mv88w8618_flashcfg_state { 988 /*< private >*/ 989 SysBusDevice parent_obj; 990 /*< public >*/ 991 992 MemoryRegion iomem; 993 uint32_t cfgr0; 994 } mv88w8618_flashcfg_state; 995 996 static uint64_t mv88w8618_flashcfg_read(void *opaque, 997 hwaddr offset, 998 unsigned size) 999 { 1000 mv88w8618_flashcfg_state *s = opaque; 1001 1002 switch (offset) { 1003 case MP_FLASHCFG_CFGR0: 1004 return s->cfgr0; 1005 1006 default: 1007 return 0; 1008 } 1009 } 1010 1011 static void mv88w8618_flashcfg_write(void *opaque, hwaddr offset, 1012 uint64_t value, unsigned size) 1013 { 1014 mv88w8618_flashcfg_state *s = opaque; 1015 1016 switch (offset) { 1017 case MP_FLASHCFG_CFGR0: 1018 s->cfgr0 = value; 1019 break; 1020 } 1021 } 1022 1023 static const MemoryRegionOps mv88w8618_flashcfg_ops = { 1024 .read = mv88w8618_flashcfg_read, 1025 .write = mv88w8618_flashcfg_write, 1026 .endianness = DEVICE_NATIVE_ENDIAN, 1027 }; 1028 1029 static int mv88w8618_flashcfg_init(SysBusDevice *dev) 1030 { 1031 mv88w8618_flashcfg_state *s = MV88W8618_FLASHCFG(dev); 1032 1033 s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */ 1034 memory_region_init_io(&s->iomem, OBJECT(s), &mv88w8618_flashcfg_ops, s, 1035 "musicpal-flashcfg", MP_FLASHCFG_SIZE); 1036 sysbus_init_mmio(dev, &s->iomem); 1037 return 0; 1038 } 1039 1040 static const VMStateDescription mv88w8618_flashcfg_vmsd = { 1041 .name = "mv88w8618_flashcfg", 1042 .version_id = 1, 1043 .minimum_version_id = 1, 1044 .minimum_version_id_old = 1, 1045 .fields = (VMStateField[]) { 1046 VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state), 1047 VMSTATE_END_OF_LIST() 1048 } 1049 }; 1050 1051 static void mv88w8618_flashcfg_class_init(ObjectClass *klass, void *data) 1052 { 1053 DeviceClass *dc = DEVICE_CLASS(klass); 1054 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1055 1056 k->init = mv88w8618_flashcfg_init; 1057 dc->vmsd = &mv88w8618_flashcfg_vmsd; 1058 } 1059 1060 static const TypeInfo mv88w8618_flashcfg_info = { 1061 .name = TYPE_MV88W8618_FLASHCFG, 1062 .parent = TYPE_SYS_BUS_DEVICE, 1063 .instance_size = sizeof(mv88w8618_flashcfg_state), 1064 .class_init = mv88w8618_flashcfg_class_init, 1065 }; 1066 1067 /* Misc register offsets */ 1068 #define MP_MISC_BOARD_REVISION 0x18 1069 1070 #define MP_BOARD_REVISION 0x31 1071 1072 typedef struct { 1073 SysBusDevice parent_obj; 1074 MemoryRegion iomem; 1075 } MusicPalMiscState; 1076 1077 #define TYPE_MUSICPAL_MISC "musicpal-misc" 1078 #define MUSICPAL_MISC(obj) \ 1079 OBJECT_CHECK(MusicPalMiscState, (obj), TYPE_MUSICPAL_MISC) 1080 1081 static uint64_t musicpal_misc_read(void *opaque, hwaddr offset, 1082 unsigned size) 1083 { 1084 switch (offset) { 1085 case MP_MISC_BOARD_REVISION: 1086 return MP_BOARD_REVISION; 1087 1088 default: 1089 return 0; 1090 } 1091 } 1092 1093 static void musicpal_misc_write(void *opaque, hwaddr offset, 1094 uint64_t value, unsigned size) 1095 { 1096 } 1097 1098 static const MemoryRegionOps musicpal_misc_ops = { 1099 .read = musicpal_misc_read, 1100 .write = musicpal_misc_write, 1101 .endianness = DEVICE_NATIVE_ENDIAN, 1102 }; 1103 1104 static void musicpal_misc_init(Object *obj) 1105 { 1106 SysBusDevice *sd = SYS_BUS_DEVICE(obj); 1107 MusicPalMiscState *s = MUSICPAL_MISC(obj); 1108 1109 memory_region_init_io(&s->iomem, OBJECT(s), &musicpal_misc_ops, NULL, 1110 "musicpal-misc", MP_MISC_SIZE); 1111 sysbus_init_mmio(sd, &s->iomem); 1112 } 1113 1114 static const TypeInfo musicpal_misc_info = { 1115 .name = TYPE_MUSICPAL_MISC, 1116 .parent = TYPE_SYS_BUS_DEVICE, 1117 .instance_init = musicpal_misc_init, 1118 .instance_size = sizeof(MusicPalMiscState), 1119 }; 1120 1121 /* WLAN register offsets */ 1122 #define MP_WLAN_MAGIC1 0x11c 1123 #define MP_WLAN_MAGIC2 0x124 1124 1125 static uint64_t mv88w8618_wlan_read(void *opaque, hwaddr offset, 1126 unsigned size) 1127 { 1128 switch (offset) { 1129 /* Workaround to allow loading the binary-only wlandrv.ko crap 1130 * from the original Freecom firmware. */ 1131 case MP_WLAN_MAGIC1: 1132 return ~3; 1133 case MP_WLAN_MAGIC2: 1134 return -1; 1135 1136 default: 1137 return 0; 1138 } 1139 } 1140 1141 static void mv88w8618_wlan_write(void *opaque, hwaddr offset, 1142 uint64_t value, unsigned size) 1143 { 1144 } 1145 1146 static const MemoryRegionOps mv88w8618_wlan_ops = { 1147 .read = mv88w8618_wlan_read, 1148 .write =mv88w8618_wlan_write, 1149 .endianness = DEVICE_NATIVE_ENDIAN, 1150 }; 1151 1152 static int mv88w8618_wlan_init(SysBusDevice *dev) 1153 { 1154 MemoryRegion *iomem = g_new(MemoryRegion, 1); 1155 1156 memory_region_init_io(iomem, OBJECT(dev), &mv88w8618_wlan_ops, NULL, 1157 "musicpal-wlan", MP_WLAN_SIZE); 1158 sysbus_init_mmio(dev, iomem); 1159 return 0; 1160 } 1161 1162 /* GPIO register offsets */ 1163 #define MP_GPIO_OE_LO 0x008 1164 #define MP_GPIO_OUT_LO 0x00c 1165 #define MP_GPIO_IN_LO 0x010 1166 #define MP_GPIO_IER_LO 0x014 1167 #define MP_GPIO_IMR_LO 0x018 1168 #define MP_GPIO_ISR_LO 0x020 1169 #define MP_GPIO_OE_HI 0x508 1170 #define MP_GPIO_OUT_HI 0x50c 1171 #define MP_GPIO_IN_HI 0x510 1172 #define MP_GPIO_IER_HI 0x514 1173 #define MP_GPIO_IMR_HI 0x518 1174 #define MP_GPIO_ISR_HI 0x520 1175 1176 /* GPIO bits & masks */ 1177 #define MP_GPIO_LCD_BRIGHTNESS 0x00070000 1178 #define MP_GPIO_I2C_DATA_BIT 29 1179 #define MP_GPIO_I2C_CLOCK_BIT 30 1180 1181 /* LCD brightness bits in GPIO_OE_HI */ 1182 #define MP_OE_LCD_BRIGHTNESS 0x0007 1183 1184 #define TYPE_MUSICPAL_GPIO "musicpal_gpio" 1185 #define MUSICPAL_GPIO(obj) \ 1186 OBJECT_CHECK(musicpal_gpio_state, (obj), TYPE_MUSICPAL_GPIO) 1187 1188 typedef struct musicpal_gpio_state { 1189 /*< private >*/ 1190 SysBusDevice parent_obj; 1191 /*< public >*/ 1192 1193 MemoryRegion iomem; 1194 uint32_t lcd_brightness; 1195 uint32_t out_state; 1196 uint32_t in_state; 1197 uint32_t ier; 1198 uint32_t imr; 1199 uint32_t isr; 1200 qemu_irq irq; 1201 qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */ 1202 } musicpal_gpio_state; 1203 1204 static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) { 1205 int i; 1206 uint32_t brightness; 1207 1208 /* compute brightness ratio */ 1209 switch (s->lcd_brightness) { 1210 case 0x00000007: 1211 brightness = 0; 1212 break; 1213 1214 case 0x00020000: 1215 brightness = 1; 1216 break; 1217 1218 case 0x00020001: 1219 brightness = 2; 1220 break; 1221 1222 case 0x00040000: 1223 brightness = 3; 1224 break; 1225 1226 case 0x00010006: 1227 brightness = 4; 1228 break; 1229 1230 case 0x00020005: 1231 brightness = 5; 1232 break; 1233 1234 case 0x00040003: 1235 brightness = 6; 1236 break; 1237 1238 case 0x00030004: 1239 default: 1240 brightness = 7; 1241 } 1242 1243 /* set lcd brightness GPIOs */ 1244 for (i = 0; i <= 2; i++) { 1245 qemu_set_irq(s->out[i], (brightness >> i) & 1); 1246 } 1247 } 1248 1249 static void musicpal_gpio_pin_event(void *opaque, int pin, int level) 1250 { 1251 musicpal_gpio_state *s = opaque; 1252 uint32_t mask = 1 << pin; 1253 uint32_t delta = level << pin; 1254 uint32_t old = s->in_state & mask; 1255 1256 s->in_state &= ~mask; 1257 s->in_state |= delta; 1258 1259 if ((old ^ delta) && 1260 ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) { 1261 s->isr = mask; 1262 qemu_irq_raise(s->irq); 1263 } 1264 } 1265 1266 static uint64_t musicpal_gpio_read(void *opaque, hwaddr offset, 1267 unsigned size) 1268 { 1269 musicpal_gpio_state *s = opaque; 1270 1271 switch (offset) { 1272 case MP_GPIO_OE_HI: /* used for LCD brightness control */ 1273 return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS; 1274 1275 case MP_GPIO_OUT_LO: 1276 return s->out_state & 0xFFFF; 1277 case MP_GPIO_OUT_HI: 1278 return s->out_state >> 16; 1279 1280 case MP_GPIO_IN_LO: 1281 return s->in_state & 0xFFFF; 1282 case MP_GPIO_IN_HI: 1283 return s->in_state >> 16; 1284 1285 case MP_GPIO_IER_LO: 1286 return s->ier & 0xFFFF; 1287 case MP_GPIO_IER_HI: 1288 return s->ier >> 16; 1289 1290 case MP_GPIO_IMR_LO: 1291 return s->imr & 0xFFFF; 1292 case MP_GPIO_IMR_HI: 1293 return s->imr >> 16; 1294 1295 case MP_GPIO_ISR_LO: 1296 return s->isr & 0xFFFF; 1297 case MP_GPIO_ISR_HI: 1298 return s->isr >> 16; 1299 1300 default: 1301 return 0; 1302 } 1303 } 1304 1305 static void musicpal_gpio_write(void *opaque, hwaddr offset, 1306 uint64_t value, unsigned size) 1307 { 1308 musicpal_gpio_state *s = opaque; 1309 switch (offset) { 1310 case MP_GPIO_OE_HI: /* used for LCD brightness control */ 1311 s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) | 1312 (value & MP_OE_LCD_BRIGHTNESS); 1313 musicpal_gpio_brightness_update(s); 1314 break; 1315 1316 case MP_GPIO_OUT_LO: 1317 s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF); 1318 break; 1319 case MP_GPIO_OUT_HI: 1320 s->out_state = (s->out_state & 0xFFFF) | (value << 16); 1321 s->lcd_brightness = (s->lcd_brightness & 0xFFFF) | 1322 (s->out_state & MP_GPIO_LCD_BRIGHTNESS); 1323 musicpal_gpio_brightness_update(s); 1324 qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1); 1325 qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1); 1326 break; 1327 1328 case MP_GPIO_IER_LO: 1329 s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF); 1330 break; 1331 case MP_GPIO_IER_HI: 1332 s->ier = (s->ier & 0xFFFF) | (value << 16); 1333 break; 1334 1335 case MP_GPIO_IMR_LO: 1336 s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF); 1337 break; 1338 case MP_GPIO_IMR_HI: 1339 s->imr = (s->imr & 0xFFFF) | (value << 16); 1340 break; 1341 } 1342 } 1343 1344 static const MemoryRegionOps musicpal_gpio_ops = { 1345 .read = musicpal_gpio_read, 1346 .write = musicpal_gpio_write, 1347 .endianness = DEVICE_NATIVE_ENDIAN, 1348 }; 1349 1350 static void musicpal_gpio_reset(DeviceState *d) 1351 { 1352 musicpal_gpio_state *s = MUSICPAL_GPIO(d); 1353 1354 s->lcd_brightness = 0; 1355 s->out_state = 0; 1356 s->in_state = 0xffffffff; 1357 s->ier = 0; 1358 s->imr = 0; 1359 s->isr = 0; 1360 } 1361 1362 static int musicpal_gpio_init(SysBusDevice *sbd) 1363 { 1364 DeviceState *dev = DEVICE(sbd); 1365 musicpal_gpio_state *s = MUSICPAL_GPIO(dev); 1366 1367 sysbus_init_irq(sbd, &s->irq); 1368 1369 memory_region_init_io(&s->iomem, OBJECT(s), &musicpal_gpio_ops, s, 1370 "musicpal-gpio", MP_GPIO_SIZE); 1371 sysbus_init_mmio(sbd, &s->iomem); 1372 1373 qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out)); 1374 1375 qdev_init_gpio_in(dev, musicpal_gpio_pin_event, 32); 1376 1377 return 0; 1378 } 1379 1380 static const VMStateDescription musicpal_gpio_vmsd = { 1381 .name = "musicpal_gpio", 1382 .version_id = 1, 1383 .minimum_version_id = 1, 1384 .minimum_version_id_old = 1, 1385 .fields = (VMStateField[]) { 1386 VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state), 1387 VMSTATE_UINT32(out_state, musicpal_gpio_state), 1388 VMSTATE_UINT32(in_state, musicpal_gpio_state), 1389 VMSTATE_UINT32(ier, musicpal_gpio_state), 1390 VMSTATE_UINT32(imr, musicpal_gpio_state), 1391 VMSTATE_UINT32(isr, musicpal_gpio_state), 1392 VMSTATE_END_OF_LIST() 1393 } 1394 }; 1395 1396 static void musicpal_gpio_class_init(ObjectClass *klass, void *data) 1397 { 1398 DeviceClass *dc = DEVICE_CLASS(klass); 1399 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1400 1401 k->init = musicpal_gpio_init; 1402 dc->reset = musicpal_gpio_reset; 1403 dc->vmsd = &musicpal_gpio_vmsd; 1404 } 1405 1406 static const TypeInfo musicpal_gpio_info = { 1407 .name = TYPE_MUSICPAL_GPIO, 1408 .parent = TYPE_SYS_BUS_DEVICE, 1409 .instance_size = sizeof(musicpal_gpio_state), 1410 .class_init = musicpal_gpio_class_init, 1411 }; 1412 1413 /* Keyboard codes & masks */ 1414 #define KEY_RELEASED 0x80 1415 #define KEY_CODE 0x7f 1416 1417 #define KEYCODE_TAB 0x0f 1418 #define KEYCODE_ENTER 0x1c 1419 #define KEYCODE_F 0x21 1420 #define KEYCODE_M 0x32 1421 1422 #define KEYCODE_EXTENDED 0xe0 1423 #define KEYCODE_UP 0x48 1424 #define KEYCODE_DOWN 0x50 1425 #define KEYCODE_LEFT 0x4b 1426 #define KEYCODE_RIGHT 0x4d 1427 1428 #define MP_KEY_WHEEL_VOL (1 << 0) 1429 #define MP_KEY_WHEEL_VOL_INV (1 << 1) 1430 #define MP_KEY_WHEEL_NAV (1 << 2) 1431 #define MP_KEY_WHEEL_NAV_INV (1 << 3) 1432 #define MP_KEY_BTN_FAVORITS (1 << 4) 1433 #define MP_KEY_BTN_MENU (1 << 5) 1434 #define MP_KEY_BTN_VOLUME (1 << 6) 1435 #define MP_KEY_BTN_NAVIGATION (1 << 7) 1436 1437 #define TYPE_MUSICPAL_KEY "musicpal_key" 1438 #define MUSICPAL_KEY(obj) \ 1439 OBJECT_CHECK(musicpal_key_state, (obj), TYPE_MUSICPAL_KEY) 1440 1441 typedef struct musicpal_key_state { 1442 /*< private >*/ 1443 SysBusDevice parent_obj; 1444 /*< public >*/ 1445 1446 MemoryRegion iomem; 1447 uint32_t kbd_extended; 1448 uint32_t pressed_keys; 1449 qemu_irq out[8]; 1450 } musicpal_key_state; 1451 1452 static void musicpal_key_event(void *opaque, int keycode) 1453 { 1454 musicpal_key_state *s = opaque; 1455 uint32_t event = 0; 1456 int i; 1457 1458 if (keycode == KEYCODE_EXTENDED) { 1459 s->kbd_extended = 1; 1460 return; 1461 } 1462 1463 if (s->kbd_extended) { 1464 switch (keycode & KEY_CODE) { 1465 case KEYCODE_UP: 1466 event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV; 1467 break; 1468 1469 case KEYCODE_DOWN: 1470 event = MP_KEY_WHEEL_NAV; 1471 break; 1472 1473 case KEYCODE_LEFT: 1474 event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV; 1475 break; 1476 1477 case KEYCODE_RIGHT: 1478 event = MP_KEY_WHEEL_VOL; 1479 break; 1480 } 1481 } else { 1482 switch (keycode & KEY_CODE) { 1483 case KEYCODE_F: 1484 event = MP_KEY_BTN_FAVORITS; 1485 break; 1486 1487 case KEYCODE_TAB: 1488 event = MP_KEY_BTN_VOLUME; 1489 break; 1490 1491 case KEYCODE_ENTER: 1492 event = MP_KEY_BTN_NAVIGATION; 1493 break; 1494 1495 case KEYCODE_M: 1496 event = MP_KEY_BTN_MENU; 1497 break; 1498 } 1499 /* Do not repeat already pressed buttons */ 1500 if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) { 1501 event = 0; 1502 } 1503 } 1504 1505 if (event) { 1506 /* Raise GPIO pin first if repeating a key */ 1507 if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) { 1508 for (i = 0; i <= 7; i++) { 1509 if (event & (1 << i)) { 1510 qemu_set_irq(s->out[i], 1); 1511 } 1512 } 1513 } 1514 for (i = 0; i <= 7; i++) { 1515 if (event & (1 << i)) { 1516 qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED)); 1517 } 1518 } 1519 if (keycode & KEY_RELEASED) { 1520 s->pressed_keys &= ~event; 1521 } else { 1522 s->pressed_keys |= event; 1523 } 1524 } 1525 1526 s->kbd_extended = 0; 1527 } 1528 1529 static int musicpal_key_init(SysBusDevice *sbd) 1530 { 1531 DeviceState *dev = DEVICE(sbd); 1532 musicpal_key_state *s = MUSICPAL_KEY(dev); 1533 1534 memory_region_init(&s->iomem, OBJECT(s), "dummy", 0); 1535 sysbus_init_mmio(sbd, &s->iomem); 1536 1537 s->kbd_extended = 0; 1538 s->pressed_keys = 0; 1539 1540 qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out)); 1541 1542 qemu_add_kbd_event_handler(musicpal_key_event, s); 1543 1544 return 0; 1545 } 1546 1547 static const VMStateDescription musicpal_key_vmsd = { 1548 .name = "musicpal_key", 1549 .version_id = 1, 1550 .minimum_version_id = 1, 1551 .minimum_version_id_old = 1, 1552 .fields = (VMStateField[]) { 1553 VMSTATE_UINT32(kbd_extended, musicpal_key_state), 1554 VMSTATE_UINT32(pressed_keys, musicpal_key_state), 1555 VMSTATE_END_OF_LIST() 1556 } 1557 }; 1558 1559 static void musicpal_key_class_init(ObjectClass *klass, void *data) 1560 { 1561 DeviceClass *dc = DEVICE_CLASS(klass); 1562 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1563 1564 k->init = musicpal_key_init; 1565 dc->vmsd = &musicpal_key_vmsd; 1566 } 1567 1568 static const TypeInfo musicpal_key_info = { 1569 .name = TYPE_MUSICPAL_KEY, 1570 .parent = TYPE_SYS_BUS_DEVICE, 1571 .instance_size = sizeof(musicpal_key_state), 1572 .class_init = musicpal_key_class_init, 1573 }; 1574 1575 static struct arm_boot_info musicpal_binfo = { 1576 .loader_start = 0x0, 1577 .board_id = 0x20e, 1578 }; 1579 1580 static void musicpal_init(QEMUMachineInitArgs *args) 1581 { 1582 const char *cpu_model = args->cpu_model; 1583 const char *kernel_filename = args->kernel_filename; 1584 const char *kernel_cmdline = args->kernel_cmdline; 1585 const char *initrd_filename = args->initrd_filename; 1586 ARMCPU *cpu; 1587 qemu_irq pic[32]; 1588 DeviceState *dev; 1589 DeviceState *i2c_dev; 1590 DeviceState *lcd_dev; 1591 DeviceState *key_dev; 1592 DeviceState *wm8750_dev; 1593 SysBusDevice *s; 1594 I2CBus *i2c; 1595 int i; 1596 unsigned long flash_size; 1597 DriveInfo *dinfo; 1598 MemoryRegion *address_space_mem = get_system_memory(); 1599 MemoryRegion *ram = g_new(MemoryRegion, 1); 1600 MemoryRegion *sram = g_new(MemoryRegion, 1); 1601 1602 if (!cpu_model) { 1603 cpu_model = "arm926"; 1604 } 1605 cpu = cpu_arm_init(cpu_model); 1606 if (!cpu) { 1607 fprintf(stderr, "Unable to find CPU definition\n"); 1608 exit(1); 1609 } 1610 1611 /* For now we use a fixed - the original - RAM size */ 1612 memory_region_init_ram(ram, NULL, "musicpal.ram", MP_RAM_DEFAULT_SIZE); 1613 vmstate_register_ram_global(ram); 1614 memory_region_add_subregion(address_space_mem, 0, ram); 1615 1616 memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE); 1617 vmstate_register_ram_global(sram); 1618 memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram); 1619 1620 dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE, 1621 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); 1622 for (i = 0; i < 32; i++) { 1623 pic[i] = qdev_get_gpio_in(dev, i); 1624 } 1625 sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ], 1626 pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], 1627 pic[MP_TIMER4_IRQ], NULL); 1628 1629 if (serial_hds[0]) { 1630 serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1631 1825000, serial_hds[0], DEVICE_NATIVE_ENDIAN); 1632 } 1633 if (serial_hds[1]) { 1634 serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1635 1825000, serial_hds[1], DEVICE_NATIVE_ENDIAN); 1636 } 1637 1638 /* Register flash */ 1639 dinfo = drive_get(IF_PFLASH, 0, 0); 1640 if (dinfo) { 1641 flash_size = bdrv_getlength(dinfo->bdrv); 1642 if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 && 1643 flash_size != 32*1024*1024) { 1644 fprintf(stderr, "Invalid flash image size\n"); 1645 exit(1); 1646 } 1647 1648 /* 1649 * The original U-Boot accesses the flash at 0xFE000000 instead of 1650 * 0xFF800000 (if there is 8 MB flash). So remap flash access if the 1651 * image is smaller than 32 MB. 1652 */ 1653 #ifdef TARGET_WORDS_BIGENDIAN 1654 pflash_cfi02_register(0x100000000ULL-MP_FLASH_SIZE_MAX, NULL, 1655 "musicpal.flash", flash_size, 1656 dinfo->bdrv, 0x10000, 1657 (flash_size + 0xffff) >> 16, 1658 MP_FLASH_SIZE_MAX / flash_size, 1659 2, 0x00BF, 0x236D, 0x0000, 0x0000, 1660 0x5555, 0x2AAA, 1); 1661 #else 1662 pflash_cfi02_register(0x100000000ULL-MP_FLASH_SIZE_MAX, NULL, 1663 "musicpal.flash", flash_size, 1664 dinfo->bdrv, 0x10000, 1665 (flash_size + 0xffff) >> 16, 1666 MP_FLASH_SIZE_MAX / flash_size, 1667 2, 0x00BF, 0x236D, 0x0000, 0x0000, 1668 0x5555, 0x2AAA, 0); 1669 #endif 1670 1671 } 1672 sysbus_create_simple(TYPE_MV88W8618_FLASHCFG, MP_FLASHCFG_BASE, NULL); 1673 1674 qemu_check_nic_model(&nd_table[0], "mv88w8618"); 1675 dev = qdev_create(NULL, TYPE_MV88W8618_ETH); 1676 qdev_set_nic_properties(dev, &nd_table[0]); 1677 qdev_init_nofail(dev); 1678 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE); 1679 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]); 1680 1681 sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); 1682 1683 sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL); 1684 1685 dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE, 1686 pic[MP_GPIO_IRQ]); 1687 i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL); 1688 i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c"); 1689 1690 lcd_dev = sysbus_create_simple(TYPE_MUSICPAL_LCD, MP_LCD_BASE, NULL); 1691 key_dev = sysbus_create_simple(TYPE_MUSICPAL_KEY, -1, NULL); 1692 1693 /* I2C read data */ 1694 qdev_connect_gpio_out(i2c_dev, 0, 1695 qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT)); 1696 /* I2C data */ 1697 qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0)); 1698 /* I2C clock */ 1699 qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1)); 1700 1701 for (i = 0; i < 3; i++) { 1702 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i)); 1703 } 1704 for (i = 0; i < 4; i++) { 1705 qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8)); 1706 } 1707 for (i = 4; i < 8; i++) { 1708 qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15)); 1709 } 1710 1711 wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR); 1712 dev = qdev_create(NULL, "mv88w8618_audio"); 1713 s = SYS_BUS_DEVICE(dev); 1714 qdev_prop_set_ptr(dev, "wm8750", wm8750_dev); 1715 qdev_init_nofail(dev); 1716 sysbus_mmio_map(s, 0, MP_AUDIO_BASE); 1717 sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]); 1718 1719 musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; 1720 musicpal_binfo.kernel_filename = kernel_filename; 1721 musicpal_binfo.kernel_cmdline = kernel_cmdline; 1722 musicpal_binfo.initrd_filename = initrd_filename; 1723 arm_load_kernel(cpu, &musicpal_binfo); 1724 } 1725 1726 static QEMUMachine musicpal_machine = { 1727 .name = "musicpal", 1728 .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)", 1729 .init = musicpal_init, 1730 }; 1731 1732 static void musicpal_machine_init(void) 1733 { 1734 qemu_register_machine(&musicpal_machine); 1735 } 1736 1737 machine_init(musicpal_machine_init); 1738 1739 static void mv88w8618_wlan_class_init(ObjectClass *klass, void *data) 1740 { 1741 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 1742 1743 sdc->init = mv88w8618_wlan_init; 1744 } 1745 1746 static const TypeInfo mv88w8618_wlan_info = { 1747 .name = "mv88w8618_wlan", 1748 .parent = TYPE_SYS_BUS_DEVICE, 1749 .instance_size = sizeof(SysBusDevice), 1750 .class_init = mv88w8618_wlan_class_init, 1751 }; 1752 1753 static void musicpal_register_types(void) 1754 { 1755 type_register_static(&mv88w8618_pic_info); 1756 type_register_static(&mv88w8618_pit_info); 1757 type_register_static(&mv88w8618_flashcfg_info); 1758 type_register_static(&mv88w8618_eth_info); 1759 type_register_static(&mv88w8618_wlan_info); 1760 type_register_static(&musicpal_lcd_info); 1761 type_register_static(&musicpal_gpio_info); 1762 type_register_static(&musicpal_key_info); 1763 type_register_static(&musicpal_misc_info); 1764 } 1765 1766 type_init(musicpal_register_types) 1767