1 /* 2 * Marvell MV88W8618 / Freecom MusicPal emulation. 3 * 4 * Copyright (c) 2008 Jan Kiszka 5 * 6 * This code is licensed under the GNU GPL v2. 7 * 8 * Contributions after 2012-01-13 are licensed under the terms of the 9 * GNU GPL, version 2 or (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "cpu.h" 15 #include "hw/sysbus.h" 16 #include "migration/vmstate.h" 17 #include "hw/arm/boot.h" 18 #include "net/net.h" 19 #include "sysemu/sysemu.h" 20 #include "hw/boards.h" 21 #include "hw/char/serial.h" 22 #include "hw/hw.h" 23 #include "qemu/timer.h" 24 #include "hw/ptimer.h" 25 #include "hw/qdev-properties.h" 26 #include "hw/block/flash.h" 27 #include "ui/console.h" 28 #include "hw/i2c/i2c.h" 29 #include "hw/irq.h" 30 #include "hw/audio/wm8750.h" 31 #include "sysemu/block-backend.h" 32 #include "exec/address-spaces.h" 33 #include "ui/pixel_ops.h" 34 35 #define MP_MISC_BASE 0x80002000 36 #define MP_MISC_SIZE 0x00001000 37 38 #define MP_ETH_BASE 0x80008000 39 #define MP_ETH_SIZE 0x00001000 40 41 #define MP_WLAN_BASE 0x8000C000 42 #define MP_WLAN_SIZE 0x00000800 43 44 #define MP_UART1_BASE 0x8000C840 45 #define MP_UART2_BASE 0x8000C940 46 47 #define MP_GPIO_BASE 0x8000D000 48 #define MP_GPIO_SIZE 0x00001000 49 50 #define MP_FLASHCFG_BASE 0x90006000 51 #define MP_FLASHCFG_SIZE 0x00001000 52 53 #define MP_AUDIO_BASE 0x90007000 54 55 #define MP_PIC_BASE 0x90008000 56 #define MP_PIC_SIZE 0x00001000 57 58 #define MP_PIT_BASE 0x90009000 59 #define MP_PIT_SIZE 0x00001000 60 61 #define MP_LCD_BASE 0x9000c000 62 #define MP_LCD_SIZE 0x00001000 63 64 #define MP_SRAM_BASE 0xC0000000 65 #define MP_SRAM_SIZE 0x00020000 66 67 #define MP_RAM_DEFAULT_SIZE 32*1024*1024 68 #define MP_FLASH_SIZE_MAX 32*1024*1024 69 70 #define MP_TIMER1_IRQ 4 71 #define MP_TIMER2_IRQ 5 72 #define MP_TIMER3_IRQ 6 73 #define MP_TIMER4_IRQ 7 74 #define MP_EHCI_IRQ 8 75 #define MP_ETH_IRQ 9 76 #define MP_UART1_IRQ 11 77 #define MP_UART2_IRQ 11 78 #define MP_GPIO_IRQ 12 79 #define MP_RTC_IRQ 28 80 #define MP_AUDIO_IRQ 30 81 82 /* Wolfson 8750 I2C address */ 83 #define MP_WM_ADDR 0x1A 84 85 /* Ethernet register offsets */ 86 #define MP_ETH_SMIR 0x010 87 #define MP_ETH_PCXR 0x408 88 #define MP_ETH_SDCMR 0x448 89 #define MP_ETH_ICR 0x450 90 #define MP_ETH_IMR 0x458 91 #define MP_ETH_FRDP0 0x480 92 #define MP_ETH_FRDP1 0x484 93 #define MP_ETH_FRDP2 0x488 94 #define MP_ETH_FRDP3 0x48C 95 #define MP_ETH_CRDP0 0x4A0 96 #define MP_ETH_CRDP1 0x4A4 97 #define MP_ETH_CRDP2 0x4A8 98 #define MP_ETH_CRDP3 0x4AC 99 #define MP_ETH_CTDP0 0x4E0 100 #define MP_ETH_CTDP1 0x4E4 101 102 /* MII PHY access */ 103 #define MP_ETH_SMIR_DATA 0x0000FFFF 104 #define MP_ETH_SMIR_ADDR 0x03FF0000 105 #define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */ 106 #define MP_ETH_SMIR_RDVALID (1 << 27) 107 108 /* PHY registers */ 109 #define MP_ETH_PHY1_BMSR 0x00210000 110 #define MP_ETH_PHY1_PHYSID1 0x00410000 111 #define MP_ETH_PHY1_PHYSID2 0x00610000 112 113 #define MP_PHY_BMSR_LINK 0x0004 114 #define MP_PHY_BMSR_AUTONEG 0x0008 115 116 #define MP_PHY_88E3015 0x01410E20 117 118 /* TX descriptor status */ 119 #define MP_ETH_TX_OWN (1U << 31) 120 121 /* RX descriptor status */ 122 #define MP_ETH_RX_OWN (1U << 31) 123 124 /* Interrupt cause/mask bits */ 125 #define MP_ETH_IRQ_RX_BIT 0 126 #define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT) 127 #define MP_ETH_IRQ_TXHI_BIT 2 128 #define MP_ETH_IRQ_TXLO_BIT 3 129 130 /* Port config bits */ 131 #define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */ 132 133 /* SDMA command bits */ 134 #define MP_ETH_CMD_TXHI (1 << 23) 135 #define MP_ETH_CMD_TXLO (1 << 22) 136 137 typedef struct mv88w8618_tx_desc { 138 uint32_t cmdstat; 139 uint16_t res; 140 uint16_t bytes; 141 uint32_t buffer; 142 uint32_t next; 143 } mv88w8618_tx_desc; 144 145 typedef struct mv88w8618_rx_desc { 146 uint32_t cmdstat; 147 uint16_t bytes; 148 uint16_t buffer_size; 149 uint32_t buffer; 150 uint32_t next; 151 } mv88w8618_rx_desc; 152 153 #define TYPE_MV88W8618_ETH "mv88w8618_eth" 154 #define MV88W8618_ETH(obj) \ 155 OBJECT_CHECK(mv88w8618_eth_state, (obj), TYPE_MV88W8618_ETH) 156 157 typedef struct mv88w8618_eth_state { 158 /*< private >*/ 159 SysBusDevice parent_obj; 160 /*< public >*/ 161 162 MemoryRegion iomem; 163 qemu_irq irq; 164 uint32_t smir; 165 uint32_t icr; 166 uint32_t imr; 167 int mmio_index; 168 uint32_t vlan_header; 169 uint32_t tx_queue[2]; 170 uint32_t rx_queue[4]; 171 uint32_t frx_queue[4]; 172 uint32_t cur_rx[4]; 173 NICState *nic; 174 NICConf conf; 175 } mv88w8618_eth_state; 176 177 static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc) 178 { 179 cpu_to_le32s(&desc->cmdstat); 180 cpu_to_le16s(&desc->bytes); 181 cpu_to_le16s(&desc->buffer_size); 182 cpu_to_le32s(&desc->buffer); 183 cpu_to_le32s(&desc->next); 184 cpu_physical_memory_write(addr, desc, sizeof(*desc)); 185 } 186 187 static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc) 188 { 189 cpu_physical_memory_read(addr, desc, sizeof(*desc)); 190 le32_to_cpus(&desc->cmdstat); 191 le16_to_cpus(&desc->bytes); 192 le16_to_cpus(&desc->buffer_size); 193 le32_to_cpus(&desc->buffer); 194 le32_to_cpus(&desc->next); 195 } 196 197 static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size) 198 { 199 mv88w8618_eth_state *s = qemu_get_nic_opaque(nc); 200 uint32_t desc_addr; 201 mv88w8618_rx_desc desc; 202 int i; 203 204 for (i = 0; i < 4; i++) { 205 desc_addr = s->cur_rx[i]; 206 if (!desc_addr) { 207 continue; 208 } 209 do { 210 eth_rx_desc_get(desc_addr, &desc); 211 if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) { 212 cpu_physical_memory_write(desc.buffer + s->vlan_header, 213 buf, size); 214 desc.bytes = size + s->vlan_header; 215 desc.cmdstat &= ~MP_ETH_RX_OWN; 216 s->cur_rx[i] = desc.next; 217 218 s->icr |= MP_ETH_IRQ_RX; 219 if (s->icr & s->imr) { 220 qemu_irq_raise(s->irq); 221 } 222 eth_rx_desc_put(desc_addr, &desc); 223 return size; 224 } 225 desc_addr = desc.next; 226 } while (desc_addr != s->rx_queue[i]); 227 } 228 return size; 229 } 230 231 static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc) 232 { 233 cpu_to_le32s(&desc->cmdstat); 234 cpu_to_le16s(&desc->res); 235 cpu_to_le16s(&desc->bytes); 236 cpu_to_le32s(&desc->buffer); 237 cpu_to_le32s(&desc->next); 238 cpu_physical_memory_write(addr, desc, sizeof(*desc)); 239 } 240 241 static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc) 242 { 243 cpu_physical_memory_read(addr, desc, sizeof(*desc)); 244 le32_to_cpus(&desc->cmdstat); 245 le16_to_cpus(&desc->res); 246 le16_to_cpus(&desc->bytes); 247 le32_to_cpus(&desc->buffer); 248 le32_to_cpus(&desc->next); 249 } 250 251 static void eth_send(mv88w8618_eth_state *s, int queue_index) 252 { 253 uint32_t desc_addr = s->tx_queue[queue_index]; 254 mv88w8618_tx_desc desc; 255 uint32_t next_desc; 256 uint8_t buf[2048]; 257 int len; 258 259 do { 260 eth_tx_desc_get(desc_addr, &desc); 261 next_desc = desc.next; 262 if (desc.cmdstat & MP_ETH_TX_OWN) { 263 len = desc.bytes; 264 if (len < 2048) { 265 cpu_physical_memory_read(desc.buffer, buf, len); 266 qemu_send_packet(qemu_get_queue(s->nic), buf, len); 267 } 268 desc.cmdstat &= ~MP_ETH_TX_OWN; 269 s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index); 270 eth_tx_desc_put(desc_addr, &desc); 271 } 272 desc_addr = next_desc; 273 } while (desc_addr != s->tx_queue[queue_index]); 274 } 275 276 static uint64_t mv88w8618_eth_read(void *opaque, hwaddr offset, 277 unsigned size) 278 { 279 mv88w8618_eth_state *s = opaque; 280 281 switch (offset) { 282 case MP_ETH_SMIR: 283 if (s->smir & MP_ETH_SMIR_OPCODE) { 284 switch (s->smir & MP_ETH_SMIR_ADDR) { 285 case MP_ETH_PHY1_BMSR: 286 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG | 287 MP_ETH_SMIR_RDVALID; 288 case MP_ETH_PHY1_PHYSID1: 289 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID; 290 case MP_ETH_PHY1_PHYSID2: 291 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID; 292 default: 293 return MP_ETH_SMIR_RDVALID; 294 } 295 } 296 return 0; 297 298 case MP_ETH_ICR: 299 return s->icr; 300 301 case MP_ETH_IMR: 302 return s->imr; 303 304 case MP_ETH_FRDP0 ... MP_ETH_FRDP3: 305 return s->frx_queue[(offset - MP_ETH_FRDP0)/4]; 306 307 case MP_ETH_CRDP0 ... MP_ETH_CRDP3: 308 return s->rx_queue[(offset - MP_ETH_CRDP0)/4]; 309 310 case MP_ETH_CTDP0 ... MP_ETH_CTDP1: 311 return s->tx_queue[(offset - MP_ETH_CTDP0)/4]; 312 313 default: 314 return 0; 315 } 316 } 317 318 static void mv88w8618_eth_write(void *opaque, hwaddr offset, 319 uint64_t value, unsigned size) 320 { 321 mv88w8618_eth_state *s = opaque; 322 323 switch (offset) { 324 case MP_ETH_SMIR: 325 s->smir = value; 326 break; 327 328 case MP_ETH_PCXR: 329 s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2; 330 break; 331 332 case MP_ETH_SDCMR: 333 if (value & MP_ETH_CMD_TXHI) { 334 eth_send(s, 1); 335 } 336 if (value & MP_ETH_CMD_TXLO) { 337 eth_send(s, 0); 338 } 339 if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) { 340 qemu_irq_raise(s->irq); 341 } 342 break; 343 344 case MP_ETH_ICR: 345 s->icr &= value; 346 break; 347 348 case MP_ETH_IMR: 349 s->imr = value; 350 if (s->icr & s->imr) { 351 qemu_irq_raise(s->irq); 352 } 353 break; 354 355 case MP_ETH_FRDP0 ... MP_ETH_FRDP3: 356 s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value; 357 break; 358 359 case MP_ETH_CRDP0 ... MP_ETH_CRDP3: 360 s->rx_queue[(offset - MP_ETH_CRDP0)/4] = 361 s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value; 362 break; 363 364 case MP_ETH_CTDP0 ... MP_ETH_CTDP1: 365 s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value; 366 break; 367 } 368 } 369 370 static const MemoryRegionOps mv88w8618_eth_ops = { 371 .read = mv88w8618_eth_read, 372 .write = mv88w8618_eth_write, 373 .endianness = DEVICE_NATIVE_ENDIAN, 374 }; 375 376 static void eth_cleanup(NetClientState *nc) 377 { 378 mv88w8618_eth_state *s = qemu_get_nic_opaque(nc); 379 380 s->nic = NULL; 381 } 382 383 static NetClientInfo net_mv88w8618_info = { 384 .type = NET_CLIENT_DRIVER_NIC, 385 .size = sizeof(NICState), 386 .receive = eth_receive, 387 .cleanup = eth_cleanup, 388 }; 389 390 static void mv88w8618_eth_init(Object *obj) 391 { 392 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 393 DeviceState *dev = DEVICE(sbd); 394 mv88w8618_eth_state *s = MV88W8618_ETH(dev); 395 396 sysbus_init_irq(sbd, &s->irq); 397 memory_region_init_io(&s->iomem, obj, &mv88w8618_eth_ops, s, 398 "mv88w8618-eth", MP_ETH_SIZE); 399 sysbus_init_mmio(sbd, &s->iomem); 400 } 401 402 static void mv88w8618_eth_realize(DeviceState *dev, Error **errp) 403 { 404 mv88w8618_eth_state *s = MV88W8618_ETH(dev); 405 406 s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf, 407 object_get_typename(OBJECT(dev)), dev->id, s); 408 } 409 410 static const VMStateDescription mv88w8618_eth_vmsd = { 411 .name = "mv88w8618_eth", 412 .version_id = 1, 413 .minimum_version_id = 1, 414 .fields = (VMStateField[]) { 415 VMSTATE_UINT32(smir, mv88w8618_eth_state), 416 VMSTATE_UINT32(icr, mv88w8618_eth_state), 417 VMSTATE_UINT32(imr, mv88w8618_eth_state), 418 VMSTATE_UINT32(vlan_header, mv88w8618_eth_state), 419 VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2), 420 VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4), 421 VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4), 422 VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4), 423 VMSTATE_END_OF_LIST() 424 } 425 }; 426 427 static Property mv88w8618_eth_properties[] = { 428 DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf), 429 DEFINE_PROP_END_OF_LIST(), 430 }; 431 432 static void mv88w8618_eth_class_init(ObjectClass *klass, void *data) 433 { 434 DeviceClass *dc = DEVICE_CLASS(klass); 435 436 dc->vmsd = &mv88w8618_eth_vmsd; 437 dc->props = mv88w8618_eth_properties; 438 dc->realize = mv88w8618_eth_realize; 439 } 440 441 static const TypeInfo mv88w8618_eth_info = { 442 .name = TYPE_MV88W8618_ETH, 443 .parent = TYPE_SYS_BUS_DEVICE, 444 .instance_size = sizeof(mv88w8618_eth_state), 445 .instance_init = mv88w8618_eth_init, 446 .class_init = mv88w8618_eth_class_init, 447 }; 448 449 /* LCD register offsets */ 450 #define MP_LCD_IRQCTRL 0x180 451 #define MP_LCD_IRQSTAT 0x184 452 #define MP_LCD_SPICTRL 0x1ac 453 #define MP_LCD_INST 0x1bc 454 #define MP_LCD_DATA 0x1c0 455 456 /* Mode magics */ 457 #define MP_LCD_SPI_DATA 0x00100011 458 #define MP_LCD_SPI_CMD 0x00104011 459 #define MP_LCD_SPI_INVALID 0x00000000 460 461 /* Commmands */ 462 #define MP_LCD_INST_SETPAGE0 0xB0 463 /* ... */ 464 #define MP_LCD_INST_SETPAGE7 0xB7 465 466 #define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */ 467 468 #define TYPE_MUSICPAL_LCD "musicpal_lcd" 469 #define MUSICPAL_LCD(obj) \ 470 OBJECT_CHECK(musicpal_lcd_state, (obj), TYPE_MUSICPAL_LCD) 471 472 typedef struct musicpal_lcd_state { 473 /*< private >*/ 474 SysBusDevice parent_obj; 475 /*< public >*/ 476 477 MemoryRegion iomem; 478 uint32_t brightness; 479 uint32_t mode; 480 uint32_t irqctrl; 481 uint32_t page; 482 uint32_t page_off; 483 QemuConsole *con; 484 uint8_t video_ram[128*64/8]; 485 } musicpal_lcd_state; 486 487 static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col) 488 { 489 switch (s->brightness) { 490 case 7: 491 return col; 492 case 0: 493 return 0; 494 default: 495 return (col * s->brightness) / 7; 496 } 497 } 498 499 #define SET_LCD_PIXEL(depth, type) \ 500 static inline void glue(set_lcd_pixel, depth) \ 501 (musicpal_lcd_state *s, int x, int y, type col) \ 502 { \ 503 int dx, dy; \ 504 DisplaySurface *surface = qemu_console_surface(s->con); \ 505 type *pixel = &((type *) surface_data(surface))[(y * 128 * 3 + x) * 3]; \ 506 \ 507 for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \ 508 for (dx = 0; dx < 3; dx++, pixel++) \ 509 *pixel = col; \ 510 } 511 SET_LCD_PIXEL(8, uint8_t) 512 SET_LCD_PIXEL(16, uint16_t) 513 SET_LCD_PIXEL(32, uint32_t) 514 515 static void lcd_refresh(void *opaque) 516 { 517 musicpal_lcd_state *s = opaque; 518 DisplaySurface *surface = qemu_console_surface(s->con); 519 int x, y, col; 520 521 switch (surface_bits_per_pixel(surface)) { 522 case 0: 523 return; 524 #define LCD_REFRESH(depth, func) \ 525 case depth: \ 526 col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \ 527 scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \ 528 scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \ 529 for (x = 0; x < 128; x++) { \ 530 for (y = 0; y < 64; y++) { \ 531 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \ 532 glue(set_lcd_pixel, depth)(s, x, y, col); \ 533 } else { \ 534 glue(set_lcd_pixel, depth)(s, x, y, 0); \ 535 } \ 536 } \ 537 } \ 538 break; 539 LCD_REFRESH(8, rgb_to_pixel8) 540 LCD_REFRESH(16, rgb_to_pixel16) 541 LCD_REFRESH(32, (is_surface_bgr(surface) ? 542 rgb_to_pixel32bgr : rgb_to_pixel32)) 543 default: 544 hw_error("unsupported colour depth %i\n", 545 surface_bits_per_pixel(surface)); 546 } 547 548 dpy_gfx_update(s->con, 0, 0, 128*3, 64*3); 549 } 550 551 static void lcd_invalidate(void *opaque) 552 { 553 } 554 555 static void musicpal_lcd_gpio_brightness_in(void *opaque, int irq, int level) 556 { 557 musicpal_lcd_state *s = opaque; 558 s->brightness &= ~(1 << irq); 559 s->brightness |= level << irq; 560 } 561 562 static uint64_t musicpal_lcd_read(void *opaque, hwaddr offset, 563 unsigned size) 564 { 565 musicpal_lcd_state *s = opaque; 566 567 switch (offset) { 568 case MP_LCD_IRQCTRL: 569 return s->irqctrl; 570 571 default: 572 return 0; 573 } 574 } 575 576 static void musicpal_lcd_write(void *opaque, hwaddr offset, 577 uint64_t value, unsigned size) 578 { 579 musicpal_lcd_state *s = opaque; 580 581 switch (offset) { 582 case MP_LCD_IRQCTRL: 583 s->irqctrl = value; 584 break; 585 586 case MP_LCD_SPICTRL: 587 if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) { 588 s->mode = value; 589 } else { 590 s->mode = MP_LCD_SPI_INVALID; 591 } 592 break; 593 594 case MP_LCD_INST: 595 if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) { 596 s->page = value - MP_LCD_INST_SETPAGE0; 597 s->page_off = 0; 598 } 599 break; 600 601 case MP_LCD_DATA: 602 if (s->mode == MP_LCD_SPI_CMD) { 603 if (value >= MP_LCD_INST_SETPAGE0 && 604 value <= MP_LCD_INST_SETPAGE7) { 605 s->page = value - MP_LCD_INST_SETPAGE0; 606 s->page_off = 0; 607 } 608 } else if (s->mode == MP_LCD_SPI_DATA) { 609 s->video_ram[s->page*128 + s->page_off] = value; 610 s->page_off = (s->page_off + 1) & 127; 611 } 612 break; 613 } 614 } 615 616 static const MemoryRegionOps musicpal_lcd_ops = { 617 .read = musicpal_lcd_read, 618 .write = musicpal_lcd_write, 619 .endianness = DEVICE_NATIVE_ENDIAN, 620 }; 621 622 static const GraphicHwOps musicpal_gfx_ops = { 623 .invalidate = lcd_invalidate, 624 .gfx_update = lcd_refresh, 625 }; 626 627 static void musicpal_lcd_realize(DeviceState *dev, Error **errp) 628 { 629 musicpal_lcd_state *s = MUSICPAL_LCD(dev); 630 s->con = graphic_console_init(dev, 0, &musicpal_gfx_ops, s); 631 qemu_console_resize(s->con, 128 * 3, 64 * 3); 632 } 633 634 static void musicpal_lcd_init(Object *obj) 635 { 636 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 637 DeviceState *dev = DEVICE(sbd); 638 musicpal_lcd_state *s = MUSICPAL_LCD(dev); 639 640 s->brightness = 7; 641 642 memory_region_init_io(&s->iomem, obj, &musicpal_lcd_ops, s, 643 "musicpal-lcd", MP_LCD_SIZE); 644 sysbus_init_mmio(sbd, &s->iomem); 645 646 qdev_init_gpio_in(dev, musicpal_lcd_gpio_brightness_in, 3); 647 } 648 649 static const VMStateDescription musicpal_lcd_vmsd = { 650 .name = "musicpal_lcd", 651 .version_id = 1, 652 .minimum_version_id = 1, 653 .fields = (VMStateField[]) { 654 VMSTATE_UINT32(brightness, musicpal_lcd_state), 655 VMSTATE_UINT32(mode, musicpal_lcd_state), 656 VMSTATE_UINT32(irqctrl, musicpal_lcd_state), 657 VMSTATE_UINT32(page, musicpal_lcd_state), 658 VMSTATE_UINT32(page_off, musicpal_lcd_state), 659 VMSTATE_BUFFER(video_ram, musicpal_lcd_state), 660 VMSTATE_END_OF_LIST() 661 } 662 }; 663 664 static void musicpal_lcd_class_init(ObjectClass *klass, void *data) 665 { 666 DeviceClass *dc = DEVICE_CLASS(klass); 667 668 dc->vmsd = &musicpal_lcd_vmsd; 669 dc->realize = musicpal_lcd_realize; 670 } 671 672 static const TypeInfo musicpal_lcd_info = { 673 .name = TYPE_MUSICPAL_LCD, 674 .parent = TYPE_SYS_BUS_DEVICE, 675 .instance_size = sizeof(musicpal_lcd_state), 676 .instance_init = musicpal_lcd_init, 677 .class_init = musicpal_lcd_class_init, 678 }; 679 680 /* PIC register offsets */ 681 #define MP_PIC_STATUS 0x00 682 #define MP_PIC_ENABLE_SET 0x08 683 #define MP_PIC_ENABLE_CLR 0x0C 684 685 #define TYPE_MV88W8618_PIC "mv88w8618_pic" 686 #define MV88W8618_PIC(obj) \ 687 OBJECT_CHECK(mv88w8618_pic_state, (obj), TYPE_MV88W8618_PIC) 688 689 typedef struct mv88w8618_pic_state { 690 /*< private >*/ 691 SysBusDevice parent_obj; 692 /*< public >*/ 693 694 MemoryRegion iomem; 695 uint32_t level; 696 uint32_t enabled; 697 qemu_irq parent_irq; 698 } mv88w8618_pic_state; 699 700 static void mv88w8618_pic_update(mv88w8618_pic_state *s) 701 { 702 qemu_set_irq(s->parent_irq, (s->level & s->enabled)); 703 } 704 705 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level) 706 { 707 mv88w8618_pic_state *s = opaque; 708 709 if (level) { 710 s->level |= 1 << irq; 711 } else { 712 s->level &= ~(1 << irq); 713 } 714 mv88w8618_pic_update(s); 715 } 716 717 static uint64_t mv88w8618_pic_read(void *opaque, hwaddr offset, 718 unsigned size) 719 { 720 mv88w8618_pic_state *s = opaque; 721 722 switch (offset) { 723 case MP_PIC_STATUS: 724 return s->level & s->enabled; 725 726 default: 727 return 0; 728 } 729 } 730 731 static void mv88w8618_pic_write(void *opaque, hwaddr offset, 732 uint64_t value, unsigned size) 733 { 734 mv88w8618_pic_state *s = opaque; 735 736 switch (offset) { 737 case MP_PIC_ENABLE_SET: 738 s->enabled |= value; 739 break; 740 741 case MP_PIC_ENABLE_CLR: 742 s->enabled &= ~value; 743 s->level &= ~value; 744 break; 745 } 746 mv88w8618_pic_update(s); 747 } 748 749 static void mv88w8618_pic_reset(DeviceState *d) 750 { 751 mv88w8618_pic_state *s = MV88W8618_PIC(d); 752 753 s->level = 0; 754 s->enabled = 0; 755 } 756 757 static const MemoryRegionOps mv88w8618_pic_ops = { 758 .read = mv88w8618_pic_read, 759 .write = mv88w8618_pic_write, 760 .endianness = DEVICE_NATIVE_ENDIAN, 761 }; 762 763 static void mv88w8618_pic_init(Object *obj) 764 { 765 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 766 mv88w8618_pic_state *s = MV88W8618_PIC(dev); 767 768 qdev_init_gpio_in(DEVICE(dev), mv88w8618_pic_set_irq, 32); 769 sysbus_init_irq(dev, &s->parent_irq); 770 memory_region_init_io(&s->iomem, obj, &mv88w8618_pic_ops, s, 771 "musicpal-pic", MP_PIC_SIZE); 772 sysbus_init_mmio(dev, &s->iomem); 773 } 774 775 static const VMStateDescription mv88w8618_pic_vmsd = { 776 .name = "mv88w8618_pic", 777 .version_id = 1, 778 .minimum_version_id = 1, 779 .fields = (VMStateField[]) { 780 VMSTATE_UINT32(level, mv88w8618_pic_state), 781 VMSTATE_UINT32(enabled, mv88w8618_pic_state), 782 VMSTATE_END_OF_LIST() 783 } 784 }; 785 786 static void mv88w8618_pic_class_init(ObjectClass *klass, void *data) 787 { 788 DeviceClass *dc = DEVICE_CLASS(klass); 789 790 dc->reset = mv88w8618_pic_reset; 791 dc->vmsd = &mv88w8618_pic_vmsd; 792 } 793 794 static const TypeInfo mv88w8618_pic_info = { 795 .name = TYPE_MV88W8618_PIC, 796 .parent = TYPE_SYS_BUS_DEVICE, 797 .instance_size = sizeof(mv88w8618_pic_state), 798 .instance_init = mv88w8618_pic_init, 799 .class_init = mv88w8618_pic_class_init, 800 }; 801 802 /* PIT register offsets */ 803 #define MP_PIT_TIMER1_LENGTH 0x00 804 /* ... */ 805 #define MP_PIT_TIMER4_LENGTH 0x0C 806 #define MP_PIT_CONTROL 0x10 807 #define MP_PIT_TIMER1_VALUE 0x14 808 /* ... */ 809 #define MP_PIT_TIMER4_VALUE 0x20 810 #define MP_BOARD_RESET 0x34 811 812 /* Magic board reset value (probably some watchdog behind it) */ 813 #define MP_BOARD_RESET_MAGIC 0x10000 814 815 typedef struct mv88w8618_timer_state { 816 ptimer_state *ptimer; 817 uint32_t limit; 818 int freq; 819 qemu_irq irq; 820 } mv88w8618_timer_state; 821 822 #define TYPE_MV88W8618_PIT "mv88w8618_pit" 823 #define MV88W8618_PIT(obj) \ 824 OBJECT_CHECK(mv88w8618_pit_state, (obj), TYPE_MV88W8618_PIT) 825 826 typedef struct mv88w8618_pit_state { 827 /*< private >*/ 828 SysBusDevice parent_obj; 829 /*< public >*/ 830 831 MemoryRegion iomem; 832 mv88w8618_timer_state timer[4]; 833 } mv88w8618_pit_state; 834 835 static void mv88w8618_timer_tick(void *opaque) 836 { 837 mv88w8618_timer_state *s = opaque; 838 839 qemu_irq_raise(s->irq); 840 } 841 842 static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s, 843 uint32_t freq) 844 { 845 QEMUBH *bh; 846 847 sysbus_init_irq(dev, &s->irq); 848 s->freq = freq; 849 850 bh = qemu_bh_new(mv88w8618_timer_tick, s); 851 s->ptimer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); 852 } 853 854 static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset, 855 unsigned size) 856 { 857 mv88w8618_pit_state *s = opaque; 858 mv88w8618_timer_state *t; 859 860 switch (offset) { 861 case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE: 862 t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2]; 863 return ptimer_get_count(t->ptimer); 864 865 default: 866 return 0; 867 } 868 } 869 870 static void mv88w8618_pit_write(void *opaque, hwaddr offset, 871 uint64_t value, unsigned size) 872 { 873 mv88w8618_pit_state *s = opaque; 874 mv88w8618_timer_state *t; 875 int i; 876 877 switch (offset) { 878 case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH: 879 t = &s->timer[offset >> 2]; 880 t->limit = value; 881 if (t->limit > 0) { 882 ptimer_set_limit(t->ptimer, t->limit, 1); 883 } else { 884 ptimer_stop(t->ptimer); 885 } 886 break; 887 888 case MP_PIT_CONTROL: 889 for (i = 0; i < 4; i++) { 890 t = &s->timer[i]; 891 if (value & 0xf && t->limit > 0) { 892 ptimer_set_limit(t->ptimer, t->limit, 0); 893 ptimer_set_freq(t->ptimer, t->freq); 894 ptimer_run(t->ptimer, 0); 895 } else { 896 ptimer_stop(t->ptimer); 897 } 898 value >>= 4; 899 } 900 break; 901 902 case MP_BOARD_RESET: 903 if (value == MP_BOARD_RESET_MAGIC) { 904 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 905 } 906 break; 907 } 908 } 909 910 static void mv88w8618_pit_reset(DeviceState *d) 911 { 912 mv88w8618_pit_state *s = MV88W8618_PIT(d); 913 int i; 914 915 for (i = 0; i < 4; i++) { 916 ptimer_stop(s->timer[i].ptimer); 917 s->timer[i].limit = 0; 918 } 919 } 920 921 static const MemoryRegionOps mv88w8618_pit_ops = { 922 .read = mv88w8618_pit_read, 923 .write = mv88w8618_pit_write, 924 .endianness = DEVICE_NATIVE_ENDIAN, 925 }; 926 927 static void mv88w8618_pit_init(Object *obj) 928 { 929 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 930 mv88w8618_pit_state *s = MV88W8618_PIT(dev); 931 int i; 932 933 /* Letting them all run at 1 MHz is likely just a pragmatic 934 * simplification. */ 935 for (i = 0; i < 4; i++) { 936 mv88w8618_timer_init(dev, &s->timer[i], 1000000); 937 } 938 939 memory_region_init_io(&s->iomem, obj, &mv88w8618_pit_ops, s, 940 "musicpal-pit", MP_PIT_SIZE); 941 sysbus_init_mmio(dev, &s->iomem); 942 } 943 944 static const VMStateDescription mv88w8618_timer_vmsd = { 945 .name = "timer", 946 .version_id = 1, 947 .minimum_version_id = 1, 948 .fields = (VMStateField[]) { 949 VMSTATE_PTIMER(ptimer, mv88w8618_timer_state), 950 VMSTATE_UINT32(limit, mv88w8618_timer_state), 951 VMSTATE_END_OF_LIST() 952 } 953 }; 954 955 static const VMStateDescription mv88w8618_pit_vmsd = { 956 .name = "mv88w8618_pit", 957 .version_id = 1, 958 .minimum_version_id = 1, 959 .fields = (VMStateField[]) { 960 VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1, 961 mv88w8618_timer_vmsd, mv88w8618_timer_state), 962 VMSTATE_END_OF_LIST() 963 } 964 }; 965 966 static void mv88w8618_pit_class_init(ObjectClass *klass, void *data) 967 { 968 DeviceClass *dc = DEVICE_CLASS(klass); 969 970 dc->reset = mv88w8618_pit_reset; 971 dc->vmsd = &mv88w8618_pit_vmsd; 972 } 973 974 static const TypeInfo mv88w8618_pit_info = { 975 .name = TYPE_MV88W8618_PIT, 976 .parent = TYPE_SYS_BUS_DEVICE, 977 .instance_size = sizeof(mv88w8618_pit_state), 978 .instance_init = mv88w8618_pit_init, 979 .class_init = mv88w8618_pit_class_init, 980 }; 981 982 /* Flash config register offsets */ 983 #define MP_FLASHCFG_CFGR0 0x04 984 985 #define TYPE_MV88W8618_FLASHCFG "mv88w8618_flashcfg" 986 #define MV88W8618_FLASHCFG(obj) \ 987 OBJECT_CHECK(mv88w8618_flashcfg_state, (obj), TYPE_MV88W8618_FLASHCFG) 988 989 typedef struct mv88w8618_flashcfg_state { 990 /*< private >*/ 991 SysBusDevice parent_obj; 992 /*< public >*/ 993 994 MemoryRegion iomem; 995 uint32_t cfgr0; 996 } mv88w8618_flashcfg_state; 997 998 static uint64_t mv88w8618_flashcfg_read(void *opaque, 999 hwaddr offset, 1000 unsigned size) 1001 { 1002 mv88w8618_flashcfg_state *s = opaque; 1003 1004 switch (offset) { 1005 case MP_FLASHCFG_CFGR0: 1006 return s->cfgr0; 1007 1008 default: 1009 return 0; 1010 } 1011 } 1012 1013 static void mv88w8618_flashcfg_write(void *opaque, hwaddr offset, 1014 uint64_t value, unsigned size) 1015 { 1016 mv88w8618_flashcfg_state *s = opaque; 1017 1018 switch (offset) { 1019 case MP_FLASHCFG_CFGR0: 1020 s->cfgr0 = value; 1021 break; 1022 } 1023 } 1024 1025 static const MemoryRegionOps mv88w8618_flashcfg_ops = { 1026 .read = mv88w8618_flashcfg_read, 1027 .write = mv88w8618_flashcfg_write, 1028 .endianness = DEVICE_NATIVE_ENDIAN, 1029 }; 1030 1031 static void mv88w8618_flashcfg_init(Object *obj) 1032 { 1033 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 1034 mv88w8618_flashcfg_state *s = MV88W8618_FLASHCFG(dev); 1035 1036 s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */ 1037 memory_region_init_io(&s->iomem, obj, &mv88w8618_flashcfg_ops, s, 1038 "musicpal-flashcfg", MP_FLASHCFG_SIZE); 1039 sysbus_init_mmio(dev, &s->iomem); 1040 } 1041 1042 static const VMStateDescription mv88w8618_flashcfg_vmsd = { 1043 .name = "mv88w8618_flashcfg", 1044 .version_id = 1, 1045 .minimum_version_id = 1, 1046 .fields = (VMStateField[]) { 1047 VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state), 1048 VMSTATE_END_OF_LIST() 1049 } 1050 }; 1051 1052 static void mv88w8618_flashcfg_class_init(ObjectClass *klass, void *data) 1053 { 1054 DeviceClass *dc = DEVICE_CLASS(klass); 1055 1056 dc->vmsd = &mv88w8618_flashcfg_vmsd; 1057 } 1058 1059 static const TypeInfo mv88w8618_flashcfg_info = { 1060 .name = TYPE_MV88W8618_FLASHCFG, 1061 .parent = TYPE_SYS_BUS_DEVICE, 1062 .instance_size = sizeof(mv88w8618_flashcfg_state), 1063 .instance_init = mv88w8618_flashcfg_init, 1064 .class_init = mv88w8618_flashcfg_class_init, 1065 }; 1066 1067 /* Misc register offsets */ 1068 #define MP_MISC_BOARD_REVISION 0x18 1069 1070 #define MP_BOARD_REVISION 0x31 1071 1072 typedef struct { 1073 SysBusDevice parent_obj; 1074 MemoryRegion iomem; 1075 } MusicPalMiscState; 1076 1077 #define TYPE_MUSICPAL_MISC "musicpal-misc" 1078 #define MUSICPAL_MISC(obj) \ 1079 OBJECT_CHECK(MusicPalMiscState, (obj), TYPE_MUSICPAL_MISC) 1080 1081 static uint64_t musicpal_misc_read(void *opaque, hwaddr offset, 1082 unsigned size) 1083 { 1084 switch (offset) { 1085 case MP_MISC_BOARD_REVISION: 1086 return MP_BOARD_REVISION; 1087 1088 default: 1089 return 0; 1090 } 1091 } 1092 1093 static void musicpal_misc_write(void *opaque, hwaddr offset, 1094 uint64_t value, unsigned size) 1095 { 1096 } 1097 1098 static const MemoryRegionOps musicpal_misc_ops = { 1099 .read = musicpal_misc_read, 1100 .write = musicpal_misc_write, 1101 .endianness = DEVICE_NATIVE_ENDIAN, 1102 }; 1103 1104 static void musicpal_misc_init(Object *obj) 1105 { 1106 SysBusDevice *sd = SYS_BUS_DEVICE(obj); 1107 MusicPalMiscState *s = MUSICPAL_MISC(obj); 1108 1109 memory_region_init_io(&s->iomem, OBJECT(s), &musicpal_misc_ops, NULL, 1110 "musicpal-misc", MP_MISC_SIZE); 1111 sysbus_init_mmio(sd, &s->iomem); 1112 } 1113 1114 static const TypeInfo musicpal_misc_info = { 1115 .name = TYPE_MUSICPAL_MISC, 1116 .parent = TYPE_SYS_BUS_DEVICE, 1117 .instance_init = musicpal_misc_init, 1118 .instance_size = sizeof(MusicPalMiscState), 1119 }; 1120 1121 /* WLAN register offsets */ 1122 #define MP_WLAN_MAGIC1 0x11c 1123 #define MP_WLAN_MAGIC2 0x124 1124 1125 static uint64_t mv88w8618_wlan_read(void *opaque, hwaddr offset, 1126 unsigned size) 1127 { 1128 switch (offset) { 1129 /* Workaround to allow loading the binary-only wlandrv.ko crap 1130 * from the original Freecom firmware. */ 1131 case MP_WLAN_MAGIC1: 1132 return ~3; 1133 case MP_WLAN_MAGIC2: 1134 return -1; 1135 1136 default: 1137 return 0; 1138 } 1139 } 1140 1141 static void mv88w8618_wlan_write(void *opaque, hwaddr offset, 1142 uint64_t value, unsigned size) 1143 { 1144 } 1145 1146 static const MemoryRegionOps mv88w8618_wlan_ops = { 1147 .read = mv88w8618_wlan_read, 1148 .write =mv88w8618_wlan_write, 1149 .endianness = DEVICE_NATIVE_ENDIAN, 1150 }; 1151 1152 static void mv88w8618_wlan_realize(DeviceState *dev, Error **errp) 1153 { 1154 MemoryRegion *iomem = g_new(MemoryRegion, 1); 1155 1156 memory_region_init_io(iomem, OBJECT(dev), &mv88w8618_wlan_ops, NULL, 1157 "musicpal-wlan", MP_WLAN_SIZE); 1158 sysbus_init_mmio(SYS_BUS_DEVICE(dev), iomem); 1159 } 1160 1161 /* GPIO register offsets */ 1162 #define MP_GPIO_OE_LO 0x008 1163 #define MP_GPIO_OUT_LO 0x00c 1164 #define MP_GPIO_IN_LO 0x010 1165 #define MP_GPIO_IER_LO 0x014 1166 #define MP_GPIO_IMR_LO 0x018 1167 #define MP_GPIO_ISR_LO 0x020 1168 #define MP_GPIO_OE_HI 0x508 1169 #define MP_GPIO_OUT_HI 0x50c 1170 #define MP_GPIO_IN_HI 0x510 1171 #define MP_GPIO_IER_HI 0x514 1172 #define MP_GPIO_IMR_HI 0x518 1173 #define MP_GPIO_ISR_HI 0x520 1174 1175 /* GPIO bits & masks */ 1176 #define MP_GPIO_LCD_BRIGHTNESS 0x00070000 1177 #define MP_GPIO_I2C_DATA_BIT 29 1178 #define MP_GPIO_I2C_CLOCK_BIT 30 1179 1180 /* LCD brightness bits in GPIO_OE_HI */ 1181 #define MP_OE_LCD_BRIGHTNESS 0x0007 1182 1183 #define TYPE_MUSICPAL_GPIO "musicpal_gpio" 1184 #define MUSICPAL_GPIO(obj) \ 1185 OBJECT_CHECK(musicpal_gpio_state, (obj), TYPE_MUSICPAL_GPIO) 1186 1187 typedef struct musicpal_gpio_state { 1188 /*< private >*/ 1189 SysBusDevice parent_obj; 1190 /*< public >*/ 1191 1192 MemoryRegion iomem; 1193 uint32_t lcd_brightness; 1194 uint32_t out_state; 1195 uint32_t in_state; 1196 uint32_t ier; 1197 uint32_t imr; 1198 uint32_t isr; 1199 qemu_irq irq; 1200 qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */ 1201 } musicpal_gpio_state; 1202 1203 static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) { 1204 int i; 1205 uint32_t brightness; 1206 1207 /* compute brightness ratio */ 1208 switch (s->lcd_brightness) { 1209 case 0x00000007: 1210 brightness = 0; 1211 break; 1212 1213 case 0x00020000: 1214 brightness = 1; 1215 break; 1216 1217 case 0x00020001: 1218 brightness = 2; 1219 break; 1220 1221 case 0x00040000: 1222 brightness = 3; 1223 break; 1224 1225 case 0x00010006: 1226 brightness = 4; 1227 break; 1228 1229 case 0x00020005: 1230 brightness = 5; 1231 break; 1232 1233 case 0x00040003: 1234 brightness = 6; 1235 break; 1236 1237 case 0x00030004: 1238 default: 1239 brightness = 7; 1240 } 1241 1242 /* set lcd brightness GPIOs */ 1243 for (i = 0; i <= 2; i++) { 1244 qemu_set_irq(s->out[i], (brightness >> i) & 1); 1245 } 1246 } 1247 1248 static void musicpal_gpio_pin_event(void *opaque, int pin, int level) 1249 { 1250 musicpal_gpio_state *s = opaque; 1251 uint32_t mask = 1 << pin; 1252 uint32_t delta = level << pin; 1253 uint32_t old = s->in_state & mask; 1254 1255 s->in_state &= ~mask; 1256 s->in_state |= delta; 1257 1258 if ((old ^ delta) && 1259 ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) { 1260 s->isr = mask; 1261 qemu_irq_raise(s->irq); 1262 } 1263 } 1264 1265 static uint64_t musicpal_gpio_read(void *opaque, hwaddr offset, 1266 unsigned size) 1267 { 1268 musicpal_gpio_state *s = opaque; 1269 1270 switch (offset) { 1271 case MP_GPIO_OE_HI: /* used for LCD brightness control */ 1272 return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS; 1273 1274 case MP_GPIO_OUT_LO: 1275 return s->out_state & 0xFFFF; 1276 case MP_GPIO_OUT_HI: 1277 return s->out_state >> 16; 1278 1279 case MP_GPIO_IN_LO: 1280 return s->in_state & 0xFFFF; 1281 case MP_GPIO_IN_HI: 1282 return s->in_state >> 16; 1283 1284 case MP_GPIO_IER_LO: 1285 return s->ier & 0xFFFF; 1286 case MP_GPIO_IER_HI: 1287 return s->ier >> 16; 1288 1289 case MP_GPIO_IMR_LO: 1290 return s->imr & 0xFFFF; 1291 case MP_GPIO_IMR_HI: 1292 return s->imr >> 16; 1293 1294 case MP_GPIO_ISR_LO: 1295 return s->isr & 0xFFFF; 1296 case MP_GPIO_ISR_HI: 1297 return s->isr >> 16; 1298 1299 default: 1300 return 0; 1301 } 1302 } 1303 1304 static void musicpal_gpio_write(void *opaque, hwaddr offset, 1305 uint64_t value, unsigned size) 1306 { 1307 musicpal_gpio_state *s = opaque; 1308 switch (offset) { 1309 case MP_GPIO_OE_HI: /* used for LCD brightness control */ 1310 s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) | 1311 (value & MP_OE_LCD_BRIGHTNESS); 1312 musicpal_gpio_brightness_update(s); 1313 break; 1314 1315 case MP_GPIO_OUT_LO: 1316 s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF); 1317 break; 1318 case MP_GPIO_OUT_HI: 1319 s->out_state = (s->out_state & 0xFFFF) | (value << 16); 1320 s->lcd_brightness = (s->lcd_brightness & 0xFFFF) | 1321 (s->out_state & MP_GPIO_LCD_BRIGHTNESS); 1322 musicpal_gpio_brightness_update(s); 1323 qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1); 1324 qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1); 1325 break; 1326 1327 case MP_GPIO_IER_LO: 1328 s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF); 1329 break; 1330 case MP_GPIO_IER_HI: 1331 s->ier = (s->ier & 0xFFFF) | (value << 16); 1332 break; 1333 1334 case MP_GPIO_IMR_LO: 1335 s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF); 1336 break; 1337 case MP_GPIO_IMR_HI: 1338 s->imr = (s->imr & 0xFFFF) | (value << 16); 1339 break; 1340 } 1341 } 1342 1343 static const MemoryRegionOps musicpal_gpio_ops = { 1344 .read = musicpal_gpio_read, 1345 .write = musicpal_gpio_write, 1346 .endianness = DEVICE_NATIVE_ENDIAN, 1347 }; 1348 1349 static void musicpal_gpio_reset(DeviceState *d) 1350 { 1351 musicpal_gpio_state *s = MUSICPAL_GPIO(d); 1352 1353 s->lcd_brightness = 0; 1354 s->out_state = 0; 1355 s->in_state = 0xffffffff; 1356 s->ier = 0; 1357 s->imr = 0; 1358 s->isr = 0; 1359 } 1360 1361 static void musicpal_gpio_init(Object *obj) 1362 { 1363 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1364 DeviceState *dev = DEVICE(sbd); 1365 musicpal_gpio_state *s = MUSICPAL_GPIO(dev); 1366 1367 sysbus_init_irq(sbd, &s->irq); 1368 1369 memory_region_init_io(&s->iomem, obj, &musicpal_gpio_ops, s, 1370 "musicpal-gpio", MP_GPIO_SIZE); 1371 sysbus_init_mmio(sbd, &s->iomem); 1372 1373 qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out)); 1374 1375 qdev_init_gpio_in(dev, musicpal_gpio_pin_event, 32); 1376 } 1377 1378 static const VMStateDescription musicpal_gpio_vmsd = { 1379 .name = "musicpal_gpio", 1380 .version_id = 1, 1381 .minimum_version_id = 1, 1382 .fields = (VMStateField[]) { 1383 VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state), 1384 VMSTATE_UINT32(out_state, musicpal_gpio_state), 1385 VMSTATE_UINT32(in_state, musicpal_gpio_state), 1386 VMSTATE_UINT32(ier, musicpal_gpio_state), 1387 VMSTATE_UINT32(imr, musicpal_gpio_state), 1388 VMSTATE_UINT32(isr, musicpal_gpio_state), 1389 VMSTATE_END_OF_LIST() 1390 } 1391 }; 1392 1393 static void musicpal_gpio_class_init(ObjectClass *klass, void *data) 1394 { 1395 DeviceClass *dc = DEVICE_CLASS(klass); 1396 1397 dc->reset = musicpal_gpio_reset; 1398 dc->vmsd = &musicpal_gpio_vmsd; 1399 } 1400 1401 static const TypeInfo musicpal_gpio_info = { 1402 .name = TYPE_MUSICPAL_GPIO, 1403 .parent = TYPE_SYS_BUS_DEVICE, 1404 .instance_size = sizeof(musicpal_gpio_state), 1405 .instance_init = musicpal_gpio_init, 1406 .class_init = musicpal_gpio_class_init, 1407 }; 1408 1409 /* Keyboard codes & masks */ 1410 #define KEY_RELEASED 0x80 1411 #define KEY_CODE 0x7f 1412 1413 #define KEYCODE_TAB 0x0f 1414 #define KEYCODE_ENTER 0x1c 1415 #define KEYCODE_F 0x21 1416 #define KEYCODE_M 0x32 1417 1418 #define KEYCODE_EXTENDED 0xe0 1419 #define KEYCODE_UP 0x48 1420 #define KEYCODE_DOWN 0x50 1421 #define KEYCODE_LEFT 0x4b 1422 #define KEYCODE_RIGHT 0x4d 1423 1424 #define MP_KEY_WHEEL_VOL (1 << 0) 1425 #define MP_KEY_WHEEL_VOL_INV (1 << 1) 1426 #define MP_KEY_WHEEL_NAV (1 << 2) 1427 #define MP_KEY_WHEEL_NAV_INV (1 << 3) 1428 #define MP_KEY_BTN_FAVORITS (1 << 4) 1429 #define MP_KEY_BTN_MENU (1 << 5) 1430 #define MP_KEY_BTN_VOLUME (1 << 6) 1431 #define MP_KEY_BTN_NAVIGATION (1 << 7) 1432 1433 #define TYPE_MUSICPAL_KEY "musicpal_key" 1434 #define MUSICPAL_KEY(obj) \ 1435 OBJECT_CHECK(musicpal_key_state, (obj), TYPE_MUSICPAL_KEY) 1436 1437 typedef struct musicpal_key_state { 1438 /*< private >*/ 1439 SysBusDevice parent_obj; 1440 /*< public >*/ 1441 1442 MemoryRegion iomem; 1443 uint32_t kbd_extended; 1444 uint32_t pressed_keys; 1445 qemu_irq out[8]; 1446 } musicpal_key_state; 1447 1448 static void musicpal_key_event(void *opaque, int keycode) 1449 { 1450 musicpal_key_state *s = opaque; 1451 uint32_t event = 0; 1452 int i; 1453 1454 if (keycode == KEYCODE_EXTENDED) { 1455 s->kbd_extended = 1; 1456 return; 1457 } 1458 1459 if (s->kbd_extended) { 1460 switch (keycode & KEY_CODE) { 1461 case KEYCODE_UP: 1462 event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV; 1463 break; 1464 1465 case KEYCODE_DOWN: 1466 event = MP_KEY_WHEEL_NAV; 1467 break; 1468 1469 case KEYCODE_LEFT: 1470 event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV; 1471 break; 1472 1473 case KEYCODE_RIGHT: 1474 event = MP_KEY_WHEEL_VOL; 1475 break; 1476 } 1477 } else { 1478 switch (keycode & KEY_CODE) { 1479 case KEYCODE_F: 1480 event = MP_KEY_BTN_FAVORITS; 1481 break; 1482 1483 case KEYCODE_TAB: 1484 event = MP_KEY_BTN_VOLUME; 1485 break; 1486 1487 case KEYCODE_ENTER: 1488 event = MP_KEY_BTN_NAVIGATION; 1489 break; 1490 1491 case KEYCODE_M: 1492 event = MP_KEY_BTN_MENU; 1493 break; 1494 } 1495 /* Do not repeat already pressed buttons */ 1496 if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) { 1497 event = 0; 1498 } 1499 } 1500 1501 if (event) { 1502 /* Raise GPIO pin first if repeating a key */ 1503 if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) { 1504 for (i = 0; i <= 7; i++) { 1505 if (event & (1 << i)) { 1506 qemu_set_irq(s->out[i], 1); 1507 } 1508 } 1509 } 1510 for (i = 0; i <= 7; i++) { 1511 if (event & (1 << i)) { 1512 qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED)); 1513 } 1514 } 1515 if (keycode & KEY_RELEASED) { 1516 s->pressed_keys &= ~event; 1517 } else { 1518 s->pressed_keys |= event; 1519 } 1520 } 1521 1522 s->kbd_extended = 0; 1523 } 1524 1525 static void musicpal_key_init(Object *obj) 1526 { 1527 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1528 DeviceState *dev = DEVICE(sbd); 1529 musicpal_key_state *s = MUSICPAL_KEY(dev); 1530 1531 memory_region_init(&s->iomem, obj, "dummy", 0); 1532 sysbus_init_mmio(sbd, &s->iomem); 1533 1534 s->kbd_extended = 0; 1535 s->pressed_keys = 0; 1536 1537 qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out)); 1538 1539 qemu_add_kbd_event_handler(musicpal_key_event, s); 1540 } 1541 1542 static const VMStateDescription musicpal_key_vmsd = { 1543 .name = "musicpal_key", 1544 .version_id = 1, 1545 .minimum_version_id = 1, 1546 .fields = (VMStateField[]) { 1547 VMSTATE_UINT32(kbd_extended, musicpal_key_state), 1548 VMSTATE_UINT32(pressed_keys, musicpal_key_state), 1549 VMSTATE_END_OF_LIST() 1550 } 1551 }; 1552 1553 static void musicpal_key_class_init(ObjectClass *klass, void *data) 1554 { 1555 DeviceClass *dc = DEVICE_CLASS(klass); 1556 1557 dc->vmsd = &musicpal_key_vmsd; 1558 } 1559 1560 static const TypeInfo musicpal_key_info = { 1561 .name = TYPE_MUSICPAL_KEY, 1562 .parent = TYPE_SYS_BUS_DEVICE, 1563 .instance_size = sizeof(musicpal_key_state), 1564 .instance_init = musicpal_key_init, 1565 .class_init = musicpal_key_class_init, 1566 }; 1567 1568 static struct arm_boot_info musicpal_binfo = { 1569 .loader_start = 0x0, 1570 .board_id = 0x20e, 1571 }; 1572 1573 static void musicpal_init(MachineState *machine) 1574 { 1575 const char *kernel_filename = machine->kernel_filename; 1576 const char *kernel_cmdline = machine->kernel_cmdline; 1577 const char *initrd_filename = machine->initrd_filename; 1578 ARMCPU *cpu; 1579 qemu_irq pic[32]; 1580 DeviceState *dev; 1581 DeviceState *i2c_dev; 1582 DeviceState *lcd_dev; 1583 DeviceState *key_dev; 1584 DeviceState *wm8750_dev; 1585 SysBusDevice *s; 1586 I2CBus *i2c; 1587 int i; 1588 unsigned long flash_size; 1589 DriveInfo *dinfo; 1590 MemoryRegion *address_space_mem = get_system_memory(); 1591 MemoryRegion *ram = g_new(MemoryRegion, 1); 1592 MemoryRegion *sram = g_new(MemoryRegion, 1); 1593 1594 cpu = ARM_CPU(cpu_create(machine->cpu_type)); 1595 1596 /* For now we use a fixed - the original - RAM size */ 1597 memory_region_allocate_system_memory(ram, NULL, "musicpal.ram", 1598 MP_RAM_DEFAULT_SIZE); 1599 memory_region_add_subregion(address_space_mem, 0, ram); 1600 1601 memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE, 1602 &error_fatal); 1603 memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram); 1604 1605 dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE, 1606 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); 1607 for (i = 0; i < 32; i++) { 1608 pic[i] = qdev_get_gpio_in(dev, i); 1609 } 1610 sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ], 1611 pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], 1612 pic[MP_TIMER4_IRQ], NULL); 1613 1614 if (serial_hd(0)) { 1615 serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1616 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN); 1617 } 1618 if (serial_hd(1)) { 1619 serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1620 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN); 1621 } 1622 1623 /* Register flash */ 1624 dinfo = drive_get(IF_PFLASH, 0, 0); 1625 if (dinfo) { 1626 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 1627 1628 flash_size = blk_getlength(blk); 1629 if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 && 1630 flash_size != 32*1024*1024) { 1631 error_report("Invalid flash image size"); 1632 exit(1); 1633 } 1634 1635 /* 1636 * The original U-Boot accesses the flash at 0xFE000000 instead of 1637 * 0xFF800000 (if there is 8 MB flash). So remap flash access if the 1638 * image is smaller than 32 MB. 1639 */ 1640 #ifdef TARGET_WORDS_BIGENDIAN 1641 pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX, 1642 "musicpal.flash", flash_size, 1643 blk, 0x10000, 1644 MP_FLASH_SIZE_MAX / flash_size, 1645 2, 0x00BF, 0x236D, 0x0000, 0x0000, 1646 0x5555, 0x2AAA, 1); 1647 #else 1648 pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX, 1649 "musicpal.flash", flash_size, 1650 blk, 0x10000, 1651 MP_FLASH_SIZE_MAX / flash_size, 1652 2, 0x00BF, 0x236D, 0x0000, 0x0000, 1653 0x5555, 0x2AAA, 0); 1654 #endif 1655 1656 } 1657 sysbus_create_simple(TYPE_MV88W8618_FLASHCFG, MP_FLASHCFG_BASE, NULL); 1658 1659 qemu_check_nic_model(&nd_table[0], "mv88w8618"); 1660 dev = qdev_create(NULL, TYPE_MV88W8618_ETH); 1661 qdev_set_nic_properties(dev, &nd_table[0]); 1662 qdev_init_nofail(dev); 1663 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE); 1664 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]); 1665 1666 sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); 1667 1668 sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL); 1669 1670 dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE, 1671 pic[MP_GPIO_IRQ]); 1672 i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL); 1673 i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c"); 1674 1675 lcd_dev = sysbus_create_simple(TYPE_MUSICPAL_LCD, MP_LCD_BASE, NULL); 1676 key_dev = sysbus_create_simple(TYPE_MUSICPAL_KEY, -1, NULL); 1677 1678 /* I2C read data */ 1679 qdev_connect_gpio_out(i2c_dev, 0, 1680 qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT)); 1681 /* I2C data */ 1682 qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0)); 1683 /* I2C clock */ 1684 qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1)); 1685 1686 for (i = 0; i < 3; i++) { 1687 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i)); 1688 } 1689 for (i = 0; i < 4; i++) { 1690 qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8)); 1691 } 1692 for (i = 4; i < 8; i++) { 1693 qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15)); 1694 } 1695 1696 wm8750_dev = i2c_create_slave(i2c, TYPE_WM8750, MP_WM_ADDR); 1697 dev = qdev_create(NULL, TYPE_MV88W8618_AUDIO); 1698 s = SYS_BUS_DEVICE(dev); 1699 object_property_set_link(OBJECT(dev), OBJECT(wm8750_dev), 1700 "wm8750", NULL); 1701 qdev_init_nofail(dev); 1702 sysbus_mmio_map(s, 0, MP_AUDIO_BASE); 1703 sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]); 1704 1705 musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; 1706 musicpal_binfo.kernel_filename = kernel_filename; 1707 musicpal_binfo.kernel_cmdline = kernel_cmdline; 1708 musicpal_binfo.initrd_filename = initrd_filename; 1709 arm_load_kernel(cpu, &musicpal_binfo); 1710 } 1711 1712 static void musicpal_machine_init(MachineClass *mc) 1713 { 1714 mc->desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)"; 1715 mc->init = musicpal_init; 1716 mc->ignore_memory_transaction_failures = true; 1717 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 1718 } 1719 1720 DEFINE_MACHINE("musicpal", musicpal_machine_init) 1721 1722 static void mv88w8618_wlan_class_init(ObjectClass *klass, void *data) 1723 { 1724 DeviceClass *dc = DEVICE_CLASS(klass); 1725 1726 dc->realize = mv88w8618_wlan_realize; 1727 } 1728 1729 static const TypeInfo mv88w8618_wlan_info = { 1730 .name = "mv88w8618_wlan", 1731 .parent = TYPE_SYS_BUS_DEVICE, 1732 .instance_size = sizeof(SysBusDevice), 1733 .class_init = mv88w8618_wlan_class_init, 1734 }; 1735 1736 static void musicpal_register_types(void) 1737 { 1738 type_register_static(&mv88w8618_pic_info); 1739 type_register_static(&mv88w8618_pit_info); 1740 type_register_static(&mv88w8618_flashcfg_info); 1741 type_register_static(&mv88w8618_eth_info); 1742 type_register_static(&mv88w8618_wlan_info); 1743 type_register_static(&musicpal_lcd_info); 1744 type_register_static(&musicpal_gpio_info); 1745 type_register_static(&musicpal_key_info); 1746 type_register_static(&musicpal_misc_info); 1747 } 1748 1749 type_init(musicpal_register_types) 1750