1 /* 2 * Marvell MV88W8618 / Freecom MusicPal emulation. 3 * 4 * Copyright (c) 2008 Jan Kiszka 5 * 6 * This code is licensed under the GNU GPL v2. 7 * 8 * Contributions after 2012-01-13 are licensed under the terms of the 9 * GNU GPL, version 2 or (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "cpu.h" 15 #include "hw/sysbus.h" 16 #include "migration/vmstate.h" 17 #include "hw/arm/boot.h" 18 #include "net/net.h" 19 #include "sysemu/sysemu.h" 20 #include "hw/boards.h" 21 #include "hw/char/serial.h" 22 #include "qemu/timer.h" 23 #include "hw/ptimer.h" 24 #include "hw/qdev-properties.h" 25 #include "hw/block/flash.h" 26 #include "ui/console.h" 27 #include "hw/i2c/i2c.h" 28 #include "hw/irq.h" 29 #include "hw/or-irq.h" 30 #include "hw/audio/wm8750.h" 31 #include "sysemu/block-backend.h" 32 #include "sysemu/runstate.h" 33 #include "sysemu/dma.h" 34 #include "ui/pixel_ops.h" 35 #include "qemu/cutils.h" 36 #include "qom/object.h" 37 38 #define MP_MISC_BASE 0x80002000 39 #define MP_MISC_SIZE 0x00001000 40 41 #define MP_ETH_BASE 0x80008000 42 #define MP_ETH_SIZE 0x00001000 43 44 #define MP_WLAN_BASE 0x8000C000 45 #define MP_WLAN_SIZE 0x00000800 46 47 #define MP_UART1_BASE 0x8000C840 48 #define MP_UART2_BASE 0x8000C940 49 50 #define MP_GPIO_BASE 0x8000D000 51 #define MP_GPIO_SIZE 0x00001000 52 53 #define MP_FLASHCFG_BASE 0x90006000 54 #define MP_FLASHCFG_SIZE 0x00001000 55 56 #define MP_AUDIO_BASE 0x90007000 57 58 #define MP_PIC_BASE 0x90008000 59 #define MP_PIC_SIZE 0x00001000 60 61 #define MP_PIT_BASE 0x90009000 62 #define MP_PIT_SIZE 0x00001000 63 64 #define MP_LCD_BASE 0x9000c000 65 #define MP_LCD_SIZE 0x00001000 66 67 #define MP_SRAM_BASE 0xC0000000 68 #define MP_SRAM_SIZE 0x00020000 69 70 #define MP_RAM_DEFAULT_SIZE 32*1024*1024 71 #define MP_FLASH_SIZE_MAX 32*1024*1024 72 73 #define MP_TIMER1_IRQ 4 74 #define MP_TIMER2_IRQ 5 75 #define MP_TIMER3_IRQ 6 76 #define MP_TIMER4_IRQ 7 77 #define MP_EHCI_IRQ 8 78 #define MP_ETH_IRQ 9 79 #define MP_UART_SHARED_IRQ 11 80 #define MP_GPIO_IRQ 12 81 #define MP_RTC_IRQ 28 82 #define MP_AUDIO_IRQ 30 83 84 /* Wolfson 8750 I2C address */ 85 #define MP_WM_ADDR 0x1A 86 87 /* Ethernet register offsets */ 88 #define MP_ETH_SMIR 0x010 89 #define MP_ETH_PCXR 0x408 90 #define MP_ETH_SDCMR 0x448 91 #define MP_ETH_ICR 0x450 92 #define MP_ETH_IMR 0x458 93 #define MP_ETH_FRDP0 0x480 94 #define MP_ETH_FRDP1 0x484 95 #define MP_ETH_FRDP2 0x488 96 #define MP_ETH_FRDP3 0x48C 97 #define MP_ETH_CRDP0 0x4A0 98 #define MP_ETH_CRDP1 0x4A4 99 #define MP_ETH_CRDP2 0x4A8 100 #define MP_ETH_CRDP3 0x4AC 101 #define MP_ETH_CTDP0 0x4E0 102 #define MP_ETH_CTDP1 0x4E4 103 104 /* MII PHY access */ 105 #define MP_ETH_SMIR_DATA 0x0000FFFF 106 #define MP_ETH_SMIR_ADDR 0x03FF0000 107 #define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */ 108 #define MP_ETH_SMIR_RDVALID (1 << 27) 109 110 /* PHY registers */ 111 #define MP_ETH_PHY1_BMSR 0x00210000 112 #define MP_ETH_PHY1_PHYSID1 0x00410000 113 #define MP_ETH_PHY1_PHYSID2 0x00610000 114 115 #define MP_PHY_BMSR_LINK 0x0004 116 #define MP_PHY_BMSR_AUTONEG 0x0008 117 118 #define MP_PHY_88E3015 0x01410E20 119 120 /* TX descriptor status */ 121 #define MP_ETH_TX_OWN (1U << 31) 122 123 /* RX descriptor status */ 124 #define MP_ETH_RX_OWN (1U << 31) 125 126 /* Interrupt cause/mask bits */ 127 #define MP_ETH_IRQ_RX_BIT 0 128 #define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT) 129 #define MP_ETH_IRQ_TXHI_BIT 2 130 #define MP_ETH_IRQ_TXLO_BIT 3 131 132 /* Port config bits */ 133 #define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */ 134 135 /* SDMA command bits */ 136 #define MP_ETH_CMD_TXHI (1 << 23) 137 #define MP_ETH_CMD_TXLO (1 << 22) 138 139 typedef struct mv88w8618_tx_desc { 140 uint32_t cmdstat; 141 uint16_t res; 142 uint16_t bytes; 143 uint32_t buffer; 144 uint32_t next; 145 } mv88w8618_tx_desc; 146 147 typedef struct mv88w8618_rx_desc { 148 uint32_t cmdstat; 149 uint16_t bytes; 150 uint16_t buffer_size; 151 uint32_t buffer; 152 uint32_t next; 153 } mv88w8618_rx_desc; 154 155 #define TYPE_MV88W8618_ETH "mv88w8618_eth" 156 OBJECT_DECLARE_SIMPLE_TYPE(mv88w8618_eth_state, MV88W8618_ETH) 157 158 struct mv88w8618_eth_state { 159 /*< private >*/ 160 SysBusDevice parent_obj; 161 /*< public >*/ 162 163 MemoryRegion iomem; 164 qemu_irq irq; 165 MemoryRegion *dma_mr; 166 AddressSpace dma_as; 167 uint32_t smir; 168 uint32_t icr; 169 uint32_t imr; 170 int mmio_index; 171 uint32_t vlan_header; 172 uint32_t tx_queue[2]; 173 uint32_t rx_queue[4]; 174 uint32_t frx_queue[4]; 175 uint32_t cur_rx[4]; 176 NICState *nic; 177 NICConf conf; 178 }; 179 180 static void eth_rx_desc_put(AddressSpace *dma_as, uint32_t addr, 181 mv88w8618_rx_desc *desc) 182 { 183 cpu_to_le32s(&desc->cmdstat); 184 cpu_to_le16s(&desc->bytes); 185 cpu_to_le16s(&desc->buffer_size); 186 cpu_to_le32s(&desc->buffer); 187 cpu_to_le32s(&desc->next); 188 dma_memory_write(dma_as, addr, desc, sizeof(*desc), MEMTXATTRS_UNSPECIFIED); 189 } 190 191 static void eth_rx_desc_get(AddressSpace *dma_as, uint32_t addr, 192 mv88w8618_rx_desc *desc) 193 { 194 dma_memory_read(dma_as, addr, desc, sizeof(*desc), MEMTXATTRS_UNSPECIFIED); 195 le32_to_cpus(&desc->cmdstat); 196 le16_to_cpus(&desc->bytes); 197 le16_to_cpus(&desc->buffer_size); 198 le32_to_cpus(&desc->buffer); 199 le32_to_cpus(&desc->next); 200 } 201 202 static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size) 203 { 204 mv88w8618_eth_state *s = qemu_get_nic_opaque(nc); 205 uint32_t desc_addr; 206 mv88w8618_rx_desc desc; 207 int i; 208 209 for (i = 0; i < 4; i++) { 210 desc_addr = s->cur_rx[i]; 211 if (!desc_addr) { 212 continue; 213 } 214 do { 215 eth_rx_desc_get(&s->dma_as, desc_addr, &desc); 216 if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) { 217 dma_memory_write(&s->dma_as, desc.buffer + s->vlan_header, 218 buf, size, MEMTXATTRS_UNSPECIFIED); 219 desc.bytes = size + s->vlan_header; 220 desc.cmdstat &= ~MP_ETH_RX_OWN; 221 s->cur_rx[i] = desc.next; 222 223 s->icr |= MP_ETH_IRQ_RX; 224 if (s->icr & s->imr) { 225 qemu_irq_raise(s->irq); 226 } 227 eth_rx_desc_put(&s->dma_as, desc_addr, &desc); 228 return size; 229 } 230 desc_addr = desc.next; 231 } while (desc_addr != s->rx_queue[i]); 232 } 233 return size; 234 } 235 236 static void eth_tx_desc_put(AddressSpace *dma_as, uint32_t addr, 237 mv88w8618_tx_desc *desc) 238 { 239 cpu_to_le32s(&desc->cmdstat); 240 cpu_to_le16s(&desc->res); 241 cpu_to_le16s(&desc->bytes); 242 cpu_to_le32s(&desc->buffer); 243 cpu_to_le32s(&desc->next); 244 dma_memory_write(dma_as, addr, desc, sizeof(*desc), MEMTXATTRS_UNSPECIFIED); 245 } 246 247 static void eth_tx_desc_get(AddressSpace *dma_as, uint32_t addr, 248 mv88w8618_tx_desc *desc) 249 { 250 dma_memory_read(dma_as, addr, desc, sizeof(*desc), MEMTXATTRS_UNSPECIFIED); 251 le32_to_cpus(&desc->cmdstat); 252 le16_to_cpus(&desc->res); 253 le16_to_cpus(&desc->bytes); 254 le32_to_cpus(&desc->buffer); 255 le32_to_cpus(&desc->next); 256 } 257 258 static void eth_send(mv88w8618_eth_state *s, int queue_index) 259 { 260 uint32_t desc_addr = s->tx_queue[queue_index]; 261 mv88w8618_tx_desc desc; 262 uint32_t next_desc; 263 uint8_t buf[2048]; 264 int len; 265 266 do { 267 eth_tx_desc_get(&s->dma_as, desc_addr, &desc); 268 next_desc = desc.next; 269 if (desc.cmdstat & MP_ETH_TX_OWN) { 270 len = desc.bytes; 271 if (len < 2048) { 272 dma_memory_read(&s->dma_as, desc.buffer, buf, len, 273 MEMTXATTRS_UNSPECIFIED); 274 qemu_send_packet(qemu_get_queue(s->nic), buf, len); 275 } 276 desc.cmdstat &= ~MP_ETH_TX_OWN; 277 s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index); 278 eth_tx_desc_put(&s->dma_as, desc_addr, &desc); 279 } 280 desc_addr = next_desc; 281 } while (desc_addr != s->tx_queue[queue_index]); 282 } 283 284 static uint64_t mv88w8618_eth_read(void *opaque, hwaddr offset, 285 unsigned size) 286 { 287 mv88w8618_eth_state *s = opaque; 288 289 switch (offset) { 290 case MP_ETH_SMIR: 291 if (s->smir & MP_ETH_SMIR_OPCODE) { 292 switch (s->smir & MP_ETH_SMIR_ADDR) { 293 case MP_ETH_PHY1_BMSR: 294 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG | 295 MP_ETH_SMIR_RDVALID; 296 case MP_ETH_PHY1_PHYSID1: 297 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID; 298 case MP_ETH_PHY1_PHYSID2: 299 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID; 300 default: 301 return MP_ETH_SMIR_RDVALID; 302 } 303 } 304 return 0; 305 306 case MP_ETH_ICR: 307 return s->icr; 308 309 case MP_ETH_IMR: 310 return s->imr; 311 312 case MP_ETH_FRDP0 ... MP_ETH_FRDP3: 313 return s->frx_queue[(offset - MP_ETH_FRDP0)/4]; 314 315 case MP_ETH_CRDP0 ... MP_ETH_CRDP3: 316 return s->rx_queue[(offset - MP_ETH_CRDP0)/4]; 317 318 case MP_ETH_CTDP0 ... MP_ETH_CTDP1: 319 return s->tx_queue[(offset - MP_ETH_CTDP0)/4]; 320 321 default: 322 return 0; 323 } 324 } 325 326 static void mv88w8618_eth_write(void *opaque, hwaddr offset, 327 uint64_t value, unsigned size) 328 { 329 mv88w8618_eth_state *s = opaque; 330 331 switch (offset) { 332 case MP_ETH_SMIR: 333 s->smir = value; 334 break; 335 336 case MP_ETH_PCXR: 337 s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2; 338 break; 339 340 case MP_ETH_SDCMR: 341 if (value & MP_ETH_CMD_TXHI) { 342 eth_send(s, 1); 343 } 344 if (value & MP_ETH_CMD_TXLO) { 345 eth_send(s, 0); 346 } 347 if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) { 348 qemu_irq_raise(s->irq); 349 } 350 break; 351 352 case MP_ETH_ICR: 353 s->icr &= value; 354 break; 355 356 case MP_ETH_IMR: 357 s->imr = value; 358 if (s->icr & s->imr) { 359 qemu_irq_raise(s->irq); 360 } 361 break; 362 363 case MP_ETH_FRDP0 ... MP_ETH_FRDP3: 364 s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value; 365 break; 366 367 case MP_ETH_CRDP0 ... MP_ETH_CRDP3: 368 s->rx_queue[(offset - MP_ETH_CRDP0)/4] = 369 s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value; 370 break; 371 372 case MP_ETH_CTDP0 ... MP_ETH_CTDP1: 373 s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value; 374 break; 375 } 376 } 377 378 static const MemoryRegionOps mv88w8618_eth_ops = { 379 .read = mv88w8618_eth_read, 380 .write = mv88w8618_eth_write, 381 .endianness = DEVICE_NATIVE_ENDIAN, 382 }; 383 384 static void eth_cleanup(NetClientState *nc) 385 { 386 mv88w8618_eth_state *s = qemu_get_nic_opaque(nc); 387 388 s->nic = NULL; 389 } 390 391 static NetClientInfo net_mv88w8618_info = { 392 .type = NET_CLIENT_DRIVER_NIC, 393 .size = sizeof(NICState), 394 .receive = eth_receive, 395 .cleanup = eth_cleanup, 396 }; 397 398 static void mv88w8618_eth_init(Object *obj) 399 { 400 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 401 DeviceState *dev = DEVICE(sbd); 402 mv88w8618_eth_state *s = MV88W8618_ETH(dev); 403 404 sysbus_init_irq(sbd, &s->irq); 405 memory_region_init_io(&s->iomem, obj, &mv88w8618_eth_ops, s, 406 "mv88w8618-eth", MP_ETH_SIZE); 407 sysbus_init_mmio(sbd, &s->iomem); 408 } 409 410 static void mv88w8618_eth_realize(DeviceState *dev, Error **errp) 411 { 412 mv88w8618_eth_state *s = MV88W8618_ETH(dev); 413 414 if (!s->dma_mr) { 415 error_setg(errp, TYPE_MV88W8618_ETH " 'dma-memory' link not set"); 416 return; 417 } 418 419 address_space_init(&s->dma_as, s->dma_mr, "emac-dma"); 420 s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf, 421 object_get_typename(OBJECT(dev)), dev->id, s); 422 } 423 424 static const VMStateDescription mv88w8618_eth_vmsd = { 425 .name = "mv88w8618_eth", 426 .version_id = 1, 427 .minimum_version_id = 1, 428 .fields = (VMStateField[]) { 429 VMSTATE_UINT32(smir, mv88w8618_eth_state), 430 VMSTATE_UINT32(icr, mv88w8618_eth_state), 431 VMSTATE_UINT32(imr, mv88w8618_eth_state), 432 VMSTATE_UINT32(vlan_header, mv88w8618_eth_state), 433 VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2), 434 VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4), 435 VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4), 436 VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4), 437 VMSTATE_END_OF_LIST() 438 } 439 }; 440 441 static Property mv88w8618_eth_properties[] = { 442 DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf), 443 DEFINE_PROP_LINK("dma-memory", mv88w8618_eth_state, dma_mr, 444 TYPE_MEMORY_REGION, MemoryRegion *), 445 DEFINE_PROP_END_OF_LIST(), 446 }; 447 448 static void mv88w8618_eth_class_init(ObjectClass *klass, void *data) 449 { 450 DeviceClass *dc = DEVICE_CLASS(klass); 451 452 dc->vmsd = &mv88w8618_eth_vmsd; 453 device_class_set_props(dc, mv88w8618_eth_properties); 454 dc->realize = mv88w8618_eth_realize; 455 } 456 457 static const TypeInfo mv88w8618_eth_info = { 458 .name = TYPE_MV88W8618_ETH, 459 .parent = TYPE_SYS_BUS_DEVICE, 460 .instance_size = sizeof(mv88w8618_eth_state), 461 .instance_init = mv88w8618_eth_init, 462 .class_init = mv88w8618_eth_class_init, 463 }; 464 465 /* LCD register offsets */ 466 #define MP_LCD_IRQCTRL 0x180 467 #define MP_LCD_IRQSTAT 0x184 468 #define MP_LCD_SPICTRL 0x1ac 469 #define MP_LCD_INST 0x1bc 470 #define MP_LCD_DATA 0x1c0 471 472 /* Mode magics */ 473 #define MP_LCD_SPI_DATA 0x00100011 474 #define MP_LCD_SPI_CMD 0x00104011 475 #define MP_LCD_SPI_INVALID 0x00000000 476 477 /* Commmands */ 478 #define MP_LCD_INST_SETPAGE0 0xB0 479 /* ... */ 480 #define MP_LCD_INST_SETPAGE7 0xB7 481 482 #define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */ 483 484 #define TYPE_MUSICPAL_LCD "musicpal_lcd" 485 OBJECT_DECLARE_SIMPLE_TYPE(musicpal_lcd_state, MUSICPAL_LCD) 486 487 struct musicpal_lcd_state { 488 /*< private >*/ 489 SysBusDevice parent_obj; 490 /*< public >*/ 491 492 MemoryRegion iomem; 493 uint32_t brightness; 494 uint32_t mode; 495 uint32_t irqctrl; 496 uint32_t page; 497 uint32_t page_off; 498 QemuConsole *con; 499 uint8_t video_ram[128*64/8]; 500 }; 501 502 static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col) 503 { 504 switch (s->brightness) { 505 case 7: 506 return col; 507 case 0: 508 return 0; 509 default: 510 return (col * s->brightness) / 7; 511 } 512 } 513 514 static inline void set_lcd_pixel32(musicpal_lcd_state *s, 515 int x, int y, uint32_t col) 516 { 517 int dx, dy; 518 DisplaySurface *surface = qemu_console_surface(s->con); 519 uint32_t *pixel = 520 &((uint32_t *) surface_data(surface))[(y * 128 * 3 + x) * 3]; 521 522 for (dy = 0; dy < 3; dy++, pixel += 127 * 3) { 523 for (dx = 0; dx < 3; dx++, pixel++) { 524 *pixel = col; 525 } 526 } 527 } 528 529 static void lcd_refresh(void *opaque) 530 { 531 musicpal_lcd_state *s = opaque; 532 int x, y, col; 533 534 col = rgb_to_pixel32(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), 535 scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), 536 scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); 537 for (x = 0; x < 128; x++) { 538 for (y = 0; y < 64; y++) { 539 if (s->video_ram[x + (y / 8) * 128] & (1 << (y % 8))) { 540 set_lcd_pixel32(s, x, y, col); 541 } else { 542 set_lcd_pixel32(s, x, y, 0); 543 } 544 } 545 } 546 547 dpy_gfx_update(s->con, 0, 0, 128*3, 64*3); 548 } 549 550 static void lcd_invalidate(void *opaque) 551 { 552 } 553 554 static void musicpal_lcd_gpio_brightness_in(void *opaque, int irq, int level) 555 { 556 musicpal_lcd_state *s = opaque; 557 s->brightness &= ~(1 << irq); 558 s->brightness |= level << irq; 559 } 560 561 static uint64_t musicpal_lcd_read(void *opaque, hwaddr offset, 562 unsigned size) 563 { 564 musicpal_lcd_state *s = opaque; 565 566 switch (offset) { 567 case MP_LCD_IRQCTRL: 568 return s->irqctrl; 569 570 default: 571 return 0; 572 } 573 } 574 575 static void musicpal_lcd_write(void *opaque, hwaddr offset, 576 uint64_t value, unsigned size) 577 { 578 musicpal_lcd_state *s = opaque; 579 580 switch (offset) { 581 case MP_LCD_IRQCTRL: 582 s->irqctrl = value; 583 break; 584 585 case MP_LCD_SPICTRL: 586 if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) { 587 s->mode = value; 588 } else { 589 s->mode = MP_LCD_SPI_INVALID; 590 } 591 break; 592 593 case MP_LCD_INST: 594 if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) { 595 s->page = value - MP_LCD_INST_SETPAGE0; 596 s->page_off = 0; 597 } 598 break; 599 600 case MP_LCD_DATA: 601 if (s->mode == MP_LCD_SPI_CMD) { 602 if (value >= MP_LCD_INST_SETPAGE0 && 603 value <= MP_LCD_INST_SETPAGE7) { 604 s->page = value - MP_LCD_INST_SETPAGE0; 605 s->page_off = 0; 606 } 607 } else if (s->mode == MP_LCD_SPI_DATA) { 608 s->video_ram[s->page*128 + s->page_off] = value; 609 s->page_off = (s->page_off + 1) & 127; 610 } 611 break; 612 } 613 } 614 615 static const MemoryRegionOps musicpal_lcd_ops = { 616 .read = musicpal_lcd_read, 617 .write = musicpal_lcd_write, 618 .endianness = DEVICE_NATIVE_ENDIAN, 619 }; 620 621 static const GraphicHwOps musicpal_gfx_ops = { 622 .invalidate = lcd_invalidate, 623 .gfx_update = lcd_refresh, 624 }; 625 626 static void musicpal_lcd_realize(DeviceState *dev, Error **errp) 627 { 628 musicpal_lcd_state *s = MUSICPAL_LCD(dev); 629 s->con = graphic_console_init(dev, 0, &musicpal_gfx_ops, s); 630 qemu_console_resize(s->con, 128 * 3, 64 * 3); 631 } 632 633 static void musicpal_lcd_init(Object *obj) 634 { 635 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 636 DeviceState *dev = DEVICE(sbd); 637 musicpal_lcd_state *s = MUSICPAL_LCD(dev); 638 639 s->brightness = 7; 640 641 memory_region_init_io(&s->iomem, obj, &musicpal_lcd_ops, s, 642 "musicpal-lcd", MP_LCD_SIZE); 643 sysbus_init_mmio(sbd, &s->iomem); 644 645 qdev_init_gpio_in(dev, musicpal_lcd_gpio_brightness_in, 3); 646 } 647 648 static const VMStateDescription musicpal_lcd_vmsd = { 649 .name = "musicpal_lcd", 650 .version_id = 1, 651 .minimum_version_id = 1, 652 .fields = (VMStateField[]) { 653 VMSTATE_UINT32(brightness, musicpal_lcd_state), 654 VMSTATE_UINT32(mode, musicpal_lcd_state), 655 VMSTATE_UINT32(irqctrl, musicpal_lcd_state), 656 VMSTATE_UINT32(page, musicpal_lcd_state), 657 VMSTATE_UINT32(page_off, musicpal_lcd_state), 658 VMSTATE_BUFFER(video_ram, musicpal_lcd_state), 659 VMSTATE_END_OF_LIST() 660 } 661 }; 662 663 static void musicpal_lcd_class_init(ObjectClass *klass, void *data) 664 { 665 DeviceClass *dc = DEVICE_CLASS(klass); 666 667 dc->vmsd = &musicpal_lcd_vmsd; 668 dc->realize = musicpal_lcd_realize; 669 } 670 671 static const TypeInfo musicpal_lcd_info = { 672 .name = TYPE_MUSICPAL_LCD, 673 .parent = TYPE_SYS_BUS_DEVICE, 674 .instance_size = sizeof(musicpal_lcd_state), 675 .instance_init = musicpal_lcd_init, 676 .class_init = musicpal_lcd_class_init, 677 }; 678 679 /* PIC register offsets */ 680 #define MP_PIC_STATUS 0x00 681 #define MP_PIC_ENABLE_SET 0x08 682 #define MP_PIC_ENABLE_CLR 0x0C 683 684 #define TYPE_MV88W8618_PIC "mv88w8618_pic" 685 OBJECT_DECLARE_SIMPLE_TYPE(mv88w8618_pic_state, MV88W8618_PIC) 686 687 struct mv88w8618_pic_state { 688 /*< private >*/ 689 SysBusDevice parent_obj; 690 /*< public >*/ 691 692 MemoryRegion iomem; 693 uint32_t level; 694 uint32_t enabled; 695 qemu_irq parent_irq; 696 }; 697 698 static void mv88w8618_pic_update(mv88w8618_pic_state *s) 699 { 700 qemu_set_irq(s->parent_irq, (s->level & s->enabled)); 701 } 702 703 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level) 704 { 705 mv88w8618_pic_state *s = opaque; 706 707 if (level) { 708 s->level |= 1 << irq; 709 } else { 710 s->level &= ~(1 << irq); 711 } 712 mv88w8618_pic_update(s); 713 } 714 715 static uint64_t mv88w8618_pic_read(void *opaque, hwaddr offset, 716 unsigned size) 717 { 718 mv88w8618_pic_state *s = opaque; 719 720 switch (offset) { 721 case MP_PIC_STATUS: 722 return s->level & s->enabled; 723 724 default: 725 return 0; 726 } 727 } 728 729 static void mv88w8618_pic_write(void *opaque, hwaddr offset, 730 uint64_t value, unsigned size) 731 { 732 mv88w8618_pic_state *s = opaque; 733 734 switch (offset) { 735 case MP_PIC_ENABLE_SET: 736 s->enabled |= value; 737 break; 738 739 case MP_PIC_ENABLE_CLR: 740 s->enabled &= ~value; 741 s->level &= ~value; 742 break; 743 } 744 mv88w8618_pic_update(s); 745 } 746 747 static void mv88w8618_pic_reset(DeviceState *d) 748 { 749 mv88w8618_pic_state *s = MV88W8618_PIC(d); 750 751 s->level = 0; 752 s->enabled = 0; 753 } 754 755 static const MemoryRegionOps mv88w8618_pic_ops = { 756 .read = mv88w8618_pic_read, 757 .write = mv88w8618_pic_write, 758 .endianness = DEVICE_NATIVE_ENDIAN, 759 }; 760 761 static void mv88w8618_pic_init(Object *obj) 762 { 763 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 764 mv88w8618_pic_state *s = MV88W8618_PIC(dev); 765 766 qdev_init_gpio_in(DEVICE(dev), mv88w8618_pic_set_irq, 32); 767 sysbus_init_irq(dev, &s->parent_irq); 768 memory_region_init_io(&s->iomem, obj, &mv88w8618_pic_ops, s, 769 "musicpal-pic", MP_PIC_SIZE); 770 sysbus_init_mmio(dev, &s->iomem); 771 } 772 773 static const VMStateDescription mv88w8618_pic_vmsd = { 774 .name = "mv88w8618_pic", 775 .version_id = 1, 776 .minimum_version_id = 1, 777 .fields = (VMStateField[]) { 778 VMSTATE_UINT32(level, mv88w8618_pic_state), 779 VMSTATE_UINT32(enabled, mv88w8618_pic_state), 780 VMSTATE_END_OF_LIST() 781 } 782 }; 783 784 static void mv88w8618_pic_class_init(ObjectClass *klass, void *data) 785 { 786 DeviceClass *dc = DEVICE_CLASS(klass); 787 788 dc->reset = mv88w8618_pic_reset; 789 dc->vmsd = &mv88w8618_pic_vmsd; 790 } 791 792 static const TypeInfo mv88w8618_pic_info = { 793 .name = TYPE_MV88W8618_PIC, 794 .parent = TYPE_SYS_BUS_DEVICE, 795 .instance_size = sizeof(mv88w8618_pic_state), 796 .instance_init = mv88w8618_pic_init, 797 .class_init = mv88w8618_pic_class_init, 798 }; 799 800 /* PIT register offsets */ 801 #define MP_PIT_TIMER1_LENGTH 0x00 802 /* ... */ 803 #define MP_PIT_TIMER4_LENGTH 0x0C 804 #define MP_PIT_CONTROL 0x10 805 #define MP_PIT_TIMER1_VALUE 0x14 806 /* ... */ 807 #define MP_PIT_TIMER4_VALUE 0x20 808 #define MP_BOARD_RESET 0x34 809 810 /* Magic board reset value (probably some watchdog behind it) */ 811 #define MP_BOARD_RESET_MAGIC 0x10000 812 813 typedef struct mv88w8618_timer_state { 814 ptimer_state *ptimer; 815 uint32_t limit; 816 int freq; 817 qemu_irq irq; 818 } mv88w8618_timer_state; 819 820 #define TYPE_MV88W8618_PIT "mv88w8618_pit" 821 OBJECT_DECLARE_SIMPLE_TYPE(mv88w8618_pit_state, MV88W8618_PIT) 822 823 struct mv88w8618_pit_state { 824 /*< private >*/ 825 SysBusDevice parent_obj; 826 /*< public >*/ 827 828 MemoryRegion iomem; 829 mv88w8618_timer_state timer[4]; 830 }; 831 832 static void mv88w8618_timer_tick(void *opaque) 833 { 834 mv88w8618_timer_state *s = opaque; 835 836 qemu_irq_raise(s->irq); 837 } 838 839 static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s, 840 uint32_t freq) 841 { 842 sysbus_init_irq(dev, &s->irq); 843 s->freq = freq; 844 845 s->ptimer = ptimer_init(mv88w8618_timer_tick, s, PTIMER_POLICY_DEFAULT); 846 } 847 848 static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset, 849 unsigned size) 850 { 851 mv88w8618_pit_state *s = opaque; 852 mv88w8618_timer_state *t; 853 854 switch (offset) { 855 case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE: 856 t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2]; 857 return ptimer_get_count(t->ptimer); 858 859 default: 860 return 0; 861 } 862 } 863 864 static void mv88w8618_pit_write(void *opaque, hwaddr offset, 865 uint64_t value, unsigned size) 866 { 867 mv88w8618_pit_state *s = opaque; 868 mv88w8618_timer_state *t; 869 int i; 870 871 switch (offset) { 872 case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH: 873 t = &s->timer[offset >> 2]; 874 t->limit = value; 875 ptimer_transaction_begin(t->ptimer); 876 if (t->limit > 0) { 877 ptimer_set_limit(t->ptimer, t->limit, 1); 878 } else { 879 ptimer_stop(t->ptimer); 880 } 881 ptimer_transaction_commit(t->ptimer); 882 break; 883 884 case MP_PIT_CONTROL: 885 for (i = 0; i < 4; i++) { 886 t = &s->timer[i]; 887 ptimer_transaction_begin(t->ptimer); 888 if (value & 0xf && t->limit > 0) { 889 ptimer_set_limit(t->ptimer, t->limit, 0); 890 ptimer_set_freq(t->ptimer, t->freq); 891 ptimer_run(t->ptimer, 0); 892 } else { 893 ptimer_stop(t->ptimer); 894 } 895 ptimer_transaction_commit(t->ptimer); 896 value >>= 4; 897 } 898 break; 899 900 case MP_BOARD_RESET: 901 if (value == MP_BOARD_RESET_MAGIC) { 902 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 903 } 904 break; 905 } 906 } 907 908 static void mv88w8618_pit_reset(DeviceState *d) 909 { 910 mv88w8618_pit_state *s = MV88W8618_PIT(d); 911 int i; 912 913 for (i = 0; i < 4; i++) { 914 mv88w8618_timer_state *t = &s->timer[i]; 915 ptimer_transaction_begin(t->ptimer); 916 ptimer_stop(t->ptimer); 917 ptimer_transaction_commit(t->ptimer); 918 t->limit = 0; 919 } 920 } 921 922 static const MemoryRegionOps mv88w8618_pit_ops = { 923 .read = mv88w8618_pit_read, 924 .write = mv88w8618_pit_write, 925 .endianness = DEVICE_NATIVE_ENDIAN, 926 }; 927 928 static void mv88w8618_pit_init(Object *obj) 929 { 930 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 931 mv88w8618_pit_state *s = MV88W8618_PIT(dev); 932 int i; 933 934 /* Letting them all run at 1 MHz is likely just a pragmatic 935 * simplification. */ 936 for (i = 0; i < 4; i++) { 937 mv88w8618_timer_init(dev, &s->timer[i], 1000000); 938 } 939 940 memory_region_init_io(&s->iomem, obj, &mv88w8618_pit_ops, s, 941 "musicpal-pit", MP_PIT_SIZE); 942 sysbus_init_mmio(dev, &s->iomem); 943 } 944 945 static void mv88w8618_pit_finalize(Object *obj) 946 { 947 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 948 mv88w8618_pit_state *s = MV88W8618_PIT(dev); 949 int i; 950 951 for (i = 0; i < 4; i++) { 952 ptimer_free(s->timer[i].ptimer); 953 } 954 } 955 956 static const VMStateDescription mv88w8618_timer_vmsd = { 957 .name = "timer", 958 .version_id = 1, 959 .minimum_version_id = 1, 960 .fields = (VMStateField[]) { 961 VMSTATE_PTIMER(ptimer, mv88w8618_timer_state), 962 VMSTATE_UINT32(limit, mv88w8618_timer_state), 963 VMSTATE_END_OF_LIST() 964 } 965 }; 966 967 static const VMStateDescription mv88w8618_pit_vmsd = { 968 .name = "mv88w8618_pit", 969 .version_id = 1, 970 .minimum_version_id = 1, 971 .fields = (VMStateField[]) { 972 VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1, 973 mv88w8618_timer_vmsd, mv88w8618_timer_state), 974 VMSTATE_END_OF_LIST() 975 } 976 }; 977 978 static void mv88w8618_pit_class_init(ObjectClass *klass, void *data) 979 { 980 DeviceClass *dc = DEVICE_CLASS(klass); 981 982 dc->reset = mv88w8618_pit_reset; 983 dc->vmsd = &mv88w8618_pit_vmsd; 984 } 985 986 static const TypeInfo mv88w8618_pit_info = { 987 .name = TYPE_MV88W8618_PIT, 988 .parent = TYPE_SYS_BUS_DEVICE, 989 .instance_size = sizeof(mv88w8618_pit_state), 990 .instance_init = mv88w8618_pit_init, 991 .instance_finalize = mv88w8618_pit_finalize, 992 .class_init = mv88w8618_pit_class_init, 993 }; 994 995 /* Flash config register offsets */ 996 #define MP_FLASHCFG_CFGR0 0x04 997 998 #define TYPE_MV88W8618_FLASHCFG "mv88w8618_flashcfg" 999 OBJECT_DECLARE_SIMPLE_TYPE(mv88w8618_flashcfg_state, MV88W8618_FLASHCFG) 1000 1001 struct mv88w8618_flashcfg_state { 1002 /*< private >*/ 1003 SysBusDevice parent_obj; 1004 /*< public >*/ 1005 1006 MemoryRegion iomem; 1007 uint32_t cfgr0; 1008 }; 1009 1010 static uint64_t mv88w8618_flashcfg_read(void *opaque, 1011 hwaddr offset, 1012 unsigned size) 1013 { 1014 mv88w8618_flashcfg_state *s = opaque; 1015 1016 switch (offset) { 1017 case MP_FLASHCFG_CFGR0: 1018 return s->cfgr0; 1019 1020 default: 1021 return 0; 1022 } 1023 } 1024 1025 static void mv88w8618_flashcfg_write(void *opaque, hwaddr offset, 1026 uint64_t value, unsigned size) 1027 { 1028 mv88w8618_flashcfg_state *s = opaque; 1029 1030 switch (offset) { 1031 case MP_FLASHCFG_CFGR0: 1032 s->cfgr0 = value; 1033 break; 1034 } 1035 } 1036 1037 static const MemoryRegionOps mv88w8618_flashcfg_ops = { 1038 .read = mv88w8618_flashcfg_read, 1039 .write = mv88w8618_flashcfg_write, 1040 .endianness = DEVICE_NATIVE_ENDIAN, 1041 }; 1042 1043 static void mv88w8618_flashcfg_init(Object *obj) 1044 { 1045 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 1046 mv88w8618_flashcfg_state *s = MV88W8618_FLASHCFG(dev); 1047 1048 s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */ 1049 memory_region_init_io(&s->iomem, obj, &mv88w8618_flashcfg_ops, s, 1050 "musicpal-flashcfg", MP_FLASHCFG_SIZE); 1051 sysbus_init_mmio(dev, &s->iomem); 1052 } 1053 1054 static const VMStateDescription mv88w8618_flashcfg_vmsd = { 1055 .name = "mv88w8618_flashcfg", 1056 .version_id = 1, 1057 .minimum_version_id = 1, 1058 .fields = (VMStateField[]) { 1059 VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state), 1060 VMSTATE_END_OF_LIST() 1061 } 1062 }; 1063 1064 static void mv88w8618_flashcfg_class_init(ObjectClass *klass, void *data) 1065 { 1066 DeviceClass *dc = DEVICE_CLASS(klass); 1067 1068 dc->vmsd = &mv88w8618_flashcfg_vmsd; 1069 } 1070 1071 static const TypeInfo mv88w8618_flashcfg_info = { 1072 .name = TYPE_MV88W8618_FLASHCFG, 1073 .parent = TYPE_SYS_BUS_DEVICE, 1074 .instance_size = sizeof(mv88w8618_flashcfg_state), 1075 .instance_init = mv88w8618_flashcfg_init, 1076 .class_init = mv88w8618_flashcfg_class_init, 1077 }; 1078 1079 /* Misc register offsets */ 1080 #define MP_MISC_BOARD_REVISION 0x18 1081 1082 #define MP_BOARD_REVISION 0x31 1083 1084 struct MusicPalMiscState { 1085 SysBusDevice parent_obj; 1086 MemoryRegion iomem; 1087 }; 1088 1089 #define TYPE_MUSICPAL_MISC "musicpal-misc" 1090 OBJECT_DECLARE_SIMPLE_TYPE(MusicPalMiscState, MUSICPAL_MISC) 1091 1092 static uint64_t musicpal_misc_read(void *opaque, hwaddr offset, 1093 unsigned size) 1094 { 1095 switch (offset) { 1096 case MP_MISC_BOARD_REVISION: 1097 return MP_BOARD_REVISION; 1098 1099 default: 1100 return 0; 1101 } 1102 } 1103 1104 static void musicpal_misc_write(void *opaque, hwaddr offset, 1105 uint64_t value, unsigned size) 1106 { 1107 } 1108 1109 static const MemoryRegionOps musicpal_misc_ops = { 1110 .read = musicpal_misc_read, 1111 .write = musicpal_misc_write, 1112 .endianness = DEVICE_NATIVE_ENDIAN, 1113 }; 1114 1115 static void musicpal_misc_init(Object *obj) 1116 { 1117 SysBusDevice *sd = SYS_BUS_DEVICE(obj); 1118 MusicPalMiscState *s = MUSICPAL_MISC(obj); 1119 1120 memory_region_init_io(&s->iomem, OBJECT(s), &musicpal_misc_ops, NULL, 1121 "musicpal-misc", MP_MISC_SIZE); 1122 sysbus_init_mmio(sd, &s->iomem); 1123 } 1124 1125 static const TypeInfo musicpal_misc_info = { 1126 .name = TYPE_MUSICPAL_MISC, 1127 .parent = TYPE_SYS_BUS_DEVICE, 1128 .instance_init = musicpal_misc_init, 1129 .instance_size = sizeof(MusicPalMiscState), 1130 }; 1131 1132 /* WLAN register offsets */ 1133 #define MP_WLAN_MAGIC1 0x11c 1134 #define MP_WLAN_MAGIC2 0x124 1135 1136 static uint64_t mv88w8618_wlan_read(void *opaque, hwaddr offset, 1137 unsigned size) 1138 { 1139 switch (offset) { 1140 /* Workaround to allow loading the binary-only wlandrv.ko crap 1141 * from the original Freecom firmware. */ 1142 case MP_WLAN_MAGIC1: 1143 return ~3; 1144 case MP_WLAN_MAGIC2: 1145 return -1; 1146 1147 default: 1148 return 0; 1149 } 1150 } 1151 1152 static void mv88w8618_wlan_write(void *opaque, hwaddr offset, 1153 uint64_t value, unsigned size) 1154 { 1155 } 1156 1157 static const MemoryRegionOps mv88w8618_wlan_ops = { 1158 .read = mv88w8618_wlan_read, 1159 .write =mv88w8618_wlan_write, 1160 .endianness = DEVICE_NATIVE_ENDIAN, 1161 }; 1162 1163 static void mv88w8618_wlan_realize(DeviceState *dev, Error **errp) 1164 { 1165 MemoryRegion *iomem = g_new(MemoryRegion, 1); 1166 1167 memory_region_init_io(iomem, OBJECT(dev), &mv88w8618_wlan_ops, NULL, 1168 "musicpal-wlan", MP_WLAN_SIZE); 1169 sysbus_init_mmio(SYS_BUS_DEVICE(dev), iomem); 1170 } 1171 1172 /* GPIO register offsets */ 1173 #define MP_GPIO_OE_LO 0x008 1174 #define MP_GPIO_OUT_LO 0x00c 1175 #define MP_GPIO_IN_LO 0x010 1176 #define MP_GPIO_IER_LO 0x014 1177 #define MP_GPIO_IMR_LO 0x018 1178 #define MP_GPIO_ISR_LO 0x020 1179 #define MP_GPIO_OE_HI 0x508 1180 #define MP_GPIO_OUT_HI 0x50c 1181 #define MP_GPIO_IN_HI 0x510 1182 #define MP_GPIO_IER_HI 0x514 1183 #define MP_GPIO_IMR_HI 0x518 1184 #define MP_GPIO_ISR_HI 0x520 1185 1186 /* GPIO bits & masks */ 1187 #define MP_GPIO_LCD_BRIGHTNESS 0x00070000 1188 #define MP_GPIO_I2C_DATA_BIT 29 1189 #define MP_GPIO_I2C_CLOCK_BIT 30 1190 1191 /* LCD brightness bits in GPIO_OE_HI */ 1192 #define MP_OE_LCD_BRIGHTNESS 0x0007 1193 1194 #define TYPE_MUSICPAL_GPIO "musicpal_gpio" 1195 OBJECT_DECLARE_SIMPLE_TYPE(musicpal_gpio_state, MUSICPAL_GPIO) 1196 1197 struct musicpal_gpio_state { 1198 /*< private >*/ 1199 SysBusDevice parent_obj; 1200 /*< public >*/ 1201 1202 MemoryRegion iomem; 1203 uint32_t lcd_brightness; 1204 uint32_t out_state; 1205 uint32_t in_state; 1206 uint32_t ier; 1207 uint32_t imr; 1208 uint32_t isr; 1209 qemu_irq irq; 1210 qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */ 1211 }; 1212 1213 static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) { 1214 int i; 1215 uint32_t brightness; 1216 1217 /* compute brightness ratio */ 1218 switch (s->lcd_brightness) { 1219 case 0x00000007: 1220 brightness = 0; 1221 break; 1222 1223 case 0x00020000: 1224 brightness = 1; 1225 break; 1226 1227 case 0x00020001: 1228 brightness = 2; 1229 break; 1230 1231 case 0x00040000: 1232 brightness = 3; 1233 break; 1234 1235 case 0x00010006: 1236 brightness = 4; 1237 break; 1238 1239 case 0x00020005: 1240 brightness = 5; 1241 break; 1242 1243 case 0x00040003: 1244 brightness = 6; 1245 break; 1246 1247 case 0x00030004: 1248 default: 1249 brightness = 7; 1250 } 1251 1252 /* set lcd brightness GPIOs */ 1253 for (i = 0; i <= 2; i++) { 1254 qemu_set_irq(s->out[i], (brightness >> i) & 1); 1255 } 1256 } 1257 1258 static void musicpal_gpio_pin_event(void *opaque, int pin, int level) 1259 { 1260 musicpal_gpio_state *s = opaque; 1261 uint32_t mask = 1 << pin; 1262 uint32_t delta = level << pin; 1263 uint32_t old = s->in_state & mask; 1264 1265 s->in_state &= ~mask; 1266 s->in_state |= delta; 1267 1268 if ((old ^ delta) && 1269 ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) { 1270 s->isr = mask; 1271 qemu_irq_raise(s->irq); 1272 } 1273 } 1274 1275 static uint64_t musicpal_gpio_read(void *opaque, hwaddr offset, 1276 unsigned size) 1277 { 1278 musicpal_gpio_state *s = opaque; 1279 1280 switch (offset) { 1281 case MP_GPIO_OE_HI: /* used for LCD brightness control */ 1282 return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS; 1283 1284 case MP_GPIO_OUT_LO: 1285 return s->out_state & 0xFFFF; 1286 case MP_GPIO_OUT_HI: 1287 return s->out_state >> 16; 1288 1289 case MP_GPIO_IN_LO: 1290 return s->in_state & 0xFFFF; 1291 case MP_GPIO_IN_HI: 1292 return s->in_state >> 16; 1293 1294 case MP_GPIO_IER_LO: 1295 return s->ier & 0xFFFF; 1296 case MP_GPIO_IER_HI: 1297 return s->ier >> 16; 1298 1299 case MP_GPIO_IMR_LO: 1300 return s->imr & 0xFFFF; 1301 case MP_GPIO_IMR_HI: 1302 return s->imr >> 16; 1303 1304 case MP_GPIO_ISR_LO: 1305 return s->isr & 0xFFFF; 1306 case MP_GPIO_ISR_HI: 1307 return s->isr >> 16; 1308 1309 default: 1310 return 0; 1311 } 1312 } 1313 1314 static void musicpal_gpio_write(void *opaque, hwaddr offset, 1315 uint64_t value, unsigned size) 1316 { 1317 musicpal_gpio_state *s = opaque; 1318 switch (offset) { 1319 case MP_GPIO_OE_HI: /* used for LCD brightness control */ 1320 s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) | 1321 (value & MP_OE_LCD_BRIGHTNESS); 1322 musicpal_gpio_brightness_update(s); 1323 break; 1324 1325 case MP_GPIO_OUT_LO: 1326 s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF); 1327 break; 1328 case MP_GPIO_OUT_HI: 1329 s->out_state = (s->out_state & 0xFFFF) | (value << 16); 1330 s->lcd_brightness = (s->lcd_brightness & 0xFFFF) | 1331 (s->out_state & MP_GPIO_LCD_BRIGHTNESS); 1332 musicpal_gpio_brightness_update(s); 1333 qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1); 1334 qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1); 1335 break; 1336 1337 case MP_GPIO_IER_LO: 1338 s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF); 1339 break; 1340 case MP_GPIO_IER_HI: 1341 s->ier = (s->ier & 0xFFFF) | (value << 16); 1342 break; 1343 1344 case MP_GPIO_IMR_LO: 1345 s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF); 1346 break; 1347 case MP_GPIO_IMR_HI: 1348 s->imr = (s->imr & 0xFFFF) | (value << 16); 1349 break; 1350 } 1351 } 1352 1353 static const MemoryRegionOps musicpal_gpio_ops = { 1354 .read = musicpal_gpio_read, 1355 .write = musicpal_gpio_write, 1356 .endianness = DEVICE_NATIVE_ENDIAN, 1357 }; 1358 1359 static void musicpal_gpio_reset(DeviceState *d) 1360 { 1361 musicpal_gpio_state *s = MUSICPAL_GPIO(d); 1362 1363 s->lcd_brightness = 0; 1364 s->out_state = 0; 1365 s->in_state = 0xffffffff; 1366 s->ier = 0; 1367 s->imr = 0; 1368 s->isr = 0; 1369 } 1370 1371 static void musicpal_gpio_init(Object *obj) 1372 { 1373 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1374 DeviceState *dev = DEVICE(sbd); 1375 musicpal_gpio_state *s = MUSICPAL_GPIO(dev); 1376 1377 sysbus_init_irq(sbd, &s->irq); 1378 1379 memory_region_init_io(&s->iomem, obj, &musicpal_gpio_ops, s, 1380 "musicpal-gpio", MP_GPIO_SIZE); 1381 sysbus_init_mmio(sbd, &s->iomem); 1382 1383 qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out)); 1384 1385 qdev_init_gpio_in(dev, musicpal_gpio_pin_event, 32); 1386 } 1387 1388 static const VMStateDescription musicpal_gpio_vmsd = { 1389 .name = "musicpal_gpio", 1390 .version_id = 1, 1391 .minimum_version_id = 1, 1392 .fields = (VMStateField[]) { 1393 VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state), 1394 VMSTATE_UINT32(out_state, musicpal_gpio_state), 1395 VMSTATE_UINT32(in_state, musicpal_gpio_state), 1396 VMSTATE_UINT32(ier, musicpal_gpio_state), 1397 VMSTATE_UINT32(imr, musicpal_gpio_state), 1398 VMSTATE_UINT32(isr, musicpal_gpio_state), 1399 VMSTATE_END_OF_LIST() 1400 } 1401 }; 1402 1403 static void musicpal_gpio_class_init(ObjectClass *klass, void *data) 1404 { 1405 DeviceClass *dc = DEVICE_CLASS(klass); 1406 1407 dc->reset = musicpal_gpio_reset; 1408 dc->vmsd = &musicpal_gpio_vmsd; 1409 } 1410 1411 static const TypeInfo musicpal_gpio_info = { 1412 .name = TYPE_MUSICPAL_GPIO, 1413 .parent = TYPE_SYS_BUS_DEVICE, 1414 .instance_size = sizeof(musicpal_gpio_state), 1415 .instance_init = musicpal_gpio_init, 1416 .class_init = musicpal_gpio_class_init, 1417 }; 1418 1419 /* Keyboard codes & masks */ 1420 #define KEY_RELEASED 0x80 1421 #define KEY_CODE 0x7f 1422 1423 #define KEYCODE_TAB 0x0f 1424 #define KEYCODE_ENTER 0x1c 1425 #define KEYCODE_F 0x21 1426 #define KEYCODE_M 0x32 1427 1428 #define KEYCODE_EXTENDED 0xe0 1429 #define KEYCODE_UP 0x48 1430 #define KEYCODE_DOWN 0x50 1431 #define KEYCODE_LEFT 0x4b 1432 #define KEYCODE_RIGHT 0x4d 1433 1434 #define MP_KEY_WHEEL_VOL (1 << 0) 1435 #define MP_KEY_WHEEL_VOL_INV (1 << 1) 1436 #define MP_KEY_WHEEL_NAV (1 << 2) 1437 #define MP_KEY_WHEEL_NAV_INV (1 << 3) 1438 #define MP_KEY_BTN_FAVORITS (1 << 4) 1439 #define MP_KEY_BTN_MENU (1 << 5) 1440 #define MP_KEY_BTN_VOLUME (1 << 6) 1441 #define MP_KEY_BTN_NAVIGATION (1 << 7) 1442 1443 #define TYPE_MUSICPAL_KEY "musicpal_key" 1444 OBJECT_DECLARE_SIMPLE_TYPE(musicpal_key_state, MUSICPAL_KEY) 1445 1446 struct musicpal_key_state { 1447 /*< private >*/ 1448 SysBusDevice parent_obj; 1449 /*< public >*/ 1450 1451 MemoryRegion iomem; 1452 uint32_t kbd_extended; 1453 uint32_t pressed_keys; 1454 qemu_irq out[8]; 1455 }; 1456 1457 static void musicpal_key_event(void *opaque, int keycode) 1458 { 1459 musicpal_key_state *s = opaque; 1460 uint32_t event = 0; 1461 int i; 1462 1463 if (keycode == KEYCODE_EXTENDED) { 1464 s->kbd_extended = 1; 1465 return; 1466 } 1467 1468 if (s->kbd_extended) { 1469 switch (keycode & KEY_CODE) { 1470 case KEYCODE_UP: 1471 event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV; 1472 break; 1473 1474 case KEYCODE_DOWN: 1475 event = MP_KEY_WHEEL_NAV; 1476 break; 1477 1478 case KEYCODE_LEFT: 1479 event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV; 1480 break; 1481 1482 case KEYCODE_RIGHT: 1483 event = MP_KEY_WHEEL_VOL; 1484 break; 1485 } 1486 } else { 1487 switch (keycode & KEY_CODE) { 1488 case KEYCODE_F: 1489 event = MP_KEY_BTN_FAVORITS; 1490 break; 1491 1492 case KEYCODE_TAB: 1493 event = MP_KEY_BTN_VOLUME; 1494 break; 1495 1496 case KEYCODE_ENTER: 1497 event = MP_KEY_BTN_NAVIGATION; 1498 break; 1499 1500 case KEYCODE_M: 1501 event = MP_KEY_BTN_MENU; 1502 break; 1503 } 1504 /* Do not repeat already pressed buttons */ 1505 if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) { 1506 event = 0; 1507 } 1508 } 1509 1510 if (event) { 1511 /* Raise GPIO pin first if repeating a key */ 1512 if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) { 1513 for (i = 0; i <= 7; i++) { 1514 if (event & (1 << i)) { 1515 qemu_set_irq(s->out[i], 1); 1516 } 1517 } 1518 } 1519 for (i = 0; i <= 7; i++) { 1520 if (event & (1 << i)) { 1521 qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED)); 1522 } 1523 } 1524 if (keycode & KEY_RELEASED) { 1525 s->pressed_keys &= ~event; 1526 } else { 1527 s->pressed_keys |= event; 1528 } 1529 } 1530 1531 s->kbd_extended = 0; 1532 } 1533 1534 static void musicpal_key_init(Object *obj) 1535 { 1536 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1537 DeviceState *dev = DEVICE(sbd); 1538 musicpal_key_state *s = MUSICPAL_KEY(dev); 1539 1540 memory_region_init(&s->iomem, obj, "dummy", 0); 1541 sysbus_init_mmio(sbd, &s->iomem); 1542 1543 s->kbd_extended = 0; 1544 s->pressed_keys = 0; 1545 1546 qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out)); 1547 1548 qemu_add_kbd_event_handler(musicpal_key_event, s); 1549 } 1550 1551 static const VMStateDescription musicpal_key_vmsd = { 1552 .name = "musicpal_key", 1553 .version_id = 1, 1554 .minimum_version_id = 1, 1555 .fields = (VMStateField[]) { 1556 VMSTATE_UINT32(kbd_extended, musicpal_key_state), 1557 VMSTATE_UINT32(pressed_keys, musicpal_key_state), 1558 VMSTATE_END_OF_LIST() 1559 } 1560 }; 1561 1562 static void musicpal_key_class_init(ObjectClass *klass, void *data) 1563 { 1564 DeviceClass *dc = DEVICE_CLASS(klass); 1565 1566 dc->vmsd = &musicpal_key_vmsd; 1567 } 1568 1569 static const TypeInfo musicpal_key_info = { 1570 .name = TYPE_MUSICPAL_KEY, 1571 .parent = TYPE_SYS_BUS_DEVICE, 1572 .instance_size = sizeof(musicpal_key_state), 1573 .instance_init = musicpal_key_init, 1574 .class_init = musicpal_key_class_init, 1575 }; 1576 1577 static struct arm_boot_info musicpal_binfo = { 1578 .loader_start = 0x0, 1579 .board_id = 0x20e, 1580 }; 1581 1582 static void musicpal_init(MachineState *machine) 1583 { 1584 ARMCPU *cpu; 1585 DeviceState *dev; 1586 DeviceState *pic; 1587 DeviceState *uart_orgate; 1588 DeviceState *i2c_dev; 1589 DeviceState *lcd_dev; 1590 DeviceState *key_dev; 1591 I2CSlave *wm8750_dev; 1592 SysBusDevice *s; 1593 I2CBus *i2c; 1594 int i; 1595 unsigned long flash_size; 1596 DriveInfo *dinfo; 1597 MachineClass *mc = MACHINE_GET_CLASS(machine); 1598 MemoryRegion *address_space_mem = get_system_memory(); 1599 MemoryRegion *sram = g_new(MemoryRegion, 1); 1600 1601 /* For now we use a fixed - the original - RAM size */ 1602 if (machine->ram_size != mc->default_ram_size) { 1603 char *sz = size_to_str(mc->default_ram_size); 1604 error_report("Invalid RAM size, should be %s", sz); 1605 g_free(sz); 1606 exit(EXIT_FAILURE); 1607 } 1608 1609 cpu = ARM_CPU(cpu_create(machine->cpu_type)); 1610 1611 memory_region_add_subregion(address_space_mem, 0, machine->ram); 1612 1613 memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE, 1614 &error_fatal); 1615 memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram); 1616 1617 pic = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE, 1618 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); 1619 sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, 1620 qdev_get_gpio_in(pic, MP_TIMER1_IRQ), 1621 qdev_get_gpio_in(pic, MP_TIMER2_IRQ), 1622 qdev_get_gpio_in(pic, MP_TIMER3_IRQ), 1623 qdev_get_gpio_in(pic, MP_TIMER4_IRQ), NULL); 1624 1625 /* Logically OR both UART IRQs together */ 1626 uart_orgate = DEVICE(object_new(TYPE_OR_IRQ)); 1627 object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal); 1628 qdev_realize_and_unref(uart_orgate, NULL, &error_fatal); 1629 qdev_connect_gpio_out(DEVICE(uart_orgate), 0, 1630 qdev_get_gpio_in(pic, MP_UART_SHARED_IRQ)); 1631 1632 serial_mm_init(address_space_mem, MP_UART1_BASE, 2, 1633 qdev_get_gpio_in(uart_orgate, 0), 1634 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN); 1635 serial_mm_init(address_space_mem, MP_UART2_BASE, 2, 1636 qdev_get_gpio_in(uart_orgate, 1), 1637 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN); 1638 1639 /* Register flash */ 1640 dinfo = drive_get(IF_PFLASH, 0, 0); 1641 if (dinfo) { 1642 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 1643 1644 flash_size = blk_getlength(blk); 1645 if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 && 1646 flash_size != 32*1024*1024) { 1647 error_report("Invalid flash image size"); 1648 exit(1); 1649 } 1650 1651 /* 1652 * The original U-Boot accesses the flash at 0xFE000000 instead of 1653 * 0xFF800000 (if there is 8 MB flash). So remap flash access if the 1654 * image is smaller than 32 MB. 1655 */ 1656 pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX, 1657 "musicpal.flash", flash_size, 1658 blk, 0x10000, 1659 MP_FLASH_SIZE_MAX / flash_size, 1660 2, 0x00BF, 0x236D, 0x0000, 0x0000, 1661 0x5555, 0x2AAA, 0); 1662 } 1663 sysbus_create_simple(TYPE_MV88W8618_FLASHCFG, MP_FLASHCFG_BASE, NULL); 1664 1665 qemu_check_nic_model(&nd_table[0], "mv88w8618"); 1666 dev = qdev_new(TYPE_MV88W8618_ETH); 1667 qdev_set_nic_properties(dev, &nd_table[0]); 1668 object_property_set_link(OBJECT(dev), "dma-memory", 1669 OBJECT(get_system_memory()), &error_fatal); 1670 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1671 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE); 1672 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 1673 qdev_get_gpio_in(pic, MP_ETH_IRQ)); 1674 1675 sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); 1676 1677 sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL); 1678 1679 dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE, 1680 qdev_get_gpio_in(pic, MP_GPIO_IRQ)); 1681 i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL); 1682 i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c"); 1683 1684 lcd_dev = sysbus_create_simple(TYPE_MUSICPAL_LCD, MP_LCD_BASE, NULL); 1685 key_dev = sysbus_create_simple(TYPE_MUSICPAL_KEY, -1, NULL); 1686 1687 /* I2C read data */ 1688 qdev_connect_gpio_out(i2c_dev, 0, 1689 qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT)); 1690 /* I2C data */ 1691 qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0)); 1692 /* I2C clock */ 1693 qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1)); 1694 1695 for (i = 0; i < 3; i++) { 1696 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i)); 1697 } 1698 for (i = 0; i < 4; i++) { 1699 qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8)); 1700 } 1701 for (i = 4; i < 8; i++) { 1702 qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15)); 1703 } 1704 1705 wm8750_dev = i2c_slave_create_simple(i2c, TYPE_WM8750, MP_WM_ADDR); 1706 dev = qdev_new(TYPE_MV88W8618_AUDIO); 1707 s = SYS_BUS_DEVICE(dev); 1708 object_property_set_link(OBJECT(dev), "wm8750", OBJECT(wm8750_dev), 1709 NULL); 1710 sysbus_realize_and_unref(s, &error_fatal); 1711 sysbus_mmio_map(s, 0, MP_AUDIO_BASE); 1712 sysbus_connect_irq(s, 0, qdev_get_gpio_in(pic, MP_AUDIO_IRQ)); 1713 1714 musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; 1715 arm_load_kernel(cpu, machine, &musicpal_binfo); 1716 } 1717 1718 static void musicpal_machine_init(MachineClass *mc) 1719 { 1720 mc->desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)"; 1721 mc->init = musicpal_init; 1722 mc->ignore_memory_transaction_failures = true; 1723 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 1724 mc->default_ram_size = MP_RAM_DEFAULT_SIZE; 1725 mc->default_ram_id = "musicpal.ram"; 1726 } 1727 1728 DEFINE_MACHINE("musicpal", musicpal_machine_init) 1729 1730 static void mv88w8618_wlan_class_init(ObjectClass *klass, void *data) 1731 { 1732 DeviceClass *dc = DEVICE_CLASS(klass); 1733 1734 dc->realize = mv88w8618_wlan_realize; 1735 } 1736 1737 static const TypeInfo mv88w8618_wlan_info = { 1738 .name = "mv88w8618_wlan", 1739 .parent = TYPE_SYS_BUS_DEVICE, 1740 .instance_size = sizeof(SysBusDevice), 1741 .class_init = mv88w8618_wlan_class_init, 1742 }; 1743 1744 static void musicpal_register_types(void) 1745 { 1746 type_register_static(&mv88w8618_pic_info); 1747 type_register_static(&mv88w8618_pit_info); 1748 type_register_static(&mv88w8618_flashcfg_info); 1749 type_register_static(&mv88w8618_eth_info); 1750 type_register_static(&mv88w8618_wlan_info); 1751 type_register_static(&musicpal_lcd_info); 1752 type_register_static(&musicpal_gpio_info); 1753 type_register_static(&musicpal_key_info); 1754 type_register_static(&musicpal_misc_info); 1755 } 1756 1757 type_init(musicpal_register_types) 1758