1 /* 2 * Arm Musca-B1 test chip board emulation 3 * 4 * Copyright (c) 2019 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* 13 * The Musca boards are a reference implementation of a system using 14 * the SSE-200 subsystem for embedded: 15 * https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-a-test-chip-board 16 * https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-b-test-chip-board 17 * We model the A and B1 variants of this board, as described in the TRMs: 18 * http://infocenter.arm.com/help/topic/com.arm.doc.101107_0000_00_en/index.html 19 * http://infocenter.arm.com/help/topic/com.arm.doc.101312_0000_00_en/index.html 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qemu/error-report.h" 24 #include "qapi/error.h" 25 #include "exec/address-spaces.h" 26 #include "sysemu/sysemu.h" 27 #include "hw/arm/boot.h" 28 #include "hw/arm/armsse.h" 29 #include "hw/boards.h" 30 #include "hw/char/pl011.h" 31 #include "hw/core/split-irq.h" 32 #include "hw/misc/tz-mpc.h" 33 #include "hw/misc/tz-ppc.h" 34 #include "hw/misc/unimp.h" 35 #include "hw/rtc/pl031.h" 36 37 #define MUSCA_NUMIRQ_MAX 96 38 #define MUSCA_PPC_MAX 3 39 #define MUSCA_MPC_MAX 5 40 41 typedef struct MPCInfo MPCInfo; 42 43 typedef enum MuscaType { 44 MUSCA_A, 45 MUSCA_B1, 46 } MuscaType; 47 48 typedef struct { 49 MachineClass parent; 50 MuscaType type; 51 uint32_t init_svtor; 52 int sram_addr_width; 53 int num_irqs; 54 const MPCInfo *mpc_info; 55 int num_mpcs; 56 } MuscaMachineClass; 57 58 typedef struct { 59 MachineState parent; 60 61 ARMSSE sse; 62 /* RAM and flash */ 63 MemoryRegion ram[MUSCA_MPC_MAX]; 64 SplitIRQ cpu_irq_splitter[MUSCA_NUMIRQ_MAX]; 65 SplitIRQ sec_resp_splitter; 66 TZPPC ppc[MUSCA_PPC_MAX]; 67 MemoryRegion container; 68 UnimplementedDeviceState eflash[2]; 69 UnimplementedDeviceState qspi; 70 TZMPC mpc[MUSCA_MPC_MAX]; 71 UnimplementedDeviceState mhu[2]; 72 UnimplementedDeviceState pwm[3]; 73 UnimplementedDeviceState i2s; 74 PL011State uart[2]; 75 UnimplementedDeviceState i2c[2]; 76 UnimplementedDeviceState spi; 77 UnimplementedDeviceState scc; 78 UnimplementedDeviceState timer; 79 PL031State rtc; 80 UnimplementedDeviceState pvt; 81 UnimplementedDeviceState sdio; 82 UnimplementedDeviceState gpio; 83 UnimplementedDeviceState cryptoisland; 84 } MuscaMachineState; 85 86 #define TYPE_MUSCA_MACHINE "musca" 87 #define TYPE_MUSCA_A_MACHINE MACHINE_TYPE_NAME("musca-a") 88 #define TYPE_MUSCA_B1_MACHINE MACHINE_TYPE_NAME("musca-b1") 89 90 #define MUSCA_MACHINE(obj) \ 91 OBJECT_CHECK(MuscaMachineState, obj, TYPE_MUSCA_MACHINE) 92 #define MUSCA_MACHINE_GET_CLASS(obj) \ 93 OBJECT_GET_CLASS(MuscaMachineClass, obj, TYPE_MUSCA_MACHINE) 94 #define MUSCA_MACHINE_CLASS(klass) \ 95 OBJECT_CLASS_CHECK(MuscaMachineClass, klass, TYPE_MUSCA_MACHINE) 96 97 /* 98 * Main SYSCLK frequency in Hz 99 * TODO this should really be different for the two cores, but we 100 * don't model that in our SSE-200 model yet. 101 */ 102 #define SYSCLK_FRQ 40000000 103 104 static qemu_irq get_sse_irq_in(MuscaMachineState *mms, int irqno) 105 { 106 /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ 107 assert(irqno < MUSCA_NUMIRQ_MAX); 108 109 return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); 110 } 111 112 /* 113 * Most of the devices in the Musca board sit behind Peripheral Protection 114 * Controllers. These data structures define the layout of which devices 115 * sit behind which PPCs. 116 * The devfn for each port is a function which creates, configures 117 * and initializes the device, returning the MemoryRegion which 118 * needs to be plugged into the downstream end of the PPC port. 119 */ 120 typedef MemoryRegion *MakeDevFn(MuscaMachineState *mms, void *opaque, 121 const char *name, hwaddr size); 122 123 typedef struct PPCPortInfo { 124 const char *name; 125 MakeDevFn *devfn; 126 void *opaque; 127 hwaddr addr; 128 hwaddr size; 129 } PPCPortInfo; 130 131 typedef struct PPCInfo { 132 const char *name; 133 PPCPortInfo ports[TZ_NUM_PORTS]; 134 } PPCInfo; 135 136 static MemoryRegion *make_unimp_dev(MuscaMachineState *mms, 137 void *opaque, const char *name, hwaddr size) 138 { 139 /* 140 * Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, 141 * and return a pointer to its MemoryRegion. 142 */ 143 UnimplementedDeviceState *uds = opaque; 144 145 object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE); 146 qdev_prop_set_string(DEVICE(uds), "name", name); 147 qdev_prop_set_uint64(DEVICE(uds), "size", size); 148 sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); 149 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); 150 } 151 152 typedef enum MPCInfoType { 153 MPC_RAM, 154 MPC_ROM, 155 MPC_CRYPTOISLAND, 156 } MPCInfoType; 157 158 struct MPCInfo { 159 const char *name; 160 hwaddr addr; 161 hwaddr size; 162 MPCInfoType type; 163 }; 164 165 /* Order of the MPCs here must match the order of the bits in SECMPCINTSTATUS */ 166 static const MPCInfo a_mpc_info[] = { { 167 .name = "qspi", 168 .type = MPC_ROM, 169 .addr = 0x00200000, 170 .size = 0x00800000, 171 }, { 172 .name = "sram", 173 .type = MPC_RAM, 174 .addr = 0x00000000, 175 .size = 0x00200000, 176 } 177 }; 178 179 static const MPCInfo b1_mpc_info[] = { { 180 .name = "qspi", 181 .type = MPC_ROM, 182 .addr = 0x00000000, 183 .size = 0x02000000, 184 }, { 185 .name = "sram", 186 .type = MPC_RAM, 187 .addr = 0x0a400000, 188 .size = 0x00080000, 189 }, { 190 .name = "eflash0", 191 .type = MPC_ROM, 192 .addr = 0x0a000000, 193 .size = 0x00200000, 194 }, { 195 .name = "eflash1", 196 .type = MPC_ROM, 197 .addr = 0x0a200000, 198 .size = 0x00200000, 199 }, { 200 .name = "cryptoisland", 201 .type = MPC_CRYPTOISLAND, 202 .addr = 0x0a000000, 203 .size = 0x00200000, 204 } 205 }; 206 207 static MemoryRegion *make_mpc(MuscaMachineState *mms, void *opaque, 208 const char *name, hwaddr size) 209 { 210 /* 211 * Create an MPC and the RAM or flash behind it. 212 * MPC 0: eFlash 0 213 * MPC 1: eFlash 1 214 * MPC 2: SRAM 215 * MPC 3: QSPI flash 216 * MPC 4: CryptoIsland 217 * For now we implement the flash regions as ROM (ie not programmable) 218 * (with their control interface memory regions being unimplemented 219 * stubs behind the PPCs). 220 * The whole CryptoIsland region behind its MPC is an unimplemented stub. 221 */ 222 MuscaMachineClass *mmc = MUSCA_MACHINE_GET_CLASS(mms); 223 TZMPC *mpc = opaque; 224 int i = mpc - &mms->mpc[0]; 225 MemoryRegion *downstream; 226 MemoryRegion *upstream; 227 UnimplementedDeviceState *uds; 228 char *mpcname; 229 const MPCInfo *mpcinfo = mmc->mpc_info; 230 231 mpcname = g_strdup_printf("%s-mpc", mpcinfo[i].name); 232 233 switch (mpcinfo[i].type) { 234 case MPC_ROM: 235 downstream = &mms->ram[i]; 236 memory_region_init_rom(downstream, NULL, mpcinfo[i].name, 237 mpcinfo[i].size, &error_fatal); 238 break; 239 case MPC_RAM: 240 downstream = &mms->ram[i]; 241 memory_region_init_ram(downstream, NULL, mpcinfo[i].name, 242 mpcinfo[i].size, &error_fatal); 243 break; 244 case MPC_CRYPTOISLAND: 245 /* We don't implement the CryptoIsland yet */ 246 uds = &mms->cryptoisland; 247 object_initialize_child(OBJECT(mms), name, uds, 248 TYPE_UNIMPLEMENTED_DEVICE); 249 qdev_prop_set_string(DEVICE(uds), "name", mpcinfo[i].name); 250 qdev_prop_set_uint64(DEVICE(uds), "size", mpcinfo[i].size); 251 sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); 252 downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); 253 break; 254 default: 255 g_assert_not_reached(); 256 } 257 258 object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC); 259 object_property_set_link(OBJECT(mpc), OBJECT(downstream), 260 "downstream", &error_fatal); 261 sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); 262 /* Map the upstream end of the MPC into system memory */ 263 upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); 264 memory_region_add_subregion(get_system_memory(), mpcinfo[i].addr, upstream); 265 /* and connect its interrupt to the SSE-200 */ 266 qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, 267 qdev_get_gpio_in_named(DEVICE(&mms->sse), 268 "mpcexp_status", i)); 269 270 g_free(mpcname); 271 /* Return the register interface MR for our caller to map behind the PPC */ 272 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); 273 } 274 275 static MemoryRegion *make_rtc(MuscaMachineState *mms, void *opaque, 276 const char *name, hwaddr size) 277 { 278 PL031State *rtc = opaque; 279 280 object_initialize_child(OBJECT(mms), name, rtc, TYPE_PL031); 281 sysbus_realize(SYS_BUS_DEVICE(rtc), &error_fatal); 282 sysbus_connect_irq(SYS_BUS_DEVICE(rtc), 0, get_sse_irq_in(mms, 39)); 283 return sysbus_mmio_get_region(SYS_BUS_DEVICE(rtc), 0); 284 } 285 286 static MemoryRegion *make_uart(MuscaMachineState *mms, void *opaque, 287 const char *name, hwaddr size) 288 { 289 PL011State *uart = opaque; 290 int i = uart - &mms->uart[0]; 291 int irqbase = 7 + i * 6; 292 SysBusDevice *s; 293 294 object_initialize_child(OBJECT(mms), name, uart, TYPE_PL011); 295 qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); 296 sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); 297 s = SYS_BUS_DEVICE(uart); 298 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqbase + 5)); /* combined */ 299 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqbase + 0)); /* RX */ 300 sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqbase + 1)); /* TX */ 301 sysbus_connect_irq(s, 3, get_sse_irq_in(mms, irqbase + 2)); /* RT */ 302 sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqbase + 3)); /* MS */ 303 sysbus_connect_irq(s, 5, get_sse_irq_in(mms, irqbase + 4)); /* E */ 304 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); 305 } 306 307 static MemoryRegion *make_musca_a_devs(MuscaMachineState *mms, void *opaque, 308 const char *name, hwaddr size) 309 { 310 /* 311 * Create the container MemoryRegion for all the devices that live 312 * behind the Musca-A PPC's single port. These devices don't have a PPC 313 * port each, but we use the PPCPortInfo struct as a convenient way 314 * to describe them. Note that addresses here are relative to the base 315 * address of the PPC port region: 0x40100000, and devices appear both 316 * at the 0x4... NS region and the 0x5... S region. 317 */ 318 int i; 319 MemoryRegion *container = &mms->container; 320 321 const PPCPortInfo devices[] = { 322 { "uart0", make_uart, &mms->uart[0], 0x1000, 0x1000 }, 323 { "uart1", make_uart, &mms->uart[1], 0x2000, 0x1000 }, 324 { "spi", make_unimp_dev, &mms->spi, 0x3000, 0x1000 }, 325 { "i2c0", make_unimp_dev, &mms->i2c[0], 0x4000, 0x1000 }, 326 { "i2c1", make_unimp_dev, &mms->i2c[1], 0x5000, 0x1000 }, 327 { "i2s", make_unimp_dev, &mms->i2s, 0x6000, 0x1000 }, 328 { "pwm0", make_unimp_dev, &mms->pwm[0], 0x7000, 0x1000 }, 329 { "rtc", make_rtc, &mms->rtc, 0x8000, 0x1000 }, 330 { "qspi", make_unimp_dev, &mms->qspi, 0xa000, 0x1000 }, 331 { "timer", make_unimp_dev, &mms->timer, 0xb000, 0x1000 }, 332 { "scc", make_unimp_dev, &mms->scc, 0xc000, 0x1000 }, 333 { "pwm1", make_unimp_dev, &mms->pwm[1], 0xe000, 0x1000 }, 334 { "pwm2", make_unimp_dev, &mms->pwm[2], 0xf000, 0x1000 }, 335 { "gpio", make_unimp_dev, &mms->gpio, 0x10000, 0x1000 }, 336 { "mpc0", make_mpc, &mms->mpc[0], 0x12000, 0x1000 }, 337 { "mpc1", make_mpc, &mms->mpc[1], 0x13000, 0x1000 }, 338 }; 339 340 memory_region_init(container, OBJECT(mms), "musca-device-container", size); 341 342 for (i = 0; i < ARRAY_SIZE(devices); i++) { 343 const PPCPortInfo *pinfo = &devices[i]; 344 MemoryRegion *mr; 345 346 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); 347 memory_region_add_subregion(container, pinfo->addr, mr); 348 } 349 350 return &mms->container; 351 } 352 353 static void musca_init(MachineState *machine) 354 { 355 MuscaMachineState *mms = MUSCA_MACHINE(machine); 356 MuscaMachineClass *mmc = MUSCA_MACHINE_GET_CLASS(mms); 357 MachineClass *mc = MACHINE_GET_CLASS(machine); 358 MemoryRegion *system_memory = get_system_memory(); 359 DeviceState *ssedev; 360 DeviceState *dev_splitter; 361 const PPCInfo *ppcs; 362 int num_ppcs; 363 int i; 364 365 assert(mmc->num_irqs <= MUSCA_NUMIRQ_MAX); 366 assert(mmc->num_mpcs <= MUSCA_MPC_MAX); 367 368 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { 369 error_report("This board can only be used with CPU %s", 370 mc->default_cpu_type); 371 exit(1); 372 } 373 374 object_initialize_child(OBJECT(machine), "sse-200", &mms->sse, 375 TYPE_SSE200); 376 ssedev = DEVICE(&mms->sse); 377 object_property_set_link(OBJECT(&mms->sse), OBJECT(system_memory), 378 "memory", &error_fatal); 379 qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs); 380 qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor); 381 qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); 382 qdev_prop_set_uint32(ssedev, "MAINCLK", SYSCLK_FRQ); 383 /* 384 * Musca-A takes the default SSE-200 FPU/DSP settings (ie no for 385 * CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0. 386 */ 387 if (mmc->type == MUSCA_B1) { 388 qdev_prop_set_bit(ssedev, "CPU0_FPU", true); 389 qdev_prop_set_bit(ssedev, "CPU0_DSP", true); 390 } 391 sysbus_realize(SYS_BUS_DEVICE(&mms->sse), &error_fatal); 392 393 /* 394 * We need to create splitters to feed the IRQ inputs 395 * for each CPU in the SSE-200 from each device in the board. 396 */ 397 for (i = 0; i < mmc->num_irqs; i++) { 398 char *name = g_strdup_printf("musca-irq-splitter%d", i); 399 SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; 400 401 object_initialize_child_with_props(OBJECT(machine), name, splitter, 402 sizeof(*splitter), TYPE_SPLIT_IRQ, 403 &error_fatal, NULL); 404 g_free(name); 405 406 object_property_set_int(OBJECT(splitter), 2, "num-lines", 407 &error_fatal); 408 qdev_realize(DEVICE(splitter), NULL, &error_fatal); 409 qdev_connect_gpio_out(DEVICE(splitter), 0, 410 qdev_get_gpio_in_named(ssedev, "EXP_IRQ", i)); 411 qdev_connect_gpio_out(DEVICE(splitter), 1, 412 qdev_get_gpio_in_named(ssedev, 413 "EXP_CPU1_IRQ", i)); 414 } 415 416 /* 417 * The sec_resp_cfg output from the SSE-200 must be split into multiple 418 * lines, one for each of the PPCs we create here. 419 */ 420 object_initialize_child_with_props(OBJECT(machine), "sec-resp-splitter", 421 &mms->sec_resp_splitter, 422 sizeof(mms->sec_resp_splitter), 423 TYPE_SPLIT_IRQ, &error_fatal, NULL); 424 425 object_property_set_int(OBJECT(&mms->sec_resp_splitter), 426 ARRAY_SIZE(mms->ppc), "num-lines", &error_fatal); 427 qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal); 428 dev_splitter = DEVICE(&mms->sec_resp_splitter); 429 qdev_connect_gpio_out_named(ssedev, "sec_resp_cfg", 0, 430 qdev_get_gpio_in(dev_splitter, 0)); 431 432 /* 433 * Most of the devices in the board are behind Peripheral Protection 434 * Controllers. The required order for initializing things is: 435 * + initialize the PPC 436 * + initialize, configure and realize downstream devices 437 * + connect downstream device MemoryRegions to the PPC 438 * + realize the PPC 439 * + map the PPC's MemoryRegions to the places in the address map 440 * where the downstream devices should appear 441 * + wire up the PPC's control lines to the SSE object 442 * 443 * The PPC mapping differs for the -A and -B1 variants; the -A version 444 * is much simpler, using only a single port of a single PPC and putting 445 * all the devices behind that. 446 */ 447 const PPCInfo a_ppcs[] = { { 448 .name = "ahb_ppcexp0", 449 .ports = { 450 { "musca-devices", make_musca_a_devs, 0, 0x40100000, 0x100000 }, 451 }, 452 }, 453 }; 454 455 /* 456 * Devices listed with an 0x4.. address appear in both the NS 0x4.. region 457 * and the 0x5.. S region. Devices listed with an 0x5.. address appear 458 * only in the S region. 459 */ 460 const PPCInfo b1_ppcs[] = { { 461 .name = "apb_ppcexp0", 462 .ports = { 463 { "eflash0", make_unimp_dev, &mms->eflash[0], 464 0x52400000, 0x1000 }, 465 { "eflash1", make_unimp_dev, &mms->eflash[1], 466 0x52500000, 0x1000 }, 467 { "qspi", make_unimp_dev, &mms->qspi, 0x42800000, 0x100000 }, 468 { "mpc0", make_mpc, &mms->mpc[0], 0x52000000, 0x1000 }, 469 { "mpc1", make_mpc, &mms->mpc[1], 0x52100000, 0x1000 }, 470 { "mpc2", make_mpc, &mms->mpc[2], 0x52200000, 0x1000 }, 471 { "mpc3", make_mpc, &mms->mpc[3], 0x52300000, 0x1000 }, 472 { "mhu0", make_unimp_dev, &mms->mhu[0], 0x42600000, 0x100000 }, 473 { "mhu1", make_unimp_dev, &mms->mhu[1], 0x42700000, 0x100000 }, 474 { }, /* port 9: unused */ 475 { }, /* port 10: unused */ 476 { }, /* port 11: unused */ 477 { }, /* port 12: unused */ 478 { }, /* port 13: unused */ 479 { "mpc4", make_mpc, &mms->mpc[4], 0x52e00000, 0x1000 }, 480 }, 481 }, { 482 .name = "apb_ppcexp1", 483 .ports = { 484 { "pwm0", make_unimp_dev, &mms->pwm[0], 0x40101000, 0x1000 }, 485 { "pwm1", make_unimp_dev, &mms->pwm[1], 0x40102000, 0x1000 }, 486 { "pwm2", make_unimp_dev, &mms->pwm[2], 0x40103000, 0x1000 }, 487 { "i2s", make_unimp_dev, &mms->i2s, 0x40104000, 0x1000 }, 488 { "uart0", make_uart, &mms->uart[0], 0x40105000, 0x1000 }, 489 { "uart1", make_uart, &mms->uart[1], 0x40106000, 0x1000 }, 490 { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40108000, 0x1000 }, 491 { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40109000, 0x1000 }, 492 { "spi", make_unimp_dev, &mms->spi, 0x4010a000, 0x1000 }, 493 { "scc", make_unimp_dev, &mms->scc, 0x5010b000, 0x1000 }, 494 { "timer", make_unimp_dev, &mms->timer, 0x4010c000, 0x1000 }, 495 { "rtc", make_rtc, &mms->rtc, 0x4010d000, 0x1000 }, 496 { "pvt", make_unimp_dev, &mms->pvt, 0x4010e000, 0x1000 }, 497 { "sdio", make_unimp_dev, &mms->sdio, 0x4010f000, 0x1000 }, 498 }, 499 }, { 500 .name = "ahb_ppcexp0", 501 .ports = { 502 { }, /* port 0: unused */ 503 { "gpio", make_unimp_dev, &mms->gpio, 0x41000000, 0x1000 }, 504 }, 505 }, 506 }; 507 508 switch (mmc->type) { 509 case MUSCA_A: 510 ppcs = a_ppcs; 511 num_ppcs = ARRAY_SIZE(a_ppcs); 512 break; 513 case MUSCA_B1: 514 ppcs = b1_ppcs; 515 num_ppcs = ARRAY_SIZE(b1_ppcs); 516 break; 517 default: 518 g_assert_not_reached(); 519 } 520 assert(num_ppcs <= MUSCA_PPC_MAX); 521 522 for (i = 0; i < num_ppcs; i++) { 523 const PPCInfo *ppcinfo = &ppcs[i]; 524 TZPPC *ppc = &mms->ppc[i]; 525 DeviceState *ppcdev; 526 int port; 527 char *gpioname; 528 529 object_initialize_child(OBJECT(machine), ppcinfo->name, ppc, 530 TYPE_TZ_PPC); 531 ppcdev = DEVICE(ppc); 532 533 for (port = 0; port < TZ_NUM_PORTS; port++) { 534 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 535 MemoryRegion *mr; 536 char *portname; 537 538 if (!pinfo->devfn) { 539 continue; 540 } 541 542 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); 543 portname = g_strdup_printf("port[%d]", port); 544 object_property_set_link(OBJECT(ppc), OBJECT(mr), 545 portname, &error_fatal); 546 g_free(portname); 547 } 548 549 sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal); 550 551 for (port = 0; port < TZ_NUM_PORTS; port++) { 552 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 553 554 if (!pinfo->devfn) { 555 continue; 556 } 557 sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); 558 559 gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); 560 qdev_connect_gpio_out_named(ssedev, gpioname, port, 561 qdev_get_gpio_in_named(ppcdev, 562 "cfg_nonsec", 563 port)); 564 g_free(gpioname); 565 gpioname = g_strdup_printf("%s_ap", ppcinfo->name); 566 qdev_connect_gpio_out_named(ssedev, gpioname, port, 567 qdev_get_gpio_in_named(ppcdev, 568 "cfg_ap", port)); 569 g_free(gpioname); 570 } 571 572 gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); 573 qdev_connect_gpio_out_named(ssedev, gpioname, 0, 574 qdev_get_gpio_in_named(ppcdev, 575 "irq_enable", 0)); 576 g_free(gpioname); 577 gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); 578 qdev_connect_gpio_out_named(ssedev, gpioname, 0, 579 qdev_get_gpio_in_named(ppcdev, 580 "irq_clear", 0)); 581 g_free(gpioname); 582 gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); 583 qdev_connect_gpio_out_named(ppcdev, "irq", 0, 584 qdev_get_gpio_in_named(ssedev, 585 gpioname, 0)); 586 g_free(gpioname); 587 588 qdev_connect_gpio_out(dev_splitter, i, 589 qdev_get_gpio_in_named(ppcdev, 590 "cfg_sec_resp", 0)); 591 } 592 593 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x2000000); 594 } 595 596 static void musca_class_init(ObjectClass *oc, void *data) 597 { 598 MachineClass *mc = MACHINE_CLASS(oc); 599 600 mc->default_cpus = 2; 601 mc->min_cpus = mc->default_cpus; 602 mc->max_cpus = mc->default_cpus; 603 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 604 mc->init = musca_init; 605 } 606 607 static void musca_a_class_init(ObjectClass *oc, void *data) 608 { 609 MachineClass *mc = MACHINE_CLASS(oc); 610 MuscaMachineClass *mmc = MUSCA_MACHINE_CLASS(oc); 611 612 mc->desc = "ARM Musca-A board (dual Cortex-M33)"; 613 mmc->type = MUSCA_A; 614 mmc->init_svtor = 0x10200000; 615 mmc->sram_addr_width = 15; 616 mmc->num_irqs = 64; 617 mmc->mpc_info = a_mpc_info; 618 mmc->num_mpcs = ARRAY_SIZE(a_mpc_info); 619 } 620 621 static void musca_b1_class_init(ObjectClass *oc, void *data) 622 { 623 MachineClass *mc = MACHINE_CLASS(oc); 624 MuscaMachineClass *mmc = MUSCA_MACHINE_CLASS(oc); 625 626 mc->desc = "ARM Musca-B1 board (dual Cortex-M33)"; 627 mmc->type = MUSCA_B1; 628 /* 629 * This matches the DAPlink firmware which boots from QSPI. There 630 * is also a firmware blob which boots from the eFlash, which 631 * uses init_svtor = 0x1A000000. QEMU doesn't currently support that, 632 * though we could in theory expose a machine property on the command 633 * line to allow the user to request eFlash boot. 634 */ 635 mmc->init_svtor = 0x10000000; 636 mmc->sram_addr_width = 17; 637 mmc->num_irqs = 96; 638 mmc->mpc_info = b1_mpc_info; 639 mmc->num_mpcs = ARRAY_SIZE(b1_mpc_info); 640 } 641 642 static const TypeInfo musca_info = { 643 .name = TYPE_MUSCA_MACHINE, 644 .parent = TYPE_MACHINE, 645 .abstract = true, 646 .instance_size = sizeof(MuscaMachineState), 647 .class_size = sizeof(MuscaMachineClass), 648 .class_init = musca_class_init, 649 }; 650 651 static const TypeInfo musca_a_info = { 652 .name = TYPE_MUSCA_A_MACHINE, 653 .parent = TYPE_MUSCA_MACHINE, 654 .class_init = musca_a_class_init, 655 }; 656 657 static const TypeInfo musca_b1_info = { 658 .name = TYPE_MUSCA_B1_MACHINE, 659 .parent = TYPE_MUSCA_MACHINE, 660 .class_init = musca_b1_class_init, 661 }; 662 663 static void musca_machine_init(void) 664 { 665 type_register_static(&musca_info); 666 type_register_static(&musca_a_info); 667 type_register_static(&musca_b1_info); 668 } 669 670 type_init(musca_machine_init); 671