1 /* 2 * SmartFusion2 SoC emulation. 3 * 4 * Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "exec/address-spaces.h" 29 #include "hw/char/serial.h" 30 #include "hw/irq.h" 31 #include "hw/arm/msf2-soc.h" 32 #include "hw/misc/unimp.h" 33 #include "sysemu/sysemu.h" 34 35 #define MSF2_TIMER_BASE 0x40004000 36 #define MSF2_SYSREG_BASE 0x40038000 37 #define MSF2_EMAC_BASE 0x40041000 38 39 #define ENVM_BASE_ADDRESS 0x60000000 40 41 #define SRAM_BASE_ADDRESS 0x20000000 42 43 #define MSF2_EMAC_IRQ 12 44 45 #define MSF2_ENVM_MAX_SIZE (512 * KiB) 46 47 /* 48 * eSRAM max size is 80k without SECDED(Single error correction and 49 * dual error detection) feature and 64k with SECDED. 50 * We do not support SECDED now. 51 */ 52 #define MSF2_ESRAM_MAX_SIZE (80 * KiB) 53 54 static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 }; 55 static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 }; 56 57 static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 }; 58 static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 }; 59 static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 }; 60 61 static void m2sxxx_soc_initfn(Object *obj) 62 { 63 MSF2State *s = MSF2_SOC(obj); 64 int i; 65 66 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); 67 68 object_initialize_child(obj, "sysreg", &s->sysreg, TYPE_MSF2_SYSREG); 69 70 object_initialize_child(obj, "timer", &s->timer, TYPE_MSS_TIMER); 71 72 for (i = 0; i < MSF2_NUM_SPIS; i++) { 73 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_MSS_SPI); 74 } 75 76 object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC); 77 } 78 79 static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) 80 { 81 MSF2State *s = MSF2_SOC(dev_soc); 82 DeviceState *dev, *armv7m; 83 SysBusDevice *busdev; 84 int i; 85 86 MemoryRegion *system_memory = get_system_memory(); 87 MemoryRegion *nvm = g_new(MemoryRegion, 1); 88 MemoryRegion *nvm_alias = g_new(MemoryRegion, 1); 89 MemoryRegion *sram = g_new(MemoryRegion, 1); 90 91 memory_region_init_rom(nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_size, 92 &error_fatal); 93 /* 94 * On power-on, the eNVM region 0x60000000 is automatically 95 * remapped to the Cortex-M3 processor executable region 96 * start address (0x0). We do not support remapping other eNVM, 97 * eSRAM and DDR regions by guest(via Sysreg) currently. 98 */ 99 memory_region_init_alias(nvm_alias, OBJECT(dev_soc), "MSF2.eNVM", nvm, 0, 100 s->envm_size); 101 102 memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm); 103 memory_region_add_subregion(system_memory, 0, nvm_alias); 104 105 memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size, 106 &error_fatal); 107 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); 108 109 armv7m = DEVICE(&s->armv7m); 110 qdev_prop_set_uint32(armv7m, "num-irq", 81); 111 qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); 112 qdev_prop_set_bit(armv7m, "enable-bitband", true); 113 object_property_set_link(OBJECT(&s->armv7m), "memory", 114 OBJECT(get_system_memory()), &error_abort); 115 if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { 116 return; 117 } 118 119 if (!s->m3clk) { 120 error_setg(errp, "Invalid m3clk value"); 121 error_append_hint(errp, "m3clk can not be zero\n"); 122 return; 123 } 124 125 system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk; 126 127 for (i = 0; i < MSF2_NUM_UARTS; i++) { 128 if (serial_hd(i)) { 129 serial_mm_init(get_system_memory(), uart_addr[i], 2, 130 qdev_get_gpio_in(armv7m, uart_irq[i]), 131 115200, serial_hd(i), DEVICE_NATIVE_ENDIAN); 132 } 133 } 134 135 dev = DEVICE(&s->timer); 136 /* APB0 clock is the timer input clock */ 137 qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div); 138 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) { 139 return; 140 } 141 busdev = SYS_BUS_DEVICE(dev); 142 sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE); 143 sysbus_connect_irq(busdev, 0, 144 qdev_get_gpio_in(armv7m, timer_irq[0])); 145 sysbus_connect_irq(busdev, 1, 146 qdev_get_gpio_in(armv7m, timer_irq[1])); 147 148 dev = DEVICE(&s->sysreg); 149 qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div); 150 qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div); 151 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp)) { 152 return; 153 } 154 busdev = SYS_BUS_DEVICE(dev); 155 sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE); 156 157 for (i = 0; i < MSF2_NUM_SPIS; i++) { 158 gchar *bus_name; 159 160 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 161 return; 162 } 163 164 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 165 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 166 qdev_get_gpio_in(armv7m, spi_irq[i])); 167 168 /* Alias controller SPI bus to the SoC itself */ 169 bus_name = g_strdup_printf("spi%d", i); 170 object_property_add_alias(OBJECT(s), bus_name, 171 OBJECT(&s->spi[i]), "spi"); 172 g_free(bus_name); 173 } 174 175 /* FIXME use qdev NIC properties instead of nd_table[] */ 176 if (nd_table[0].used) { 177 qemu_check_nic_model(&nd_table[0], TYPE_MSS_EMAC); 178 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); 179 } 180 dev = DEVICE(&s->emac); 181 object_property_set_link(OBJECT(&s->emac), "ahb-bus", 182 OBJECT(get_system_memory()), &error_abort); 183 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emac), errp)) { 184 return; 185 } 186 busdev = SYS_BUS_DEVICE(dev); 187 sysbus_mmio_map(busdev, 0, MSF2_EMAC_BASE); 188 sysbus_connect_irq(busdev, 0, 189 qdev_get_gpio_in(armv7m, MSF2_EMAC_IRQ)); 190 191 /* Below devices are not modelled yet. */ 192 create_unimplemented_device("i2c_0", 0x40002000, 0x1000); 193 create_unimplemented_device("dma", 0x40003000, 0x1000); 194 create_unimplemented_device("watchdog", 0x40005000, 0x1000); 195 create_unimplemented_device("i2c_1", 0x40012000, 0x1000); 196 create_unimplemented_device("gpio", 0x40013000, 0x1000); 197 create_unimplemented_device("hs-dma", 0x40014000, 0x1000); 198 create_unimplemented_device("can", 0x40015000, 0x1000); 199 create_unimplemented_device("rtc", 0x40017000, 0x1000); 200 create_unimplemented_device("apb_config", 0x40020000, 0x10000); 201 create_unimplemented_device("usb", 0x40043000, 0x1000); 202 } 203 204 static Property m2sxxx_soc_properties[] = { 205 /* 206 * part name specifies the type of SmartFusion2 device variant(this 207 * property is for information purpose only. 208 */ 209 DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type), 210 DEFINE_PROP_STRING("part-name", MSF2State, part_name), 211 DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE), 212 DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size, 213 MSF2_ESRAM_MAX_SIZE), 214 /* Libero GUI shows 100Mhz as default for clocks */ 215 DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000), 216 /* default divisors in Libero GUI */ 217 DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2), 218 DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2), 219 DEFINE_PROP_END_OF_LIST(), 220 }; 221 222 static void m2sxxx_soc_class_init(ObjectClass *klass, void *data) 223 { 224 DeviceClass *dc = DEVICE_CLASS(klass); 225 226 dc->realize = m2sxxx_soc_realize; 227 device_class_set_props(dc, m2sxxx_soc_properties); 228 } 229 230 static const TypeInfo m2sxxx_soc_info = { 231 .name = TYPE_MSF2_SOC, 232 .parent = TYPE_SYS_BUS_DEVICE, 233 .instance_size = sizeof(MSF2State), 234 .instance_init = m2sxxx_soc_initfn, 235 .class_init = m2sxxx_soc_class_init, 236 }; 237 238 static void m2sxxx_soc_types(void) 239 { 240 type_register_static(&m2sxxx_soc_info); 241 } 242 243 type_init(m2sxxx_soc_types) 244