1 /* 2 * SmartFusion2 SoC emulation. 3 * 4 * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "qemu-common.h" 28 #include "hw/arm/arm.h" 29 #include "exec/address-spaces.h" 30 #include "hw/char/serial.h" 31 #include "hw/boards.h" 32 #include "sysemu/block-backend.h" 33 #include "qemu/cutils.h" 34 #include "hw/arm/msf2-soc.h" 35 #include "hw/misc/unimp.h" 36 37 #define MSF2_TIMER_BASE 0x40004000 38 #define MSF2_SYSREG_BASE 0x40038000 39 40 #define ENVM_BASE_ADDRESS 0x60000000 41 42 #define SRAM_BASE_ADDRESS 0x20000000 43 44 #define MSF2_ENVM_MAX_SIZE (512 * K_BYTE) 45 46 /* 47 * eSRAM max size is 80k without SECDED(Single error correction and 48 * dual error detection) feature and 64k with SECDED. 49 * We do not support SECDED now. 50 */ 51 #define MSF2_ESRAM_MAX_SIZE (80 * K_BYTE) 52 53 static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 }; 54 static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 }; 55 56 static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 }; 57 static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 }; 58 static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 }; 59 60 static void do_sys_reset(void *opaque, int n, int level) 61 { 62 if (level) { 63 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 64 } 65 } 66 67 static void m2sxxx_soc_initfn(Object *obj) 68 { 69 MSF2State *s = MSF2_SOC(obj); 70 int i; 71 72 object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M); 73 qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default()); 74 75 object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG); 76 qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default()); 77 78 object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER); 79 qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default()); 80 81 for (i = 0; i < MSF2_NUM_SPIS; i++) { 82 object_initialize(&s->spi[i], sizeof(s->spi[i]), 83 TYPE_MSS_SPI); 84 qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); 85 } 86 } 87 88 static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) 89 { 90 MSF2State *s = MSF2_SOC(dev_soc); 91 DeviceState *dev, *armv7m; 92 SysBusDevice *busdev; 93 Error *err = NULL; 94 int i; 95 96 MemoryRegion *system_memory = get_system_memory(); 97 MemoryRegion *nvm = g_new(MemoryRegion, 1); 98 MemoryRegion *nvm_alias = g_new(MemoryRegion, 1); 99 MemoryRegion *sram = g_new(MemoryRegion, 1); 100 101 memory_region_init_rom(nvm, NULL, "MSF2.eNVM", s->envm_size, 102 &error_fatal); 103 /* 104 * On power-on, the eNVM region 0x60000000 is automatically 105 * remapped to the Cortex-M3 processor executable region 106 * start address (0x0). We do not support remapping other eNVM, 107 * eSRAM and DDR regions by guest(via Sysreg) currently. 108 */ 109 memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM", 110 nvm, 0, s->envm_size); 111 112 memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm); 113 memory_region_add_subregion(system_memory, 0, nvm_alias); 114 115 memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size, 116 &error_fatal); 117 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); 118 119 armv7m = DEVICE(&s->armv7m); 120 qdev_prop_set_uint32(armv7m, "num-irq", 81); 121 qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); 122 object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), 123 "memory", &error_abort); 124 object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); 125 if (err != NULL) { 126 error_propagate(errp, err); 127 return; 128 } 129 130 if (!s->m3clk) { 131 error_setg(errp, "Invalid m3clk value"); 132 error_append_hint(errp, "m3clk can not be zero\n"); 133 return; 134 } 135 136 qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0, 137 qemu_allocate_irq(&do_sys_reset, NULL, 0)); 138 139 system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk; 140 141 for (i = 0; i < MSF2_NUM_UARTS; i++) { 142 if (serial_hds[i]) { 143 serial_mm_init(get_system_memory(), uart_addr[i], 2, 144 qdev_get_gpio_in(armv7m, uart_irq[i]), 145 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN); 146 } 147 } 148 149 dev = DEVICE(&s->timer); 150 /* APB0 clock is the timer input clock */ 151 qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div); 152 object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); 153 if (err != NULL) { 154 error_propagate(errp, err); 155 return; 156 } 157 busdev = SYS_BUS_DEVICE(dev); 158 sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE); 159 sysbus_connect_irq(busdev, 0, 160 qdev_get_gpio_in(armv7m, timer_irq[0])); 161 sysbus_connect_irq(busdev, 1, 162 qdev_get_gpio_in(armv7m, timer_irq[1])); 163 164 dev = DEVICE(&s->sysreg); 165 qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div); 166 qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div); 167 object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err); 168 if (err != NULL) { 169 error_propagate(errp, err); 170 return; 171 } 172 busdev = SYS_BUS_DEVICE(dev); 173 sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE); 174 175 for (i = 0; i < MSF2_NUM_SPIS; i++) { 176 gchar *bus_name; 177 178 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); 179 if (err != NULL) { 180 error_propagate(errp, err); 181 return; 182 } 183 184 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 185 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 186 qdev_get_gpio_in(armv7m, spi_irq[i])); 187 188 /* Alias controller SPI bus to the SoC itself */ 189 bus_name = g_strdup_printf("spi%d", i); 190 object_property_add_alias(OBJECT(s), bus_name, 191 OBJECT(&s->spi[i]), "spi", 192 &error_abort); 193 g_free(bus_name); 194 } 195 196 /* Below devices are not modelled yet. */ 197 create_unimplemented_device("i2c_0", 0x40002000, 0x1000); 198 create_unimplemented_device("dma", 0x40003000, 0x1000); 199 create_unimplemented_device("watchdog", 0x40005000, 0x1000); 200 create_unimplemented_device("i2c_1", 0x40012000, 0x1000); 201 create_unimplemented_device("gpio", 0x40013000, 0x1000); 202 create_unimplemented_device("hs-dma", 0x40014000, 0x1000); 203 create_unimplemented_device("can", 0x40015000, 0x1000); 204 create_unimplemented_device("rtc", 0x40017000, 0x1000); 205 create_unimplemented_device("apb_config", 0x40020000, 0x10000); 206 create_unimplemented_device("emac", 0x40041000, 0x1000); 207 create_unimplemented_device("usb", 0x40043000, 0x1000); 208 } 209 210 static Property m2sxxx_soc_properties[] = { 211 /* 212 * part name specifies the type of SmartFusion2 device variant(this 213 * property is for information purpose only. 214 */ 215 DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type), 216 DEFINE_PROP_STRING("part-name", MSF2State, part_name), 217 DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE), 218 DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size, 219 MSF2_ESRAM_MAX_SIZE), 220 /* Libero GUI shows 100Mhz as default for clocks */ 221 DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000), 222 /* default divisors in Libero GUI */ 223 DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2), 224 DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2), 225 DEFINE_PROP_END_OF_LIST(), 226 }; 227 228 static void m2sxxx_soc_class_init(ObjectClass *klass, void *data) 229 { 230 DeviceClass *dc = DEVICE_CLASS(klass); 231 232 dc->realize = m2sxxx_soc_realize; 233 dc->props = m2sxxx_soc_properties; 234 } 235 236 static const TypeInfo m2sxxx_soc_info = { 237 .name = TYPE_MSF2_SOC, 238 .parent = TYPE_SYS_BUS_DEVICE, 239 .instance_size = sizeof(MSF2State), 240 .instance_init = m2sxxx_soc_initfn, 241 .class_init = m2sxxx_soc_class_init, 242 }; 243 244 static void m2sxxx_soc_types(void) 245 { 246 type_register_static(&m2sxxx_soc_info); 247 } 248 249 type_init(m2sxxx_soc_types) 250