1 /* 2 * SmartFusion2 SoC emulation. 3 * 4 * Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "exec/address-spaces.h" 29 #include "hw/char/serial.h" 30 #include "hw/irq.h" 31 #include "hw/arm/msf2-soc.h" 32 #include "hw/misc/unimp.h" 33 #include "sysemu/runstate.h" 34 #include "sysemu/sysemu.h" 35 36 #define MSF2_TIMER_BASE 0x40004000 37 #define MSF2_SYSREG_BASE 0x40038000 38 #define MSF2_EMAC_BASE 0x40041000 39 40 #define ENVM_BASE_ADDRESS 0x60000000 41 42 #define SRAM_BASE_ADDRESS 0x20000000 43 44 #define MSF2_EMAC_IRQ 12 45 46 #define MSF2_ENVM_MAX_SIZE (512 * KiB) 47 48 /* 49 * eSRAM max size is 80k without SECDED(Single error correction and 50 * dual error detection) feature and 64k with SECDED. 51 * We do not support SECDED now. 52 */ 53 #define MSF2_ESRAM_MAX_SIZE (80 * KiB) 54 55 static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 }; 56 static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 }; 57 58 static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 }; 59 static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 }; 60 static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 }; 61 62 static void do_sys_reset(void *opaque, int n, int level) 63 { 64 if (level) { 65 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 66 } 67 } 68 69 static void m2sxxx_soc_initfn(Object *obj) 70 { 71 MSF2State *s = MSF2_SOC(obj); 72 int i; 73 74 sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), 75 TYPE_ARMV7M); 76 77 sysbus_init_child_obj(obj, "sysreg", &s->sysreg, sizeof(s->sysreg), 78 TYPE_MSF2_SYSREG); 79 80 sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer), 81 TYPE_MSS_TIMER); 82 83 for (i = 0; i < MSF2_NUM_SPIS; i++) { 84 sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), 85 TYPE_MSS_SPI); 86 } 87 88 sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), 89 TYPE_MSS_EMAC); 90 if (nd_table[0].used) { 91 qemu_check_nic_model(&nd_table[0], TYPE_MSS_EMAC); 92 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); 93 } 94 } 95 96 static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) 97 { 98 MSF2State *s = MSF2_SOC(dev_soc); 99 DeviceState *dev, *armv7m; 100 SysBusDevice *busdev; 101 Error *err = NULL; 102 int i; 103 104 MemoryRegion *system_memory = get_system_memory(); 105 MemoryRegion *nvm = g_new(MemoryRegion, 1); 106 MemoryRegion *nvm_alias = g_new(MemoryRegion, 1); 107 MemoryRegion *sram = g_new(MemoryRegion, 1); 108 109 memory_region_init_rom(nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_size, 110 &error_fatal); 111 /* 112 * On power-on, the eNVM region 0x60000000 is automatically 113 * remapped to the Cortex-M3 processor executable region 114 * start address (0x0). We do not support remapping other eNVM, 115 * eSRAM and DDR regions by guest(via Sysreg) currently. 116 */ 117 memory_region_init_alias(nvm_alias, OBJECT(dev_soc), "MSF2.eNVM", nvm, 0, 118 s->envm_size); 119 120 memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm); 121 memory_region_add_subregion(system_memory, 0, nvm_alias); 122 123 memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size, 124 &error_fatal); 125 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); 126 127 armv7m = DEVICE(&s->armv7m); 128 qdev_prop_set_uint32(armv7m, "num-irq", 81); 129 qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); 130 qdev_prop_set_bit(armv7m, "enable-bitband", true); 131 object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), 132 "memory", &error_abort); 133 object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); 134 if (err != NULL) { 135 error_propagate(errp, err); 136 return; 137 } 138 139 if (!s->m3clk) { 140 error_setg(errp, "Invalid m3clk value"); 141 error_append_hint(errp, "m3clk can not be zero\n"); 142 return; 143 } 144 145 qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0, 146 qemu_allocate_irq(&do_sys_reset, NULL, 0)); 147 148 system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk; 149 150 for (i = 0; i < MSF2_NUM_UARTS; i++) { 151 if (serial_hd(i)) { 152 serial_mm_init(get_system_memory(), uart_addr[i], 2, 153 qdev_get_gpio_in(armv7m, uart_irq[i]), 154 115200, serial_hd(i), DEVICE_NATIVE_ENDIAN); 155 } 156 } 157 158 dev = DEVICE(&s->timer); 159 /* APB0 clock is the timer input clock */ 160 qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div); 161 object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); 162 if (err != NULL) { 163 error_propagate(errp, err); 164 return; 165 } 166 busdev = SYS_BUS_DEVICE(dev); 167 sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE); 168 sysbus_connect_irq(busdev, 0, 169 qdev_get_gpio_in(armv7m, timer_irq[0])); 170 sysbus_connect_irq(busdev, 1, 171 qdev_get_gpio_in(armv7m, timer_irq[1])); 172 173 dev = DEVICE(&s->sysreg); 174 qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div); 175 qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div); 176 object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err); 177 if (err != NULL) { 178 error_propagate(errp, err); 179 return; 180 } 181 busdev = SYS_BUS_DEVICE(dev); 182 sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE); 183 184 for (i = 0; i < MSF2_NUM_SPIS; i++) { 185 gchar *bus_name; 186 187 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); 188 if (err != NULL) { 189 error_propagate(errp, err); 190 return; 191 } 192 193 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 194 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 195 qdev_get_gpio_in(armv7m, spi_irq[i])); 196 197 /* Alias controller SPI bus to the SoC itself */ 198 bus_name = g_strdup_printf("spi%d", i); 199 object_property_add_alias(OBJECT(s), bus_name, 200 OBJECT(&s->spi[i]), "spi"); 201 g_free(bus_name); 202 } 203 204 dev = DEVICE(&s->emac); 205 object_property_set_link(OBJECT(&s->emac), OBJECT(get_system_memory()), 206 "ahb-bus", &error_abort); 207 object_property_set_bool(OBJECT(&s->emac), true, "realized", &err); 208 if (err != NULL) { 209 error_propagate(errp, err); 210 return; 211 } 212 busdev = SYS_BUS_DEVICE(dev); 213 sysbus_mmio_map(busdev, 0, MSF2_EMAC_BASE); 214 sysbus_connect_irq(busdev, 0, 215 qdev_get_gpio_in(armv7m, MSF2_EMAC_IRQ)); 216 217 /* Below devices are not modelled yet. */ 218 create_unimplemented_device("i2c_0", 0x40002000, 0x1000); 219 create_unimplemented_device("dma", 0x40003000, 0x1000); 220 create_unimplemented_device("watchdog", 0x40005000, 0x1000); 221 create_unimplemented_device("i2c_1", 0x40012000, 0x1000); 222 create_unimplemented_device("gpio", 0x40013000, 0x1000); 223 create_unimplemented_device("hs-dma", 0x40014000, 0x1000); 224 create_unimplemented_device("can", 0x40015000, 0x1000); 225 create_unimplemented_device("rtc", 0x40017000, 0x1000); 226 create_unimplemented_device("apb_config", 0x40020000, 0x10000); 227 create_unimplemented_device("usb", 0x40043000, 0x1000); 228 } 229 230 static Property m2sxxx_soc_properties[] = { 231 /* 232 * part name specifies the type of SmartFusion2 device variant(this 233 * property is for information purpose only. 234 */ 235 DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type), 236 DEFINE_PROP_STRING("part-name", MSF2State, part_name), 237 DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE), 238 DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size, 239 MSF2_ESRAM_MAX_SIZE), 240 /* Libero GUI shows 100Mhz as default for clocks */ 241 DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000), 242 /* default divisors in Libero GUI */ 243 DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2), 244 DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2), 245 DEFINE_PROP_END_OF_LIST(), 246 }; 247 248 static void m2sxxx_soc_class_init(ObjectClass *klass, void *data) 249 { 250 DeviceClass *dc = DEVICE_CLASS(klass); 251 252 dc->realize = m2sxxx_soc_realize; 253 device_class_set_props(dc, m2sxxx_soc_properties); 254 } 255 256 static const TypeInfo m2sxxx_soc_info = { 257 .name = TYPE_MSF2_SOC, 258 .parent = TYPE_SYS_BUS_DEVICE, 259 .instance_size = sizeof(MSF2State), 260 .instance_init = m2sxxx_soc_initfn, 261 .class_init = m2sxxx_soc_class_init, 262 }; 263 264 static void m2sxxx_soc_types(void) 265 { 266 type_register_static(&m2sxxx_soc_info); 267 } 268 269 type_init(m2sxxx_soc_types) 270