1 /* 2 * ARM V2M MPS2 board emulation. 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger 13 * FPGA but is otherwise the same as the 2). Since the CPU itself 14 * and most of the devices are in the FPGA, the details of the board 15 * as seen by the guest depend significantly on the FPGA image. 16 * We model the following FPGA images: 17 * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385 18 * "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386 19 * "mps2-an500" -- Cortex-M7 as documented in ARM Application Note AN500 20 * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511 21 * 22 * Links to the TRM for the board itself and to the various Application 23 * Notes which document the FPGA images can be found here: 24 * https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/units.h" 29 #include "qemu/cutils.h" 30 #include "qapi/error.h" 31 #include "qemu/error-report.h" 32 #include "hw/arm/boot.h" 33 #include "hw/arm/armv7m.h" 34 #include "hw/or-irq.h" 35 #include "hw/boards.h" 36 #include "exec/address-spaces.h" 37 #include "sysemu/sysemu.h" 38 #include "hw/misc/unimp.h" 39 #include "hw/char/cmsdk-apb-uart.h" 40 #include "hw/timer/cmsdk-apb-timer.h" 41 #include "hw/timer/cmsdk-apb-dualtimer.h" 42 #include "hw/misc/mps2-scc.h" 43 #include "hw/misc/mps2-fpgaio.h" 44 #include "hw/ssi/pl022.h" 45 #include "hw/i2c/arm_sbcon_i2c.h" 46 #include "hw/net/lan9118.h" 47 #include "net/net.h" 48 #include "hw/watchdog/cmsdk-apb-watchdog.h" 49 #include "qom/object.h" 50 51 typedef enum MPS2FPGAType { 52 FPGA_AN385, 53 FPGA_AN386, 54 FPGA_AN500, 55 FPGA_AN511, 56 } MPS2FPGAType; 57 58 struct MPS2MachineClass { 59 MachineClass parent; 60 MPS2FPGAType fpga_type; 61 uint32_t scc_id; 62 bool has_block_ram; 63 hwaddr ethernet_base; 64 hwaddr psram_base; 65 }; 66 typedef struct MPS2MachineClass MPS2MachineClass; 67 68 struct MPS2MachineState { 69 MachineState parent; 70 71 ARMv7MState armv7m; 72 MemoryRegion ssram1; 73 MemoryRegion ssram1_m; 74 MemoryRegion ssram23; 75 MemoryRegion ssram23_m; 76 MemoryRegion blockram; 77 MemoryRegion blockram_m1; 78 MemoryRegion blockram_m2; 79 MemoryRegion blockram_m3; 80 MemoryRegion sram; 81 /* FPGA APB subsystem */ 82 MPS2SCC scc; 83 MPS2FPGAIO fpgaio; 84 /* CMSDK APB subsystem */ 85 CMSDKAPBDualTimer dualtimer; 86 CMSDKAPBWatchdog watchdog; 87 }; 88 typedef struct MPS2MachineState MPS2MachineState; 89 90 #define TYPE_MPS2_MACHINE "mps2" 91 #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385") 92 #define TYPE_MPS2_AN386_MACHINE MACHINE_TYPE_NAME("mps2-an386") 93 #define TYPE_MPS2_AN500_MACHINE MACHINE_TYPE_NAME("mps2-an500") 94 #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511") 95 96 DECLARE_OBJ_CHECKERS(MPS2MachineState, MPS2MachineClass, 97 MPS2_MACHINE, TYPE_MPS2_MACHINE) 98 99 /* Main SYSCLK frequency in Hz */ 100 #define SYSCLK_FRQ 25000000 101 102 /* Initialize the auxiliary RAM region @mr and map it into 103 * the memory map at @base. 104 */ 105 static void make_ram(MemoryRegion *mr, const char *name, 106 hwaddr base, hwaddr size) 107 { 108 memory_region_init_ram(mr, NULL, name, size, &error_fatal); 109 memory_region_add_subregion(get_system_memory(), base, mr); 110 } 111 112 /* Create an alias of an entire original MemoryRegion @orig 113 * located at @base in the memory map. 114 */ 115 static void make_ram_alias(MemoryRegion *mr, const char *name, 116 MemoryRegion *orig, hwaddr base) 117 { 118 memory_region_init_alias(mr, NULL, name, orig, 0, 119 memory_region_size(orig)); 120 memory_region_add_subregion(get_system_memory(), base, mr); 121 } 122 123 static void mps2_common_init(MachineState *machine) 124 { 125 MPS2MachineState *mms = MPS2_MACHINE(machine); 126 MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine); 127 MemoryRegion *system_memory = get_system_memory(); 128 MachineClass *mc = MACHINE_GET_CLASS(machine); 129 DeviceState *armv7m, *sccdev; 130 int i; 131 132 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { 133 error_report("This board can only be used with CPU %s", 134 mc->default_cpu_type); 135 exit(1); 136 } 137 138 if (machine->ram_size != mc->default_ram_size) { 139 char *sz = size_to_str(mc->default_ram_size); 140 error_report("Invalid RAM size, should be %s", sz); 141 g_free(sz); 142 exit(EXIT_FAILURE); 143 } 144 145 /* The FPGA images have an odd combination of different RAMs, 146 * because in hardware they are different implementations and 147 * connected to different buses, giving varying performance/size 148 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily 149 * call the 16MB our "system memory", as it's the largest lump. 150 * 151 * AN385/AN386/AN511: 152 * 0x21000000 .. 0x21ffffff : PSRAM (16MB) 153 * AN385/AN386/AN500: 154 * 0x00000000 .. 0x003fffff : ZBT SSRAM1 155 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1 156 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3 157 * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3 158 * AN385/AN386 only: 159 * 0x01000000 .. 0x01003fff : block RAM (16K) 160 * 0x01004000 .. 0x01007fff : mirror of above 161 * 0x01008000 .. 0x0100bfff : mirror of above 162 * 0x0100c000 .. 0x0100ffff : mirror of above 163 * AN511 only: 164 * 0x00000000 .. 0x0003ffff : FPGA block RAM 165 * 0x00400000 .. 0x007fffff : ZBT SSRAM1 166 * 0x20000000 .. 0x2001ffff : SRAM 167 * 0x20400000 .. 0x207fffff : ZBT SSRAM 2&3 168 * AN500 only: 169 * 0x60000000 .. 0x60ffffff : PSRAM (16MB) 170 * 171 * The AN385/AN386 has a feature where the lowest 16K can be mapped 172 * either to the bottom of the ZBT SSRAM1 or to the block RAM. 173 * This is of no use for QEMU so we don't implement it (as if 174 * zbt_boot_ctrl is always zero). 175 */ 176 memory_region_add_subregion(system_memory, mmc->psram_base, machine->ram); 177 178 if (mmc->has_block_ram) { 179 make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000); 180 make_ram_alias(&mms->blockram_m1, "mps.blockram_m1", 181 &mms->blockram, 0x01004000); 182 make_ram_alias(&mms->blockram_m2, "mps.blockram_m2", 183 &mms->blockram, 0x01008000); 184 make_ram_alias(&mms->blockram_m3, "mps.blockram_m3", 185 &mms->blockram, 0x0100c000); 186 } 187 188 switch (mmc->fpga_type) { 189 case FPGA_AN385: 190 case FPGA_AN386: 191 case FPGA_AN500: 192 make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000); 193 make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000); 194 make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000); 195 make_ram_alias(&mms->ssram23_m, "mps.ssram23_m", 196 &mms->ssram23, 0x20400000); 197 break; 198 case FPGA_AN511: 199 make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000); 200 make_ram(&mms->ssram1, "mps.ssram1", 0x00400000, 0x00800000); 201 make_ram(&mms->sram, "mps.sram", 0x20000000, 0x20000); 202 make_ram(&mms->ssram23, "mps.ssram23", 0x20400000, 0x400000); 203 break; 204 default: 205 g_assert_not_reached(); 206 } 207 208 object_initialize_child(OBJECT(mms), "armv7m", &mms->armv7m, TYPE_ARMV7M); 209 armv7m = DEVICE(&mms->armv7m); 210 switch (mmc->fpga_type) { 211 case FPGA_AN385: 212 case FPGA_AN386: 213 case FPGA_AN500: 214 qdev_prop_set_uint32(armv7m, "num-irq", 32); 215 break; 216 case FPGA_AN511: 217 qdev_prop_set_uint32(armv7m, "num-irq", 64); 218 break; 219 default: 220 g_assert_not_reached(); 221 } 222 qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type); 223 qdev_prop_set_bit(armv7m, "enable-bitband", true); 224 object_property_set_link(OBJECT(&mms->armv7m), "memory", 225 OBJECT(system_memory), &error_abort); 226 sysbus_realize(SYS_BUS_DEVICE(&mms->armv7m), &error_fatal); 227 228 create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000); 229 create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000); 230 create_unimplemented_device("Block RAM", 0x01000000, 0x00010000); 231 create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000); 232 create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000); 233 create_unimplemented_device("PSRAM", 0x21000000, 0x01000000); 234 /* These three ranges all cover multiple devices; we may implement 235 * some of them below (in which case the real device takes precedence 236 * over the unimplemented-region mapping). 237 */ 238 create_unimplemented_device("CMSDK APB peripheral region @0x40000000", 239 0x40000000, 0x00010000); 240 create_unimplemented_device("CMSDK AHB peripheral region @0x40010000", 241 0x40010000, 0x00010000); 242 create_unimplemented_device("Extra peripheral region @0x40020000", 243 0x40020000, 0x00010000); 244 245 create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000); 246 create_unimplemented_device("VGA", 0x41000000, 0x0200000); 247 248 switch (mmc->fpga_type) { 249 case FPGA_AN385: 250 case FPGA_AN386: 251 case FPGA_AN500: 252 { 253 /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together. 254 * Overflow for UARTs 4 and 5 doesn't trigger any interrupt. 255 */ 256 Object *orgate; 257 DeviceState *orgate_dev; 258 259 orgate = object_new(TYPE_OR_IRQ); 260 object_property_set_int(orgate, "num-lines", 6, &error_fatal); 261 qdev_realize(DEVICE(orgate), NULL, &error_fatal); 262 orgate_dev = DEVICE(orgate); 263 qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12)); 264 265 for (i = 0; i < 5; i++) { 266 static const hwaddr uartbase[] = {0x40004000, 0x40005000, 267 0x40006000, 0x40007000, 268 0x40009000}; 269 /* RX irq number; TX irq is always one greater */ 270 static const int uartirq[] = {0, 2, 4, 18, 20}; 271 qemu_irq txovrint = NULL, rxovrint = NULL; 272 273 if (i < 3) { 274 txovrint = qdev_get_gpio_in(orgate_dev, i * 2); 275 rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1); 276 } 277 278 cmsdk_apb_uart_create(uartbase[i], 279 qdev_get_gpio_in(armv7m, uartirq[i] + 1), 280 qdev_get_gpio_in(armv7m, uartirq[i]), 281 txovrint, rxovrint, 282 NULL, 283 serial_hd(i), SYSCLK_FRQ); 284 } 285 break; 286 } 287 case FPGA_AN511: 288 { 289 /* The overflow IRQs for all UARTs are ORed together. 290 * Tx and Rx IRQs for each UART are ORed together. 291 */ 292 Object *orgate; 293 DeviceState *orgate_dev; 294 295 orgate = object_new(TYPE_OR_IRQ); 296 object_property_set_int(orgate, "num-lines", 10, &error_fatal); 297 qdev_realize(DEVICE(orgate), NULL, &error_fatal); 298 orgate_dev = DEVICE(orgate); 299 qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12)); 300 301 for (i = 0; i < 5; i++) { 302 /* system irq numbers for the combined tx/rx for each UART */ 303 static const int uart_txrx_irqno[] = {0, 2, 45, 46, 56}; 304 static const hwaddr uartbase[] = {0x40004000, 0x40005000, 305 0x4002c000, 0x4002d000, 306 0x4002e000}; 307 Object *txrx_orgate; 308 DeviceState *txrx_orgate_dev; 309 310 txrx_orgate = object_new(TYPE_OR_IRQ); 311 object_property_set_int(txrx_orgate, "num-lines", 2, &error_fatal); 312 qdev_realize(DEVICE(txrx_orgate), NULL, &error_fatal); 313 txrx_orgate_dev = DEVICE(txrx_orgate); 314 qdev_connect_gpio_out(txrx_orgate_dev, 0, 315 qdev_get_gpio_in(armv7m, uart_txrx_irqno[i])); 316 cmsdk_apb_uart_create(uartbase[i], 317 qdev_get_gpio_in(txrx_orgate_dev, 0), 318 qdev_get_gpio_in(txrx_orgate_dev, 1), 319 qdev_get_gpio_in(orgate_dev, i * 2), 320 qdev_get_gpio_in(orgate_dev, i * 2 + 1), 321 NULL, 322 serial_hd(i), SYSCLK_FRQ); 323 } 324 break; 325 } 326 default: 327 g_assert_not_reached(); 328 } 329 for (i = 0; i < 4; i++) { 330 static const hwaddr gpiobase[] = {0x40010000, 0x40011000, 331 0x40012000, 0x40013000}; 332 create_unimplemented_device("cmsdk-ahb-gpio", gpiobase[i], 0x1000); 333 } 334 335 /* CMSDK APB subsystem */ 336 cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ); 337 cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ); 338 object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, 339 TYPE_CMSDK_APB_DUALTIMER); 340 qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ); 341 sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal); 342 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, 343 qdev_get_gpio_in(armv7m, 10)); 344 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000); 345 object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog, 346 TYPE_CMSDK_APB_WATCHDOG); 347 qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ); 348 sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal); 349 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0, 350 qdev_get_gpio_in_named(armv7m, "NMI", 0)); 351 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0x40008000); 352 353 /* FPGA APB subsystem */ 354 object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC); 355 sccdev = DEVICE(&mms->scc); 356 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); 357 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); 358 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); 359 sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal); 360 sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000); 361 object_initialize_child(OBJECT(mms), "fpgaio", 362 &mms->fpgaio, TYPE_MPS2_FPGAIO); 363 qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", 25000000); 364 sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal); 365 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0x40028000); 366 sysbus_create_simple(TYPE_PL022, 0x40025000, /* External ADC */ 367 qdev_get_gpio_in(armv7m, 22)); 368 for (i = 0; i < 2; i++) { 369 static const int spi_irqno[] = {11, 24}; 370 static const hwaddr spibase[] = {0x40020000, /* APB */ 371 0x40021000, /* LCD */ 372 0x40026000, /* Shield0 */ 373 0x40027000}; /* Shield1 */ 374 DeviceState *orgate_dev; 375 Object *orgate; 376 int j; 377 378 orgate = object_new(TYPE_OR_IRQ); 379 object_property_set_int(orgate, "num-lines", 2, &error_fatal); 380 orgate_dev = DEVICE(orgate); 381 qdev_realize(orgate_dev, NULL, &error_fatal); 382 qdev_connect_gpio_out(orgate_dev, 0, 383 qdev_get_gpio_in(armv7m, spi_irqno[i])); 384 for (j = 0; j < 2; j++) { 385 sysbus_create_simple(TYPE_PL022, spibase[2 * i + j], 386 qdev_get_gpio_in(orgate_dev, j)); 387 } 388 } 389 for (i = 0; i < 4; i++) { 390 static const hwaddr i2cbase[] = {0x40022000, /* Touch */ 391 0x40023000, /* Audio */ 392 0x40029000, /* Shield0 */ 393 0x4002a000}; /* Shield1 */ 394 sysbus_create_simple(TYPE_ARM_SBCON_I2C, i2cbase[i], NULL); 395 } 396 create_unimplemented_device("i2s", 0x40024000, 0x400); 397 398 /* In hardware this is a LAN9220; the LAN9118 is software compatible 399 * except that it doesn't support the checksum-offload feature. 400 */ 401 lan9118_init(&nd_table[0], mmc->ethernet_base, 402 qdev_get_gpio_in(armv7m, 403 mmc->fpga_type == FPGA_AN511 ? 47 : 13)); 404 405 system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ; 406 407 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 408 0x400000); 409 } 410 411 static void mps2_class_init(ObjectClass *oc, void *data) 412 { 413 MachineClass *mc = MACHINE_CLASS(oc); 414 415 mc->init = mps2_common_init; 416 mc->max_cpus = 1; 417 mc->default_ram_size = 16 * MiB; 418 mc->default_ram_id = "mps.ram"; 419 } 420 421 static void mps2_an385_class_init(ObjectClass *oc, void *data) 422 { 423 MachineClass *mc = MACHINE_CLASS(oc); 424 MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc); 425 426 mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3"; 427 mmc->fpga_type = FPGA_AN385; 428 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 429 mmc->scc_id = 0x41043850; 430 mmc->psram_base = 0x21000000; 431 mmc->ethernet_base = 0x40200000; 432 mmc->has_block_ram = true; 433 } 434 435 static void mps2_an386_class_init(ObjectClass *oc, void *data) 436 { 437 MachineClass *mc = MACHINE_CLASS(oc); 438 MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc); 439 440 mc->desc = "ARM MPS2 with AN386 FPGA image for Cortex-M4"; 441 mmc->fpga_type = FPGA_AN386; 442 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); 443 mmc->scc_id = 0x41043860; 444 mmc->psram_base = 0x21000000; 445 mmc->ethernet_base = 0x40200000; 446 mmc->has_block_ram = true; 447 } 448 449 static void mps2_an500_class_init(ObjectClass *oc, void *data) 450 { 451 MachineClass *mc = MACHINE_CLASS(oc); 452 MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc); 453 454 mc->desc = "ARM MPS2 with AN500 FPGA image for Cortex-M7"; 455 mmc->fpga_type = FPGA_AN500; 456 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m7"); 457 mmc->scc_id = 0x41045000; 458 mmc->psram_base = 0x60000000; 459 mmc->ethernet_base = 0xa0000000; 460 mmc->has_block_ram = false; 461 } 462 463 static void mps2_an511_class_init(ObjectClass *oc, void *data) 464 { 465 MachineClass *mc = MACHINE_CLASS(oc); 466 MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc); 467 468 mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3"; 469 mmc->fpga_type = FPGA_AN511; 470 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 471 mmc->scc_id = 0x41045110; 472 mmc->psram_base = 0x21000000; 473 mmc->ethernet_base = 0x40200000; 474 mmc->has_block_ram = false; 475 } 476 477 static const TypeInfo mps2_info = { 478 .name = TYPE_MPS2_MACHINE, 479 .parent = TYPE_MACHINE, 480 .abstract = true, 481 .instance_size = sizeof(MPS2MachineState), 482 .class_size = sizeof(MPS2MachineClass), 483 .class_init = mps2_class_init, 484 }; 485 486 static const TypeInfo mps2_an385_info = { 487 .name = TYPE_MPS2_AN385_MACHINE, 488 .parent = TYPE_MPS2_MACHINE, 489 .class_init = mps2_an385_class_init, 490 }; 491 492 static const TypeInfo mps2_an386_info = { 493 .name = TYPE_MPS2_AN386_MACHINE, 494 .parent = TYPE_MPS2_MACHINE, 495 .class_init = mps2_an386_class_init, 496 }; 497 498 static const TypeInfo mps2_an500_info = { 499 .name = TYPE_MPS2_AN500_MACHINE, 500 .parent = TYPE_MPS2_MACHINE, 501 .class_init = mps2_an500_class_init, 502 }; 503 504 static const TypeInfo mps2_an511_info = { 505 .name = TYPE_MPS2_AN511_MACHINE, 506 .parent = TYPE_MPS2_MACHINE, 507 .class_init = mps2_an511_class_init, 508 }; 509 510 static void mps2_machine_init(void) 511 { 512 type_register_static(&mps2_info); 513 type_register_static(&mps2_an385_info); 514 type_register_static(&mps2_an386_info); 515 type_register_static(&mps2_an500_info); 516 type_register_static(&mps2_an511_info); 517 } 518 519 type_init(mps2_machine_init); 520