1 /* 2 * ARM V2M MPS2 board emulation. 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger 13 * FPGA but is otherwise the same as the 2). Since the CPU itself 14 * and most of the devices are in the FPGA, the details of the board 15 * as seen by the guest depend significantly on the FPGA image. 16 * We model the following FPGA images: 17 * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385 18 * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511 19 * 20 * Links to the TRM for the board itself and to the various Application 21 * Notes which document the FPGA images can be found here: 22 * https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "hw/arm/arm.h" 29 #include "hw/arm/armv7m.h" 30 #include "hw/or-irq.h" 31 #include "hw/boards.h" 32 #include "exec/address-spaces.h" 33 #include "sysemu/sysemu.h" 34 #include "hw/misc/unimp.h" 35 #include "hw/char/cmsdk-apb-uart.h" 36 37 typedef enum MPS2FPGAType { 38 FPGA_AN385, 39 FPGA_AN511, 40 } MPS2FPGAType; 41 42 typedef struct { 43 MachineClass parent; 44 MPS2FPGAType fpga_type; 45 const char *cpu_model; 46 } MPS2MachineClass; 47 48 typedef struct { 49 MachineState parent; 50 51 ARMv7MState armv7m; 52 MemoryRegion psram; 53 MemoryRegion ssram1; 54 MemoryRegion ssram1_m; 55 MemoryRegion ssram23; 56 MemoryRegion ssram23_m; 57 MemoryRegion blockram; 58 MemoryRegion blockram_m1; 59 MemoryRegion blockram_m2; 60 MemoryRegion blockram_m3; 61 MemoryRegion sram; 62 } MPS2MachineState; 63 64 #define TYPE_MPS2_MACHINE "mps2" 65 #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385") 66 #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511") 67 68 #define MPS2_MACHINE(obj) \ 69 OBJECT_CHECK(MPS2MachineState, obj, TYPE_MPS2_MACHINE) 70 #define MPS2_MACHINE_GET_CLASS(obj) \ 71 OBJECT_GET_CLASS(MPS2MachineClass, obj, TYPE_MPS2_MACHINE) 72 #define MPS2_MACHINE_CLASS(klass) \ 73 OBJECT_CLASS_CHECK(MPS2MachineClass, klass, TYPE_MPS2_MACHINE) 74 75 /* Main SYSCLK frequency in Hz */ 76 #define SYSCLK_FRQ 25000000 77 78 /* Initialize the auxiliary RAM region @mr and map it into 79 * the memory map at @base. 80 */ 81 static void make_ram(MemoryRegion *mr, const char *name, 82 hwaddr base, hwaddr size) 83 { 84 memory_region_init_ram(mr, NULL, name, size, &error_fatal); 85 memory_region_add_subregion(get_system_memory(), base, mr); 86 } 87 88 /* Create an alias of an entire original MemoryRegion @orig 89 * located at @base in the memory map. 90 */ 91 static void make_ram_alias(MemoryRegion *mr, const char *name, 92 MemoryRegion *orig, hwaddr base) 93 { 94 memory_region_init_alias(mr, NULL, name, orig, 0, 95 memory_region_size(orig)); 96 memory_region_add_subregion(get_system_memory(), base, mr); 97 } 98 99 static void mps2_common_init(MachineState *machine) 100 { 101 MPS2MachineState *mms = MPS2_MACHINE(machine); 102 MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine); 103 MemoryRegion *system_memory = get_system_memory(); 104 DeviceState *armv7m; 105 106 if (!machine->cpu_model) { 107 machine->cpu_model = mmc->cpu_model; 108 } 109 110 if (strcmp(machine->cpu_model, mmc->cpu_model) != 0) { 111 error_report("This board can only be used with CPU %s", mmc->cpu_model); 112 exit(1); 113 } 114 115 /* The FPGA images have an odd combination of different RAMs, 116 * because in hardware they are different implementations and 117 * connected to different buses, giving varying performance/size 118 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily 119 * call the 16MB our "system memory", as it's the largest lump. 120 * 121 * Common to both boards: 122 * 0x21000000..0x21ffffff : PSRAM (16MB) 123 * AN385 only: 124 * 0x00000000 .. 0x003fffff : ZBT SSRAM1 125 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1 126 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3 127 * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3 128 * 0x01000000 .. 0x01003fff : block RAM (16K) 129 * 0x01004000 .. 0x01007fff : mirror of above 130 * 0x01008000 .. 0x0100bfff : mirror of above 131 * 0x0100c000 .. 0x0100ffff : mirror of above 132 * AN511 only: 133 * 0x00000000 .. 0x0003ffff : FPGA block RAM 134 * 0x00400000 .. 0x007fffff : ZBT SSRAM1 135 * 0x20000000 .. 0x2001ffff : SRAM 136 * 0x20400000 .. 0x207fffff : ZBT SSRAM 2&3 137 * 138 * The AN385 has a feature where the lowest 16K can be mapped 139 * either to the bottom of the ZBT SSRAM1 or to the block RAM. 140 * This is of no use for QEMU so we don't implement it (as if 141 * zbt_boot_ctrl is always zero). 142 */ 143 memory_region_allocate_system_memory(&mms->psram, 144 NULL, "mps.ram", 0x1000000); 145 memory_region_add_subregion(system_memory, 0x21000000, &mms->psram); 146 147 switch (mmc->fpga_type) { 148 case FPGA_AN385: 149 make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000); 150 make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000); 151 make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000); 152 make_ram_alias(&mms->ssram23_m, "mps.ssram23_m", 153 &mms->ssram23, 0x20400000); 154 make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000); 155 make_ram_alias(&mms->blockram_m1, "mps.blockram_m1", 156 &mms->blockram, 0x01004000); 157 make_ram_alias(&mms->blockram_m2, "mps.blockram_m2", 158 &mms->blockram, 0x01008000); 159 make_ram_alias(&mms->blockram_m3, "mps.blockram_m3", 160 &mms->blockram, 0x0100c000); 161 break; 162 case FPGA_AN511: 163 make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000); 164 make_ram(&mms->ssram1, "mps.ssram1", 0x00400000, 0x00800000); 165 make_ram(&mms->sram, "mps.sram", 0x20000000, 0x20000); 166 make_ram(&mms->ssram23, "mps.ssram23", 0x20400000, 0x400000); 167 break; 168 default: 169 g_assert_not_reached(); 170 } 171 172 object_initialize(&mms->armv7m, sizeof(mms->armv7m), TYPE_ARMV7M); 173 armv7m = DEVICE(&mms->armv7m); 174 qdev_set_parent_bus(armv7m, sysbus_get_default()); 175 switch (mmc->fpga_type) { 176 case FPGA_AN385: 177 qdev_prop_set_uint32(armv7m, "num-irq", 32); 178 break; 179 case FPGA_AN511: 180 qdev_prop_set_uint32(armv7m, "num-irq", 64); 181 break; 182 default: 183 g_assert_not_reached(); 184 } 185 qdev_prop_set_string(armv7m, "cpu-model", machine->cpu_model); 186 object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory), 187 "memory", &error_abort); 188 object_property_set_bool(OBJECT(&mms->armv7m), true, "realized", 189 &error_fatal); 190 191 create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000); 192 create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000); 193 create_unimplemented_device("Block RAM", 0x01000000, 0x00010000); 194 create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000); 195 create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000); 196 create_unimplemented_device("PSRAM", 0x21000000, 0x01000000); 197 /* These three ranges all cover multiple devices; we may implement 198 * some of them below (in which case the real device takes precedence 199 * over the unimplemented-region mapping). 200 */ 201 create_unimplemented_device("CMSDK APB peripheral region @0x40000000", 202 0x40000000, 0x00010000); 203 create_unimplemented_device("CMSDK peripheral region @0x40010000", 204 0x40010000, 0x00010000); 205 create_unimplemented_device("Extra peripheral region @0x40020000", 206 0x40020000, 0x00010000); 207 create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000); 208 create_unimplemented_device("Ethernet", 0x40200000, 0x00100000); 209 create_unimplemented_device("VGA", 0x41000000, 0x0200000); 210 211 switch (mmc->fpga_type) { 212 case FPGA_AN385: 213 { 214 /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together. 215 * Overflow for UARTs 4 and 5 doesn't trigger any interrupt. 216 */ 217 Object *orgate; 218 DeviceState *orgate_dev; 219 int i; 220 221 orgate = object_new(TYPE_OR_IRQ); 222 object_property_set_int(orgate, 6, "num-lines", &error_fatal); 223 object_property_set_bool(orgate, true, "realized", &error_fatal); 224 orgate_dev = DEVICE(orgate); 225 qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12)); 226 227 for (i = 0; i < 5; i++) { 228 static const hwaddr uartbase[] = {0x40004000, 0x40005000, 229 0x40006000, 0x40007000, 230 0x40009000}; 231 Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL; 232 /* RX irq number; TX irq is always one greater */ 233 static const int uartirq[] = {0, 2, 4, 18, 20}; 234 qemu_irq txovrint = NULL, rxovrint = NULL; 235 236 if (i < 3) { 237 txovrint = qdev_get_gpio_in(orgate_dev, i * 2); 238 rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1); 239 } 240 241 cmsdk_apb_uart_create(uartbase[i], 242 qdev_get_gpio_in(armv7m, uartirq[i] + 1), 243 qdev_get_gpio_in(armv7m, uartirq[i]), 244 txovrint, rxovrint, 245 NULL, 246 uartchr, SYSCLK_FRQ); 247 } 248 break; 249 } 250 case FPGA_AN511: 251 { 252 /* The overflow IRQs for all UARTs are ORed together. 253 * Tx and Rx IRQs for each UART are ORed together. 254 */ 255 Object *orgate; 256 DeviceState *orgate_dev; 257 int i; 258 259 orgate = object_new(TYPE_OR_IRQ); 260 object_property_set_int(orgate, 10, "num-lines", &error_fatal); 261 object_property_set_bool(orgate, true, "realized", &error_fatal); 262 orgate_dev = DEVICE(orgate); 263 qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12)); 264 265 for (i = 0; i < 5; i++) { 266 /* system irq numbers for the combined tx/rx for each UART */ 267 static const int uart_txrx_irqno[] = {0, 2, 45, 46, 56}; 268 static const hwaddr uartbase[] = {0x40004000, 0x40005000, 269 0x4002c000, 0x4002d000, 270 0x4002e000}; 271 Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL; 272 Object *txrx_orgate; 273 DeviceState *txrx_orgate_dev; 274 275 txrx_orgate = object_new(TYPE_OR_IRQ); 276 object_property_set_int(txrx_orgate, 2, "num-lines", &error_fatal); 277 object_property_set_bool(txrx_orgate, true, "realized", 278 &error_fatal); 279 txrx_orgate_dev = DEVICE(txrx_orgate); 280 qdev_connect_gpio_out(txrx_orgate_dev, 0, 281 qdev_get_gpio_in(armv7m, uart_txrx_irqno[i])); 282 cmsdk_apb_uart_create(uartbase[i], 283 qdev_get_gpio_in(txrx_orgate_dev, 0), 284 qdev_get_gpio_in(txrx_orgate_dev, 1), 285 qdev_get_gpio_in(orgate_dev, 0), 286 qdev_get_gpio_in(orgate_dev, 1), 287 NULL, 288 uartchr, SYSCLK_FRQ); 289 } 290 break; 291 } 292 default: 293 g_assert_not_reached(); 294 } 295 296 system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ; 297 298 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 299 0x400000); 300 } 301 302 static void mps2_class_init(ObjectClass *oc, void *data) 303 { 304 MachineClass *mc = MACHINE_CLASS(oc); 305 306 mc->init = mps2_common_init; 307 mc->max_cpus = 1; 308 } 309 310 static void mps2_an385_class_init(ObjectClass *oc, void *data) 311 { 312 MachineClass *mc = MACHINE_CLASS(oc); 313 MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc); 314 315 mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3"; 316 mmc->fpga_type = FPGA_AN385; 317 mmc->cpu_model = "cortex-m3"; 318 } 319 320 static void mps2_an511_class_init(ObjectClass *oc, void *data) 321 { 322 MachineClass *mc = MACHINE_CLASS(oc); 323 MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc); 324 325 mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3"; 326 mmc->fpga_type = FPGA_AN511; 327 mmc->cpu_model = "cortex-m3"; 328 } 329 330 static const TypeInfo mps2_info = { 331 .name = TYPE_MPS2_MACHINE, 332 .parent = TYPE_MACHINE, 333 .abstract = true, 334 .instance_size = sizeof(MPS2MachineState), 335 .class_size = sizeof(MPS2MachineClass), 336 .class_init = mps2_class_init, 337 }; 338 339 static const TypeInfo mps2_an385_info = { 340 .name = TYPE_MPS2_AN385_MACHINE, 341 .parent = TYPE_MPS2_MACHINE, 342 .class_init = mps2_an385_class_init, 343 }; 344 345 static const TypeInfo mps2_an511_info = { 346 .name = TYPE_MPS2_AN511_MACHINE, 347 .parent = TYPE_MPS2_MACHINE, 348 .class_init = mps2_an511_class_init, 349 }; 350 351 static void mps2_machine_init(void) 352 { 353 type_register_static(&mps2_info); 354 type_register_static(&mps2_an385_info); 355 type_register_static(&mps2_an511_info); 356 } 357 358 type_init(mps2_machine_init); 359