1 /* 2 * ARM V2M MPS2 board emulation, trustzone aware FPGA images 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger 13 * FPGA but is otherwise the same as the 2). Since the CPU itself 14 * and most of the devices are in the FPGA, the details of the board 15 * as seen by the guest depend significantly on the FPGA image. 16 * This source file covers the following FPGA images, for TrustZone cores: 17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 18 * 19 * Links to the TRM for the board itself and to the various Application 20 * Notes which document the FPGA images can be found here: 21 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 22 * 23 * Board TRM: 24 * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf 25 * Application Note AN505: 26 * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html 27 * 28 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide 29 * (ARM ECM0601256) for the details of some of the device layout: 30 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html 31 */ 32 33 #include "qemu/osdep.h" 34 #include "qapi/error.h" 35 #include "qemu/error-report.h" 36 #include "hw/arm/arm.h" 37 #include "hw/arm/armv7m.h" 38 #include "hw/or-irq.h" 39 #include "hw/boards.h" 40 #include "exec/address-spaces.h" 41 #include "sysemu/sysemu.h" 42 #include "hw/misc/unimp.h" 43 #include "hw/char/cmsdk-apb-uart.h" 44 #include "hw/timer/cmsdk-apb-timer.h" 45 #include "hw/misc/mps2-scc.h" 46 #include "hw/misc/mps2-fpgaio.h" 47 #include "hw/arm/iotkit.h" 48 #include "hw/devices.h" 49 #include "net/net.h" 50 #include "hw/core/split-irq.h" 51 52 typedef enum MPS2TZFPGAType { 53 FPGA_AN505, 54 } MPS2TZFPGAType; 55 56 typedef struct { 57 MachineClass parent; 58 MPS2TZFPGAType fpga_type; 59 uint32_t scc_id; 60 } MPS2TZMachineClass; 61 62 typedef struct { 63 MachineState parent; 64 65 IoTKit iotkit; 66 MemoryRegion psram; 67 MemoryRegion ssram1; 68 MemoryRegion ssram1_m; 69 MemoryRegion ssram23; 70 MPS2SCC scc; 71 MPS2FPGAIO fpgaio; 72 TZPPC ppc[5]; 73 UnimplementedDeviceState ssram_mpc[3]; 74 UnimplementedDeviceState spi[5]; 75 UnimplementedDeviceState i2c[4]; 76 UnimplementedDeviceState i2s_audio; 77 UnimplementedDeviceState gpio[5]; 78 UnimplementedDeviceState dma[4]; 79 UnimplementedDeviceState gfx; 80 CMSDKAPBUART uart[5]; 81 SplitIRQ sec_resp_splitter; 82 qemu_or_irq uart_irq_orgate; 83 } MPS2TZMachineState; 84 85 #define TYPE_MPS2TZ_MACHINE "mps2tz" 86 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") 87 88 #define MPS2TZ_MACHINE(obj) \ 89 OBJECT_CHECK(MPS2TZMachineState, obj, TYPE_MPS2TZ_MACHINE) 90 #define MPS2TZ_MACHINE_GET_CLASS(obj) \ 91 OBJECT_GET_CLASS(MPS2TZMachineClass, obj, TYPE_MPS2TZ_MACHINE) 92 #define MPS2TZ_MACHINE_CLASS(klass) \ 93 OBJECT_CLASS_CHECK(MPS2TZMachineClass, klass, TYPE_MPS2TZ_MACHINE) 94 95 /* Main SYSCLK frequency in Hz */ 96 #define SYSCLK_FRQ 20000000 97 98 /* Initialize the auxiliary RAM region @mr and map it into 99 * the memory map at @base. 100 */ 101 static void make_ram(MemoryRegion *mr, const char *name, 102 hwaddr base, hwaddr size) 103 { 104 memory_region_init_ram(mr, NULL, name, size, &error_fatal); 105 memory_region_add_subregion(get_system_memory(), base, mr); 106 } 107 108 /* Create an alias of an entire original MemoryRegion @orig 109 * located at @base in the memory map. 110 */ 111 static void make_ram_alias(MemoryRegion *mr, const char *name, 112 MemoryRegion *orig, hwaddr base) 113 { 114 memory_region_init_alias(mr, NULL, name, orig, 0, 115 memory_region_size(orig)); 116 memory_region_add_subregion(get_system_memory(), base, mr); 117 } 118 119 static void init_sysbus_child(Object *parent, const char *childname, 120 void *child, size_t childsize, 121 const char *childtype) 122 { 123 object_initialize(child, childsize, childtype); 124 object_property_add_child(parent, childname, OBJECT(child), &error_abort); 125 qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); 126 127 } 128 129 /* Most of the devices in the AN505 FPGA image sit behind 130 * Peripheral Protection Controllers. These data structures 131 * define the layout of which devices sit behind which PPCs. 132 * The devfn for each port is a function which creates, configures 133 * and initializes the device, returning the MemoryRegion which 134 * needs to be plugged into the downstream end of the PPC port. 135 */ 136 typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, 137 const char *name, hwaddr size); 138 139 typedef struct PPCPortInfo { 140 const char *name; 141 MakeDevFn *devfn; 142 void *opaque; 143 hwaddr addr; 144 hwaddr size; 145 } PPCPortInfo; 146 147 typedef struct PPCInfo { 148 const char *name; 149 PPCPortInfo ports[TZ_NUM_PORTS]; 150 } PPCInfo; 151 152 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, 153 void *opaque, 154 const char *name, hwaddr size) 155 { 156 /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, 157 * and return a pointer to its MemoryRegion. 158 */ 159 UnimplementedDeviceState *uds = opaque; 160 161 init_sysbus_child(OBJECT(mms), name, uds, 162 sizeof(UnimplementedDeviceState), 163 TYPE_UNIMPLEMENTED_DEVICE); 164 qdev_prop_set_string(DEVICE(uds), "name", name); 165 qdev_prop_set_uint64(DEVICE(uds), "size", size); 166 object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal); 167 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); 168 } 169 170 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, 171 const char *name, hwaddr size) 172 { 173 CMSDKAPBUART *uart = opaque; 174 int i = uart - &mms->uart[0]; 175 Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL; 176 int rxirqno = i * 2; 177 int txirqno = i * 2 + 1; 178 int combirqno = i + 10; 179 SysBusDevice *s; 180 DeviceState *iotkitdev = DEVICE(&mms->iotkit); 181 DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); 182 183 init_sysbus_child(OBJECT(mms), name, uart, 184 sizeof(mms->uart[0]), TYPE_CMSDK_APB_UART); 185 qdev_prop_set_chr(DEVICE(uart), "chardev", uartchr); 186 qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); 187 object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal); 188 s = SYS_BUS_DEVICE(uart); 189 sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, 190 "EXP_IRQ", txirqno)); 191 sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev, 192 "EXP_IRQ", rxirqno)); 193 sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); 194 sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); 195 sysbus_connect_irq(s, 4, qdev_get_gpio_in_named(iotkitdev, 196 "EXP_IRQ", combirqno)); 197 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); 198 } 199 200 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, 201 const char *name, hwaddr size) 202 { 203 MPS2SCC *scc = opaque; 204 DeviceState *sccdev; 205 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 206 207 object_initialize(scc, sizeof(mms->scc), TYPE_MPS2_SCC); 208 sccdev = DEVICE(scc); 209 qdev_set_parent_bus(sccdev, sysbus_get_default()); 210 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); 211 qdev_prop_set_uint32(sccdev, "scc-aid", 0x02000008); 212 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); 213 object_property_set_bool(OBJECT(scc), true, "realized", &error_fatal); 214 return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); 215 } 216 217 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, 218 const char *name, hwaddr size) 219 { 220 MPS2FPGAIO *fpgaio = opaque; 221 222 object_initialize(fpgaio, sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO); 223 qdev_set_parent_bus(DEVICE(fpgaio), sysbus_get_default()); 224 object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal); 225 return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); 226 } 227 228 static void mps2tz_common_init(MachineState *machine) 229 { 230 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); 231 MachineClass *mc = MACHINE_GET_CLASS(machine); 232 MemoryRegion *system_memory = get_system_memory(); 233 DeviceState *iotkitdev; 234 DeviceState *dev_splitter; 235 int i; 236 237 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { 238 error_report("This board can only be used with CPU %s", 239 mc->default_cpu_type); 240 exit(1); 241 } 242 243 init_sysbus_child(OBJECT(machine), "iotkit", &mms->iotkit, 244 sizeof(mms->iotkit), TYPE_IOTKIT); 245 iotkitdev = DEVICE(&mms->iotkit); 246 object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory), 247 "memory", &error_abort); 248 qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", 92); 249 qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); 250 object_property_set_bool(OBJECT(&mms->iotkit), true, "realized", 251 &error_fatal); 252 253 /* The sec_resp_cfg output from the IoTKit must be split into multiple 254 * lines, one for each of the PPCs we create here. 255 */ 256 object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter), 257 TYPE_SPLIT_IRQ); 258 object_property_add_child(OBJECT(machine), "sec-resp-splitter", 259 OBJECT(&mms->sec_resp_splitter), &error_abort); 260 object_property_set_int(OBJECT(&mms->sec_resp_splitter), 5, 261 "num-lines", &error_fatal); 262 object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true, 263 "realized", &error_fatal); 264 dev_splitter = DEVICE(&mms->sec_resp_splitter); 265 qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, 266 qdev_get_gpio_in(dev_splitter, 0)); 267 268 /* The IoTKit sets up much of the memory layout, including 269 * the aliases between secure and non-secure regions in the 270 * address space. The FPGA itself contains: 271 * 272 * 0x00000000..0x003fffff SSRAM1 273 * 0x00400000..0x007fffff alias of SSRAM1 274 * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3 275 * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices 276 * 0x80000000..0x80ffffff 16MB PSRAM 277 */ 278 279 /* The FPGA images have an odd combination of different RAMs, 280 * because in hardware they are different implementations and 281 * connected to different buses, giving varying performance/size 282 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily 283 * call the 16MB our "system memory", as it's the largest lump. 284 */ 285 memory_region_allocate_system_memory(&mms->psram, 286 NULL, "mps.ram", 0x01000000); 287 memory_region_add_subregion(system_memory, 0x80000000, &mms->psram); 288 289 /* The SSRAM memories should all be behind Memory Protection Controllers, 290 * but we don't implement that yet. 291 */ 292 make_ram(&mms->ssram1, "mps.ssram1", 0x00000000, 0x00400000); 293 make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x00400000); 294 295 make_ram(&mms->ssram23, "mps.ssram23", 0x28000000, 0x00400000); 296 297 /* The overflow IRQs for all UARTs are ORed together. 298 * Tx, Rx and "combined" IRQs are sent to the NVIC separately. 299 * Create the OR gate for this. 300 */ 301 object_initialize(&mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate), 302 TYPE_OR_IRQ); 303 object_property_add_child(OBJECT(mms), "uart-irq-orgate", 304 OBJECT(&mms->uart_irq_orgate), &error_abort); 305 object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines", 306 &error_fatal); 307 object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true, 308 "realized", &error_fatal); 309 qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, 310 qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 15)); 311 312 /* Most of the devices in the FPGA are behind Peripheral Protection 313 * Controllers. The required order for initializing things is: 314 * + initialize the PPC 315 * + initialize, configure and realize downstream devices 316 * + connect downstream device MemoryRegions to the PPC 317 * + realize the PPC 318 * + map the PPC's MemoryRegions to the places in the address map 319 * where the downstream devices should appear 320 * + wire up the PPC's control lines to the IoTKit object 321 */ 322 323 const PPCInfo ppcs[] = { { 324 .name = "apb_ppcexp0", 325 .ports = { 326 { "ssram-mpc0", make_unimp_dev, &mms->ssram_mpc[0], 327 0x58007000, 0x1000 }, 328 { "ssram-mpc1", make_unimp_dev, &mms->ssram_mpc[1], 329 0x58008000, 0x1000 }, 330 { "ssram-mpc2", make_unimp_dev, &mms->ssram_mpc[2], 331 0x58009000, 0x1000 }, 332 }, 333 }, { 334 .name = "apb_ppcexp1", 335 .ports = { 336 { "spi0", make_unimp_dev, &mms->spi[0], 0x40205000, 0x1000 }, 337 { "spi1", make_unimp_dev, &mms->spi[1], 0x40206000, 0x1000 }, 338 { "spi2", make_unimp_dev, &mms->spi[2], 0x40209000, 0x1000 }, 339 { "spi3", make_unimp_dev, &mms->spi[3], 0x4020a000, 0x1000 }, 340 { "spi4", make_unimp_dev, &mms->spi[4], 0x4020b000, 0x1000 }, 341 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 }, 342 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 }, 343 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 }, 344 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 }, 345 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 }, 346 { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40207000, 0x1000 }, 347 { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40208000, 0x1000 }, 348 { "i2c2", make_unimp_dev, &mms->i2c[2], 0x4020c000, 0x1000 }, 349 { "i2c3", make_unimp_dev, &mms->i2c[3], 0x4020d000, 0x1000 }, 350 }, 351 }, { 352 .name = "apb_ppcexp2", 353 .ports = { 354 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, 355 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 356 0x40301000, 0x1000 }, 357 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, 358 }, 359 }, { 360 .name = "ahb_ppcexp0", 361 .ports = { 362 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, 363 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, 364 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, 365 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, 366 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, 367 { "gpio4", make_unimp_dev, &mms->gpio[4], 0x40104000, 0x1000 }, 368 }, 369 }, { 370 .name = "ahb_ppcexp1", 371 .ports = { 372 { "dma0", make_unimp_dev, &mms->dma[0], 0x40110000, 0x1000 }, 373 { "dma1", make_unimp_dev, &mms->dma[1], 0x40111000, 0x1000 }, 374 { "dma2", make_unimp_dev, &mms->dma[2], 0x40112000, 0x1000 }, 375 { "dma3", make_unimp_dev, &mms->dma[3], 0x40113000, 0x1000 }, 376 }, 377 }, 378 }; 379 380 for (i = 0; i < ARRAY_SIZE(ppcs); i++) { 381 const PPCInfo *ppcinfo = &ppcs[i]; 382 TZPPC *ppc = &mms->ppc[i]; 383 DeviceState *ppcdev; 384 int port; 385 char *gpioname; 386 387 init_sysbus_child(OBJECT(machine), ppcinfo->name, ppc, 388 sizeof(TZPPC), TYPE_TZ_PPC); 389 ppcdev = DEVICE(ppc); 390 391 for (port = 0; port < TZ_NUM_PORTS; port++) { 392 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 393 MemoryRegion *mr; 394 char *portname; 395 396 if (!pinfo->devfn) { 397 continue; 398 } 399 400 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); 401 portname = g_strdup_printf("port[%d]", port); 402 object_property_set_link(OBJECT(ppc), OBJECT(mr), 403 portname, &error_fatal); 404 g_free(portname); 405 } 406 407 object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal); 408 409 for (port = 0; port < TZ_NUM_PORTS; port++) { 410 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 411 412 if (!pinfo->devfn) { 413 continue; 414 } 415 sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); 416 417 gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); 418 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 419 qdev_get_gpio_in_named(ppcdev, 420 "cfg_nonsec", 421 port)); 422 g_free(gpioname); 423 gpioname = g_strdup_printf("%s_ap", ppcinfo->name); 424 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 425 qdev_get_gpio_in_named(ppcdev, 426 "cfg_ap", port)); 427 g_free(gpioname); 428 } 429 430 gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); 431 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 432 qdev_get_gpio_in_named(ppcdev, 433 "irq_enable", 0)); 434 g_free(gpioname); 435 gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); 436 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 437 qdev_get_gpio_in_named(ppcdev, 438 "irq_clear", 0)); 439 g_free(gpioname); 440 gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); 441 qdev_connect_gpio_out_named(ppcdev, "irq", 0, 442 qdev_get_gpio_in_named(iotkitdev, 443 gpioname, 0)); 444 g_free(gpioname); 445 446 qdev_connect_gpio_out(dev_splitter, i, 447 qdev_get_gpio_in_named(ppcdev, 448 "cfg_sec_resp", 0)); 449 } 450 451 /* In hardware this is a LAN9220; the LAN9118 is software compatible 452 * except that it doesn't support the checksum-offload feature. 453 * The ethernet controller is not behind a PPC. 454 */ 455 lan9118_init(&nd_table[0], 0x42000000, 456 qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 16)); 457 458 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); 459 460 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); 461 } 462 463 static void mps2tz_class_init(ObjectClass *oc, void *data) 464 { 465 MachineClass *mc = MACHINE_CLASS(oc); 466 467 mc->init = mps2tz_common_init; 468 mc->max_cpus = 1; 469 } 470 471 static void mps2tz_an505_class_init(ObjectClass *oc, void *data) 472 { 473 MachineClass *mc = MACHINE_CLASS(oc); 474 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 475 476 mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; 477 mmc->fpga_type = FPGA_AN505; 478 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 479 mmc->scc_id = 0x41040000 | (505 << 4); 480 } 481 482 static const TypeInfo mps2tz_info = { 483 .name = TYPE_MPS2TZ_MACHINE, 484 .parent = TYPE_MACHINE, 485 .abstract = true, 486 .instance_size = sizeof(MPS2TZMachineState), 487 .class_size = sizeof(MPS2TZMachineClass), 488 .class_init = mps2tz_class_init, 489 }; 490 491 static const TypeInfo mps2tz_an505_info = { 492 .name = TYPE_MPS2TZ_AN505_MACHINE, 493 .parent = TYPE_MPS2TZ_MACHINE, 494 .class_init = mps2tz_an505_class_init, 495 }; 496 497 static void mps2tz_machine_init(void) 498 { 499 type_register_static(&mps2tz_info); 500 type_register_static(&mps2tz_an505_info); 501 } 502 503 type_init(mps2tz_machine_init); 504