1 /* 2 * ARM V2M MPS2 board emulation, trustzone aware FPGA images 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger 13 * FPGA but is otherwise the same as the 2). Since the CPU itself 14 * and most of the devices are in the FPGA, the details of the board 15 * as seen by the guest depend significantly on the FPGA image. 16 * This source file covers the following FPGA images, for TrustZone cores: 17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 18 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521 19 * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524 20 * 21 * Links to the TRM for the board itself and to the various Application 22 * Notes which document the FPGA images can be found here: 23 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 24 * 25 * Board TRM: 26 * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf 27 * Application Note AN505: 28 * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html 29 * Application Note AN521: 30 * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html 31 * Application Note AN524: 32 * https://developer.arm.com/documentation/dai0524/latest/ 33 * 34 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide 35 * (ARM ECM0601256) for the details of some of the device layout: 36 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html 37 * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines 38 * most of the device layout: 39 * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf 40 * 41 */ 42 43 #include "qemu/osdep.h" 44 #include "qemu/units.h" 45 #include "qemu/cutils.h" 46 #include "qapi/error.h" 47 #include "qemu/error-report.h" 48 #include "hw/arm/boot.h" 49 #include "hw/arm/armv7m.h" 50 #include "hw/or-irq.h" 51 #include "hw/boards.h" 52 #include "exec/address-spaces.h" 53 #include "sysemu/sysemu.h" 54 #include "hw/misc/unimp.h" 55 #include "hw/char/cmsdk-apb-uart.h" 56 #include "hw/timer/cmsdk-apb-timer.h" 57 #include "hw/misc/mps2-scc.h" 58 #include "hw/misc/mps2-fpgaio.h" 59 #include "hw/misc/tz-mpc.h" 60 #include "hw/misc/tz-msc.h" 61 #include "hw/arm/armsse.h" 62 #include "hw/dma/pl080.h" 63 #include "hw/rtc/pl031.h" 64 #include "hw/ssi/pl022.h" 65 #include "hw/i2c/arm_sbcon_i2c.h" 66 #include "hw/net/lan9118.h" 67 #include "net/net.h" 68 #include "hw/core/split-irq.h" 69 #include "hw/qdev-clock.h" 70 #include "qom/object.h" 71 72 #define MPS2TZ_NUMIRQ_MAX 95 73 #define MPS2TZ_RAM_MAX 4 74 75 typedef enum MPS2TZFPGAType { 76 FPGA_AN505, 77 FPGA_AN521, 78 FPGA_AN524, 79 } MPS2TZFPGAType; 80 81 /* 82 * Define the layout of RAM in a board, including which parts are 83 * behind which MPCs. 84 * mrindex specifies the index into mms->ram[] to use for the backing RAM; 85 * -1 means "use the system RAM". 86 */ 87 typedef struct RAMInfo { 88 const char *name; 89 uint32_t base; 90 uint32_t size; 91 int mpc; /* MPC number, -1 for "not behind an MPC" */ 92 int mrindex; 93 int flags; 94 } RAMInfo; 95 96 /* 97 * Flag values: 98 * IS_ALIAS: this RAM area is an alias to the upstream end of the 99 * MPC specified by its .mpc value 100 * IS_ROM: this RAM area is read-only 101 */ 102 #define IS_ALIAS 1 103 #define IS_ROM 2 104 105 struct MPS2TZMachineClass { 106 MachineClass parent; 107 MPS2TZFPGAType fpga_type; 108 uint32_t scc_id; 109 uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ 110 uint32_t len_oscclk; 111 const uint32_t *oscclk; 112 uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ 113 bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ 114 int numirq; /* Number of external interrupts */ 115 const RAMInfo *raminfo; 116 const char *armsse_type; 117 }; 118 119 struct MPS2TZMachineState { 120 MachineState parent; 121 122 ARMSSE iotkit; 123 MemoryRegion ram[MPS2TZ_RAM_MAX]; 124 MemoryRegion eth_usb_container; 125 126 MPS2SCC scc; 127 MPS2FPGAIO fpgaio; 128 TZPPC ppc[5]; 129 TZMPC mpc[3]; 130 PL022State spi[5]; 131 ArmSbconI2CState i2c[5]; 132 UnimplementedDeviceState i2s_audio; 133 UnimplementedDeviceState gpio[4]; 134 UnimplementedDeviceState gfx; 135 UnimplementedDeviceState cldc; 136 UnimplementedDeviceState usb; 137 PL031State rtc; 138 PL080State dma[4]; 139 TZMSC msc[4]; 140 CMSDKAPBUART uart[6]; 141 SplitIRQ sec_resp_splitter; 142 qemu_or_irq uart_irq_orgate; 143 DeviceState *lan9118; 144 SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; 145 Clock *sysclk; 146 Clock *s32kclk; 147 }; 148 149 #define TYPE_MPS2TZ_MACHINE "mps2tz" 150 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") 151 #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") 152 #define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524") 153 154 OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) 155 156 /* Slow 32Khz S32KCLK frequency in Hz */ 157 #define S32KCLK_FRQ (32 * 1000) 158 159 /* 160 * The MPS3 DDR is 2GiB, but on a 32-bit host QEMU doesn't permit 161 * emulation of that much guest RAM, so artificially make it smaller. 162 */ 163 #if HOST_LONG_BITS == 32 164 #define MPS3_DDR_SIZE (1 * GiB) 165 #else 166 #define MPS3_DDR_SIZE (2 * GiB) 167 #endif 168 169 static const uint32_t an505_oscclk[] = { 170 40000000, 171 24580000, 172 25000000, 173 }; 174 175 static const uint32_t an524_oscclk[] = { 176 24000000, 177 32000000, 178 50000000, 179 50000000, 180 24576000, 181 23750000, 182 }; 183 184 static const RAMInfo an505_raminfo[] = { { 185 .name = "ssram-0", 186 .base = 0x00000000, 187 .size = 0x00400000, 188 .mpc = 0, 189 .mrindex = 0, 190 }, { 191 .name = "ssram-1", 192 .base = 0x28000000, 193 .size = 0x00200000, 194 .mpc = 1, 195 .mrindex = 1, 196 }, { 197 .name = "ssram-2", 198 .base = 0x28200000, 199 .size = 0x00200000, 200 .mpc = 2, 201 .mrindex = 2, 202 }, { 203 .name = "ssram-0-alias", 204 .base = 0x00400000, 205 .size = 0x00400000, 206 .mpc = 0, 207 .mrindex = 3, 208 .flags = IS_ALIAS, 209 }, { 210 /* Use the largest bit of contiguous RAM as our "system memory" */ 211 .name = "mps.ram", 212 .base = 0x80000000, 213 .size = 16 * MiB, 214 .mpc = -1, 215 .mrindex = -1, 216 }, { 217 .name = NULL, 218 }, 219 }; 220 221 static const RAMInfo an524_raminfo[] = { { 222 .name = "bram", 223 .base = 0x00000000, 224 .size = 512 * KiB, 225 .mpc = 0, 226 .mrindex = 0, 227 }, { 228 .name = "sram", 229 .base = 0x20000000, 230 .size = 32 * 4 * KiB, 231 .mpc = 1, 232 .mrindex = 1, 233 }, { 234 /* We don't model QSPI flash yet; for now expose it as simple ROM */ 235 .name = "QSPI", 236 .base = 0x28000000, 237 .size = 8 * MiB, 238 .mpc = 1, 239 .mrindex = 2, 240 .flags = IS_ROM, 241 }, { 242 .name = "DDR", 243 .base = 0x60000000, 244 .size = MPS3_DDR_SIZE, 245 .mpc = 2, 246 .mrindex = -1, 247 }, { 248 .name = NULL, 249 }, 250 }; 251 252 static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc) 253 { 254 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 255 const RAMInfo *p; 256 257 for (p = mmc->raminfo; p->name; p++) { 258 if (p->mpc == mpc && !(p->flags & IS_ALIAS)) { 259 return p; 260 } 261 } 262 /* if raminfo array doesn't have an entry for each MPC this is a bug */ 263 g_assert_not_reached(); 264 } 265 266 static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms, 267 const RAMInfo *raminfo) 268 { 269 /* Return an initialized MemoryRegion for the RAMInfo. */ 270 MemoryRegion *ram; 271 272 if (raminfo->mrindex < 0) { 273 /* Means this RAMInfo is for QEMU's "system memory" */ 274 MachineState *machine = MACHINE(mms); 275 assert(!(raminfo->flags & IS_ROM)); 276 return machine->ram; 277 } 278 279 assert(raminfo->mrindex < MPS2TZ_RAM_MAX); 280 ram = &mms->ram[raminfo->mrindex]; 281 282 memory_region_init_ram(ram, NULL, raminfo->name, 283 raminfo->size, &error_fatal); 284 if (raminfo->flags & IS_ROM) { 285 memory_region_set_readonly(ram, true); 286 } 287 return ram; 288 } 289 290 /* Create an alias of an entire original MemoryRegion @orig 291 * located at @base in the memory map. 292 */ 293 static void make_ram_alias(MemoryRegion *mr, const char *name, 294 MemoryRegion *orig, hwaddr base) 295 { 296 memory_region_init_alias(mr, NULL, name, orig, 0, 297 memory_region_size(orig)); 298 memory_region_add_subregion(get_system_memory(), base, mr); 299 } 300 301 static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) 302 { 303 /* 304 * Return a qemu_irq which will signal IRQ n to all CPUs in the 305 * SSE. The irqno should be as the CPU sees it, so the first 306 * external-to-the-SSE interrupt is 32. 307 */ 308 MachineClass *mc = MACHINE_GET_CLASS(mms); 309 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 310 311 assert(irqno >= 32 && irqno < (mmc->numirq + 32)); 312 313 /* 314 * Convert from "CPU irq number" (as listed in the FPGA image 315 * documentation) to the SSE external-interrupt number. 316 */ 317 irqno -= 32; 318 319 if (mc->max_cpus > 1) { 320 return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); 321 } else { 322 return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno); 323 } 324 } 325 326 /* Most of the devices in the AN505 FPGA image sit behind 327 * Peripheral Protection Controllers. These data structures 328 * define the layout of which devices sit behind which PPCs. 329 * The devfn for each port is a function which creates, configures 330 * and initializes the device, returning the MemoryRegion which 331 * needs to be plugged into the downstream end of the PPC port. 332 */ 333 typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, 334 const char *name, hwaddr size, 335 const int *irqs); 336 337 typedef struct PPCPortInfo { 338 const char *name; 339 MakeDevFn *devfn; 340 void *opaque; 341 hwaddr addr; 342 hwaddr size; 343 int irqs[3]; /* currently no device needs more IRQ lines than this */ 344 } PPCPortInfo; 345 346 typedef struct PPCInfo { 347 const char *name; 348 PPCPortInfo ports[TZ_NUM_PORTS]; 349 } PPCInfo; 350 351 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, 352 void *opaque, 353 const char *name, hwaddr size, 354 const int *irqs) 355 { 356 /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, 357 * and return a pointer to its MemoryRegion. 358 */ 359 UnimplementedDeviceState *uds = opaque; 360 361 object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE); 362 qdev_prop_set_string(DEVICE(uds), "name", name); 363 qdev_prop_set_uint64(DEVICE(uds), "size", size); 364 sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); 365 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); 366 } 367 368 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, 369 const char *name, hwaddr size, 370 const int *irqs) 371 { 372 /* The irq[] array is tx, rx, combined, in that order */ 373 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 374 CMSDKAPBUART *uart = opaque; 375 int i = uart - &mms->uart[0]; 376 SysBusDevice *s; 377 DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); 378 379 object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART); 380 qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); 381 qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->sysclk_frq); 382 sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); 383 s = SYS_BUS_DEVICE(uart); 384 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 385 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); 386 sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); 387 sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); 388 sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2])); 389 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); 390 } 391 392 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, 393 const char *name, hwaddr size, 394 const int *irqs) 395 { 396 MPS2SCC *scc = opaque; 397 DeviceState *sccdev; 398 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 399 uint32_t i; 400 401 object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); 402 sccdev = DEVICE(scc); 403 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); 404 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); 405 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); 406 qdev_prop_set_uint32(sccdev, "len-oscclk", mmc->len_oscclk); 407 for (i = 0; i < mmc->len_oscclk; i++) { 408 g_autofree char *propname = g_strdup_printf("oscclk[%u]", i); 409 qdev_prop_set_uint32(sccdev, propname, mmc->oscclk[i]); 410 } 411 sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); 412 return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); 413 } 414 415 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, 416 const char *name, hwaddr size, 417 const int *irqs) 418 { 419 MPS2FPGAIO *fpgaio = opaque; 420 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 421 422 object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO); 423 qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds); 424 qdev_prop_set_bit(DEVICE(fpgaio), "has-switches", mmc->fpgaio_has_switches); 425 sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); 426 return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); 427 } 428 429 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, 430 const char *name, hwaddr size, 431 const int *irqs) 432 { 433 SysBusDevice *s; 434 NICInfo *nd = &nd_table[0]; 435 436 /* In hardware this is a LAN9220; the LAN9118 is software compatible 437 * except that it doesn't support the checksum-offload feature. 438 */ 439 qemu_check_nic_model(nd, "lan9118"); 440 mms->lan9118 = qdev_new(TYPE_LAN9118); 441 qdev_set_nic_properties(mms->lan9118, nd); 442 443 s = SYS_BUS_DEVICE(mms->lan9118); 444 sysbus_realize_and_unref(s, &error_fatal); 445 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 446 return sysbus_mmio_get_region(s, 0); 447 } 448 449 static MemoryRegion *make_eth_usb(MPS2TZMachineState *mms, void *opaque, 450 const char *name, hwaddr size, 451 const int *irqs) 452 { 453 /* 454 * The AN524 makes the ethernet and USB share a PPC port. 455 * irqs[] is the ethernet IRQ. 456 */ 457 SysBusDevice *s; 458 NICInfo *nd = &nd_table[0]; 459 460 memory_region_init(&mms->eth_usb_container, OBJECT(mms), 461 "mps2-tz-eth-usb-container", 0x200000); 462 463 /* 464 * In hardware this is a LAN9220; the LAN9118 is software compatible 465 * except that it doesn't support the checksum-offload feature. 466 */ 467 qemu_check_nic_model(nd, "lan9118"); 468 mms->lan9118 = qdev_new(TYPE_LAN9118); 469 qdev_set_nic_properties(mms->lan9118, nd); 470 471 s = SYS_BUS_DEVICE(mms->lan9118); 472 sysbus_realize_and_unref(s, &error_fatal); 473 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 474 475 memory_region_add_subregion(&mms->eth_usb_container, 476 0, sysbus_mmio_get_region(s, 0)); 477 478 /* The USB OTG controller is an ISP1763; we don't have a model of it. */ 479 object_initialize_child(OBJECT(mms), "usb-otg", 480 &mms->usb, TYPE_UNIMPLEMENTED_DEVICE); 481 qdev_prop_set_string(DEVICE(&mms->usb), "name", "usb-otg"); 482 qdev_prop_set_uint64(DEVICE(&mms->usb), "size", 0x100000); 483 s = SYS_BUS_DEVICE(&mms->usb); 484 sysbus_realize(s, &error_fatal); 485 486 memory_region_add_subregion(&mms->eth_usb_container, 487 0x100000, sysbus_mmio_get_region(s, 0)); 488 489 return &mms->eth_usb_container; 490 } 491 492 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, 493 const char *name, hwaddr size, 494 const int *irqs) 495 { 496 TZMPC *mpc = opaque; 497 int i = mpc - &mms->mpc[0]; 498 MemoryRegion *upstream; 499 const RAMInfo *raminfo = find_raminfo_for_mpc(mms, i); 500 MemoryRegion *ram = mr_for_raminfo(mms, raminfo); 501 502 object_initialize_child(OBJECT(mms), name, mpc, TYPE_TZ_MPC); 503 object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ram), 504 &error_fatal); 505 sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); 506 /* Map the upstream end of the MPC into system memory */ 507 upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); 508 memory_region_add_subregion(get_system_memory(), raminfo->base, upstream); 509 /* and connect its interrupt to the IoTKit */ 510 qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, 511 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 512 "mpcexp_status", i)); 513 514 /* Return the register interface MR for our caller to map behind the PPC */ 515 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); 516 } 517 518 static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, 519 const char *name, hwaddr size, 520 const int *irqs) 521 { 522 /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */ 523 PL080State *dma = opaque; 524 int i = dma - &mms->dma[0]; 525 SysBusDevice *s; 526 char *mscname = g_strdup_printf("%s-msc", name); 527 TZMSC *msc = &mms->msc[i]; 528 DeviceState *iotkitdev = DEVICE(&mms->iotkit); 529 MemoryRegion *msc_upstream; 530 MemoryRegion *msc_downstream; 531 532 /* 533 * Each DMA device is a PL081 whose transaction master interface 534 * is guarded by a Master Security Controller. The downstream end of 535 * the MSC connects to the IoTKit AHB Slave Expansion port, so the 536 * DMA devices can see all devices and memory that the CPU does. 537 */ 538 object_initialize_child(OBJECT(mms), mscname, msc, TYPE_TZ_MSC); 539 msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0); 540 object_property_set_link(OBJECT(msc), "downstream", 541 OBJECT(msc_downstream), &error_fatal); 542 object_property_set_link(OBJECT(msc), "idau", OBJECT(mms), &error_fatal); 543 sysbus_realize(SYS_BUS_DEVICE(msc), &error_fatal); 544 545 qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0, 546 qdev_get_gpio_in_named(iotkitdev, 547 "mscexp_status", i)); 548 qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i, 549 qdev_get_gpio_in_named(DEVICE(msc), 550 "irq_clear", 0)); 551 qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i, 552 qdev_get_gpio_in_named(DEVICE(msc), 553 "cfg_nonsec", 0)); 554 qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter), 555 ARRAY_SIZE(mms->ppc) + i, 556 qdev_get_gpio_in_named(DEVICE(msc), 557 "cfg_sec_resp", 0)); 558 msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0); 559 560 object_initialize_child(OBJECT(mms), name, dma, TYPE_PL081); 561 object_property_set_link(OBJECT(dma), "downstream", OBJECT(msc_upstream), 562 &error_fatal); 563 sysbus_realize(SYS_BUS_DEVICE(dma), &error_fatal); 564 565 s = SYS_BUS_DEVICE(dma); 566 /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ 567 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 568 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); 569 sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqs[2])); 570 571 g_free(mscname); 572 return sysbus_mmio_get_region(s, 0); 573 } 574 575 static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, 576 const char *name, hwaddr size, 577 const int *irqs) 578 { 579 /* 580 * The AN505 has five PL022 SPI controllers. 581 * One of these should have the LCD controller behind it; the others 582 * are connected only to the FPGA's "general purpose SPI connector" 583 * or "shield" expansion connectors. 584 * Note that if we do implement devices behind SPI, the chip select 585 * lines are set via the "MISC" register in the MPS2 FPGAIO device. 586 */ 587 PL022State *spi = opaque; 588 SysBusDevice *s; 589 590 object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022); 591 sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal); 592 s = SYS_BUS_DEVICE(spi); 593 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 594 return sysbus_mmio_get_region(s, 0); 595 } 596 597 static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, 598 const char *name, hwaddr size, 599 const int *irqs) 600 { 601 ArmSbconI2CState *i2c = opaque; 602 SysBusDevice *s; 603 604 object_initialize_child(OBJECT(mms), name, i2c, TYPE_ARM_SBCON_I2C); 605 s = SYS_BUS_DEVICE(i2c); 606 sysbus_realize(s, &error_fatal); 607 return sysbus_mmio_get_region(s, 0); 608 } 609 610 static MemoryRegion *make_rtc(MPS2TZMachineState *mms, void *opaque, 611 const char *name, hwaddr size, 612 const int *irqs) 613 { 614 PL031State *pl031 = opaque; 615 SysBusDevice *s; 616 617 object_initialize_child(OBJECT(mms), name, pl031, TYPE_PL031); 618 s = SYS_BUS_DEVICE(pl031); 619 sysbus_realize(s, &error_fatal); 620 /* 621 * The board docs don't give an IRQ number for the PL031, so 622 * presumably it is not connected. 623 */ 624 return sysbus_mmio_get_region(s, 0); 625 } 626 627 static void create_non_mpc_ram(MPS2TZMachineState *mms) 628 { 629 /* 630 * Handle the RAMs which are either not behind MPCs or which are 631 * aliases to another MPC. 632 */ 633 const RAMInfo *p; 634 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 635 636 for (p = mmc->raminfo; p->name; p++) { 637 if (p->flags & IS_ALIAS) { 638 SysBusDevice *mpc_sbd = SYS_BUS_DEVICE(&mms->mpc[p->mpc]); 639 MemoryRegion *upstream = sysbus_mmio_get_region(mpc_sbd, 1); 640 make_ram_alias(&mms->ram[p->mrindex], p->name, upstream, p->base); 641 } else if (p->mpc == -1) { 642 /* RAM not behind an MPC */ 643 MemoryRegion *mr = mr_for_raminfo(mms, p); 644 memory_region_add_subregion(get_system_memory(), p->base, mr); 645 } 646 } 647 } 648 649 static uint32_t boot_ram_size(MPS2TZMachineState *mms) 650 { 651 /* Return the size of the RAM block at guest address zero */ 652 const RAMInfo *p; 653 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 654 655 for (p = mmc->raminfo; p->name; p++) { 656 if (p->base == 0) { 657 return p->size; 658 } 659 } 660 g_assert_not_reached(); 661 } 662 663 static void mps2tz_common_init(MachineState *machine) 664 { 665 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); 666 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 667 MachineClass *mc = MACHINE_GET_CLASS(machine); 668 MemoryRegion *system_memory = get_system_memory(); 669 DeviceState *iotkitdev; 670 DeviceState *dev_splitter; 671 const PPCInfo *ppcs; 672 int num_ppcs; 673 int i; 674 675 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { 676 error_report("This board can only be used with CPU %s", 677 mc->default_cpu_type); 678 exit(1); 679 } 680 681 if (machine->ram_size != mc->default_ram_size) { 682 char *sz = size_to_str(mc->default_ram_size); 683 error_report("Invalid RAM size, should be %s", sz); 684 g_free(sz); 685 exit(EXIT_FAILURE); 686 } 687 688 /* These clocks don't need migration because they are fixed-frequency */ 689 mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); 690 clock_set_hz(mms->sysclk, mmc->sysclk_frq); 691 mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); 692 clock_set_hz(mms->s32kclk, S32KCLK_FRQ); 693 694 object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit, 695 mmc->armsse_type); 696 iotkitdev = DEVICE(&mms->iotkit); 697 object_property_set_link(OBJECT(&mms->iotkit), "memory", 698 OBJECT(system_memory), &error_abort); 699 qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); 700 qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); 701 qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); 702 sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); 703 704 /* 705 * If this board has more than one CPU, then we need to create splitters 706 * to feed the IRQ inputs for each CPU in the SSE from each device in the 707 * board. If there is only one CPU, we can just wire the device IRQ 708 * directly to the SSE's IRQ input. 709 */ 710 assert(mmc->numirq <= MPS2TZ_NUMIRQ_MAX); 711 if (mc->max_cpus > 1) { 712 for (i = 0; i < mmc->numirq; i++) { 713 char *name = g_strdup_printf("mps2-irq-splitter%d", i); 714 SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; 715 716 object_initialize_child_with_props(OBJECT(machine), name, 717 splitter, sizeof(*splitter), 718 TYPE_SPLIT_IRQ, &error_fatal, 719 NULL); 720 g_free(name); 721 722 object_property_set_int(OBJECT(splitter), "num-lines", 2, 723 &error_fatal); 724 qdev_realize(DEVICE(splitter), NULL, &error_fatal); 725 qdev_connect_gpio_out(DEVICE(splitter), 0, 726 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 727 "EXP_IRQ", i)); 728 qdev_connect_gpio_out(DEVICE(splitter), 1, 729 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 730 "EXP_CPU1_IRQ", i)); 731 } 732 } 733 734 /* The sec_resp_cfg output from the IoTKit must be split into multiple 735 * lines, one for each of the PPCs we create here, plus one per MSC. 736 */ 737 object_initialize_child(OBJECT(machine), "sec-resp-splitter", 738 &mms->sec_resp_splitter, TYPE_SPLIT_IRQ); 739 object_property_set_int(OBJECT(&mms->sec_resp_splitter), "num-lines", 740 ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc), 741 &error_fatal); 742 qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal); 743 dev_splitter = DEVICE(&mms->sec_resp_splitter); 744 qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, 745 qdev_get_gpio_in(dev_splitter, 0)); 746 747 /* 748 * The IoTKit sets up much of the memory layout, including 749 * the aliases between secure and non-secure regions in the 750 * address space, and also most of the devices in the system. 751 * The FPGA itself contains various RAMs and some additional devices. 752 * The FPGA images have an odd combination of different RAMs, 753 * because in hardware they are different implementations and 754 * connected to different buses, giving varying performance/size 755 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily 756 * call the largest lump our "system memory". 757 */ 758 759 /* 760 * The overflow IRQs for all UARTs are ORed together. 761 * Tx, Rx and "combined" IRQs are sent to the NVIC separately. 762 * Create the OR gate for this: it has one input for the TX overflow 763 * and one for the RX overflow for each UART we might have. 764 * (If the board has fewer than the maximum possible number of UARTs 765 * those inputs are never wired up and are treated as always-zero.) 766 */ 767 object_initialize_child(OBJECT(mms), "uart-irq-orgate", 768 &mms->uart_irq_orgate, TYPE_OR_IRQ); 769 object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", 770 2 * ARRAY_SIZE(mms->uart), 771 &error_fatal); 772 qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); 773 qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, 774 get_sse_irq_in(mms, 47)); 775 776 /* Most of the devices in the FPGA are behind Peripheral Protection 777 * Controllers. The required order for initializing things is: 778 * + initialize the PPC 779 * + initialize, configure and realize downstream devices 780 * + connect downstream device MemoryRegions to the PPC 781 * + realize the PPC 782 * + map the PPC's MemoryRegions to the places in the address map 783 * where the downstream devices should appear 784 * + wire up the PPC's control lines to the IoTKit object 785 */ 786 787 const PPCInfo an505_ppcs[] = { { 788 .name = "apb_ppcexp0", 789 .ports = { 790 { "ssram-0-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, 791 { "ssram-1-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, 792 { "ssram-2-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, 793 }, 794 }, { 795 .name = "apb_ppcexp1", 796 .ports = { 797 { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000, { 51 } }, 798 { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000, { 52 } }, 799 { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000, { 53 } }, 800 { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000, { 54 } }, 801 { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000, { 55 } }, 802 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000, { 32, 33, 42 } }, 803 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000, { 34, 35, 43 } }, 804 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000, { 36, 37, 44 } }, 805 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000, { 38, 39, 45 } }, 806 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000, { 40, 41, 46 } }, 807 { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 }, 808 { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 }, 809 { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 }, 810 { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000 }, 811 }, 812 }, { 813 .name = "apb_ppcexp2", 814 .ports = { 815 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, 816 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 817 0x40301000, 0x1000 }, 818 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, 819 }, 820 }, { 821 .name = "ahb_ppcexp0", 822 .ports = { 823 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, 824 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, 825 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, 826 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, 827 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, 828 { "eth", make_eth_dev, NULL, 0x42000000, 0x100000, { 48 } }, 829 }, 830 }, { 831 .name = "ahb_ppcexp1", 832 .ports = { 833 { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000, { 58, 56, 57 } }, 834 { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000, { 61, 59, 60 } }, 835 { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000, { 64, 62, 63 } }, 836 { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000, { 67, 65, 66 } }, 837 }, 838 }, 839 }; 840 841 const PPCInfo an524_ppcs[] = { { 842 .name = "apb_ppcexp0", 843 .ports = { 844 { "bram-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, 845 { "qspi-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, 846 { "ddr-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, 847 }, 848 }, { 849 .name = "apb_ppcexp1", 850 .ports = { 851 { "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000 }, 852 { "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000 }, 853 { "spi0", make_spi, &mms->spi[0], 0x41202000, 0x1000, { 52 } }, 854 { "spi1", make_spi, &mms->spi[1], 0x41203000, 0x1000, { 53 } }, 855 { "spi2", make_spi, &mms->spi[2], 0x41204000, 0x1000, { 54 } }, 856 { "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000 }, 857 { "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000 }, 858 { /* port 7 reserved */ }, 859 { "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000 }, 860 }, 861 }, { 862 .name = "apb_ppcexp2", 863 .ports = { 864 { "scc", make_scc, &mms->scc, 0x41300000, 0x1000 }, 865 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 866 0x41301000, 0x1000 }, 867 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x41302000, 0x1000 }, 868 { "uart0", make_uart, &mms->uart[0], 0x41303000, 0x1000, { 32, 33, 42 } }, 869 { "uart1", make_uart, &mms->uart[1], 0x41304000, 0x1000, { 34, 35, 43 } }, 870 { "uart2", make_uart, &mms->uart[2], 0x41305000, 0x1000, { 36, 37, 44 } }, 871 { "uart3", make_uart, &mms->uart[3], 0x41306000, 0x1000, { 38, 39, 45 } }, 872 { "uart4", make_uart, &mms->uart[4], 0x41307000, 0x1000, { 40, 41, 46 } }, 873 { "uart5", make_uart, &mms->uart[5], 0x41308000, 0x1000, { 124, 125, 126 } }, 874 875 { /* port 9 reserved */ }, 876 { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 }, 877 { "rtc", make_rtc, &mms->rtc, 0x4130b000, 0x1000 }, 878 }, 879 }, { 880 .name = "ahb_ppcexp0", 881 .ports = { 882 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 }, 883 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, 884 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, 885 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, 886 { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 48 } }, 887 }, 888 }, 889 }; 890 891 switch (mmc->fpga_type) { 892 case FPGA_AN505: 893 case FPGA_AN521: 894 ppcs = an505_ppcs; 895 num_ppcs = ARRAY_SIZE(an505_ppcs); 896 break; 897 case FPGA_AN524: 898 ppcs = an524_ppcs; 899 num_ppcs = ARRAY_SIZE(an524_ppcs); 900 break; 901 default: 902 g_assert_not_reached(); 903 } 904 905 for (i = 0; i < num_ppcs; i++) { 906 const PPCInfo *ppcinfo = &ppcs[i]; 907 TZPPC *ppc = &mms->ppc[i]; 908 DeviceState *ppcdev; 909 int port; 910 char *gpioname; 911 912 object_initialize_child(OBJECT(machine), ppcinfo->name, ppc, 913 TYPE_TZ_PPC); 914 ppcdev = DEVICE(ppc); 915 916 for (port = 0; port < TZ_NUM_PORTS; port++) { 917 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 918 MemoryRegion *mr; 919 char *portname; 920 921 if (!pinfo->devfn) { 922 continue; 923 } 924 925 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size, 926 pinfo->irqs); 927 portname = g_strdup_printf("port[%d]", port); 928 object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), 929 &error_fatal); 930 g_free(portname); 931 } 932 933 sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal); 934 935 for (port = 0; port < TZ_NUM_PORTS; port++) { 936 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 937 938 if (!pinfo->devfn) { 939 continue; 940 } 941 sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); 942 943 gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); 944 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 945 qdev_get_gpio_in_named(ppcdev, 946 "cfg_nonsec", 947 port)); 948 g_free(gpioname); 949 gpioname = g_strdup_printf("%s_ap", ppcinfo->name); 950 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 951 qdev_get_gpio_in_named(ppcdev, 952 "cfg_ap", port)); 953 g_free(gpioname); 954 } 955 956 gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); 957 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 958 qdev_get_gpio_in_named(ppcdev, 959 "irq_enable", 0)); 960 g_free(gpioname); 961 gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); 962 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 963 qdev_get_gpio_in_named(ppcdev, 964 "irq_clear", 0)); 965 g_free(gpioname); 966 gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); 967 qdev_connect_gpio_out_named(ppcdev, "irq", 0, 968 qdev_get_gpio_in_named(iotkitdev, 969 gpioname, 0)); 970 g_free(gpioname); 971 972 qdev_connect_gpio_out(dev_splitter, i, 973 qdev_get_gpio_in_named(ppcdev, 974 "cfg_sec_resp", 0)); 975 } 976 977 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); 978 979 create_non_mpc_ram(mms); 980 981 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 982 boot_ram_size(mms)); 983 } 984 985 static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, 986 int *iregion, bool *exempt, bool *ns, bool *nsc) 987 { 988 /* 989 * The MPS2 TZ FPGA images have IDAUs in them which are connected to 990 * the Master Security Controllers. Thes have the same logic as 991 * is used by the IoTKit for the IDAU connected to the CPU, except 992 * that MSCs don't care about the NSC attribute. 993 */ 994 int region = extract32(address, 28, 4); 995 996 *ns = !(region & 1); 997 *nsc = false; 998 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 999 *exempt = (address & 0xeff00000) == 0xe0000000; 1000 *iregion = region; 1001 } 1002 1003 static void mps2tz_class_init(ObjectClass *oc, void *data) 1004 { 1005 MachineClass *mc = MACHINE_CLASS(oc); 1006 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); 1007 1008 mc->init = mps2tz_common_init; 1009 iic->check = mps2_tz_idau_check; 1010 } 1011 1012 static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc) 1013 { 1014 /* 1015 * Set mc->default_ram_size and default_ram_id from the 1016 * information in mmc->raminfo. 1017 */ 1018 MachineClass *mc = MACHINE_CLASS(mmc); 1019 const RAMInfo *p; 1020 1021 for (p = mmc->raminfo; p->name; p++) { 1022 if (p->mrindex < 0) { 1023 /* Found the entry for "system memory" */ 1024 mc->default_ram_size = p->size; 1025 mc->default_ram_id = p->name; 1026 return; 1027 } 1028 } 1029 g_assert_not_reached(); 1030 } 1031 1032 static void mps2tz_an505_class_init(ObjectClass *oc, void *data) 1033 { 1034 MachineClass *mc = MACHINE_CLASS(oc); 1035 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1036 1037 mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; 1038 mc->default_cpus = 1; 1039 mc->min_cpus = mc->default_cpus; 1040 mc->max_cpus = mc->default_cpus; 1041 mmc->fpga_type = FPGA_AN505; 1042 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 1043 mmc->scc_id = 0x41045050; 1044 mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ 1045 mmc->oscclk = an505_oscclk; 1046 mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); 1047 mmc->fpgaio_num_leds = 2; 1048 mmc->fpgaio_has_switches = false; 1049 mmc->numirq = 92; 1050 mmc->raminfo = an505_raminfo; 1051 mmc->armsse_type = TYPE_IOTKIT; 1052 mps2tz_set_default_ram_info(mmc); 1053 } 1054 1055 static void mps2tz_an521_class_init(ObjectClass *oc, void *data) 1056 { 1057 MachineClass *mc = MACHINE_CLASS(oc); 1058 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1059 1060 mc->desc = "ARM MPS2 with AN521 FPGA image for dual Cortex-M33"; 1061 mc->default_cpus = 2; 1062 mc->min_cpus = mc->default_cpus; 1063 mc->max_cpus = mc->default_cpus; 1064 mmc->fpga_type = FPGA_AN521; 1065 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 1066 mmc->scc_id = 0x41045210; 1067 mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ 1068 mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */ 1069 mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); 1070 mmc->fpgaio_num_leds = 2; 1071 mmc->fpgaio_has_switches = false; 1072 mmc->numirq = 92; 1073 mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */ 1074 mmc->armsse_type = TYPE_SSE200; 1075 mps2tz_set_default_ram_info(mmc); 1076 } 1077 1078 static void mps3tz_an524_class_init(ObjectClass *oc, void *data) 1079 { 1080 MachineClass *mc = MACHINE_CLASS(oc); 1081 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1082 1083 mc->desc = "ARM MPS3 with AN524 FPGA image for dual Cortex-M33"; 1084 mc->default_cpus = 2; 1085 mc->min_cpus = mc->default_cpus; 1086 mc->max_cpus = mc->default_cpus; 1087 mmc->fpga_type = FPGA_AN524; 1088 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 1089 mmc->scc_id = 0x41045240; 1090 mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */ 1091 mmc->oscclk = an524_oscclk; 1092 mmc->len_oscclk = ARRAY_SIZE(an524_oscclk); 1093 mmc->fpgaio_num_leds = 10; 1094 mmc->fpgaio_has_switches = true; 1095 mmc->numirq = 95; 1096 mmc->raminfo = an524_raminfo; 1097 mmc->armsse_type = TYPE_SSE200; 1098 mps2tz_set_default_ram_info(mmc); 1099 } 1100 1101 static const TypeInfo mps2tz_info = { 1102 .name = TYPE_MPS2TZ_MACHINE, 1103 .parent = TYPE_MACHINE, 1104 .abstract = true, 1105 .instance_size = sizeof(MPS2TZMachineState), 1106 .class_size = sizeof(MPS2TZMachineClass), 1107 .class_init = mps2tz_class_init, 1108 .interfaces = (InterfaceInfo[]) { 1109 { TYPE_IDAU_INTERFACE }, 1110 { } 1111 }, 1112 }; 1113 1114 static const TypeInfo mps2tz_an505_info = { 1115 .name = TYPE_MPS2TZ_AN505_MACHINE, 1116 .parent = TYPE_MPS2TZ_MACHINE, 1117 .class_init = mps2tz_an505_class_init, 1118 }; 1119 1120 static const TypeInfo mps2tz_an521_info = { 1121 .name = TYPE_MPS2TZ_AN521_MACHINE, 1122 .parent = TYPE_MPS2TZ_MACHINE, 1123 .class_init = mps2tz_an521_class_init, 1124 }; 1125 1126 static const TypeInfo mps3tz_an524_info = { 1127 .name = TYPE_MPS3TZ_AN524_MACHINE, 1128 .parent = TYPE_MPS2TZ_MACHINE, 1129 .class_init = mps3tz_an524_class_init, 1130 }; 1131 1132 static void mps2tz_machine_init(void) 1133 { 1134 type_register_static(&mps2tz_info); 1135 type_register_static(&mps2tz_an505_info); 1136 type_register_static(&mps2tz_an521_info); 1137 type_register_static(&mps3tz_an524_info); 1138 } 1139 1140 type_init(mps2tz_machine_init); 1141