1 /* 2 * ARM V2M MPS2 board emulation, trustzone aware FPGA images 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger 13 * FPGA but is otherwise the same as the 2). Since the CPU itself 14 * and most of the devices are in the FPGA, the details of the board 15 * as seen by the guest depend significantly on the FPGA image. 16 * This source file covers the following FPGA images, for TrustZone cores: 17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 18 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521 19 * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524 20 * "mps2-an547" -- Single Cortex-M55 as documented in Application Note AN547 21 * 22 * Links to the TRM for the board itself and to the various Application 23 * Notes which document the FPGA images can be found here: 24 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 25 * 26 * Board TRM: 27 * https://developer.arm.com/documentation/100112/latest/ 28 * Application Note AN505: 29 * https://developer.arm.com/documentation/dai0505/latest/ 30 * Application Note AN521: 31 * https://developer.arm.com/documentation/dai0521/latest/ 32 * Application Note AN524: 33 * https://developer.arm.com/documentation/dai0524/latest/ 34 * Application Note AN547: 35 * https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf 36 * 37 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide 38 * (ARM ECM0601256) for the details of some of the device layout: 39 * https://developer.arm.com/documentation/ecm0601256/latest 40 * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines 41 * most of the device layout: 42 * https://developer.arm.com/documentation/101104/latest/ 43 * and the AN547 uses the SSE-300, whose layout is in the SSE-300 TRM: 44 * https://developer.arm.com/documentation/101773/latest/ 45 */ 46 47 #include "qemu/osdep.h" 48 #include "qemu/units.h" 49 #include "qemu/cutils.h" 50 #include "qapi/error.h" 51 #include "qemu/error-report.h" 52 #include "hw/arm/boot.h" 53 #include "hw/arm/armv7m.h" 54 #include "hw/or-irq.h" 55 #include "hw/boards.h" 56 #include "exec/address-spaces.h" 57 #include "sysemu/sysemu.h" 58 #include "sysemu/reset.h" 59 #include "hw/misc/unimp.h" 60 #include "hw/char/cmsdk-apb-uart.h" 61 #include "hw/timer/cmsdk-apb-timer.h" 62 #include "hw/misc/mps2-scc.h" 63 #include "hw/misc/mps2-fpgaio.h" 64 #include "hw/misc/tz-mpc.h" 65 #include "hw/misc/tz-msc.h" 66 #include "hw/arm/armsse.h" 67 #include "hw/dma/pl080.h" 68 #include "hw/rtc/pl031.h" 69 #include "hw/ssi/pl022.h" 70 #include "hw/i2c/arm_sbcon_i2c.h" 71 #include "hw/net/lan9118.h" 72 #include "net/net.h" 73 #include "hw/core/split-irq.h" 74 #include "hw/qdev-clock.h" 75 #include "qom/object.h" 76 #include "hw/irq.h" 77 78 #define MPS2TZ_NUMIRQ_MAX 96 79 #define MPS2TZ_RAM_MAX 5 80 81 typedef enum MPS2TZFPGAType { 82 FPGA_AN505, 83 FPGA_AN521, 84 FPGA_AN524, 85 FPGA_AN547, 86 } MPS2TZFPGAType; 87 88 /* 89 * Define the layout of RAM in a board, including which parts are 90 * behind which MPCs. 91 * mrindex specifies the index into mms->ram[] to use for the backing RAM; 92 * -1 means "use the system RAM". 93 */ 94 typedef struct RAMInfo { 95 const char *name; 96 uint32_t base; 97 uint32_t size; 98 int mpc; /* MPC number, -1 for "not behind an MPC" */ 99 int mrindex; 100 int flags; 101 } RAMInfo; 102 103 /* 104 * Flag values: 105 * IS_ALIAS: this RAM area is an alias to the upstream end of the 106 * MPC specified by its .mpc value 107 * IS_ROM: this RAM area is read-only 108 */ 109 #define IS_ALIAS 1 110 #define IS_ROM 2 111 112 struct MPS2TZMachineClass { 113 MachineClass parent; 114 MPS2TZFPGAType fpga_type; 115 uint32_t scc_id; 116 uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ 117 uint32_t apb_periph_frq; /* APB peripheral frequency in Hz */ 118 uint32_t len_oscclk; 119 const uint32_t *oscclk; 120 uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ 121 bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ 122 bool fpgaio_has_dbgctrl; /* Does FPGAIO have DBGCTRL register? */ 123 int numirq; /* Number of external interrupts */ 124 int uart_overflow_irq; /* number of the combined UART overflow IRQ */ 125 uint32_t init_svtor; /* init-svtor setting for SSE */ 126 const RAMInfo *raminfo; 127 const char *armsse_type; 128 }; 129 130 struct MPS2TZMachineState { 131 MachineState parent; 132 133 ARMSSE iotkit; 134 MemoryRegion ram[MPS2TZ_RAM_MAX]; 135 MemoryRegion eth_usb_container; 136 137 MPS2SCC scc; 138 MPS2FPGAIO fpgaio; 139 TZPPC ppc[5]; 140 TZMPC mpc[3]; 141 PL022State spi[5]; 142 ArmSbconI2CState i2c[5]; 143 UnimplementedDeviceState i2s_audio; 144 UnimplementedDeviceState gpio[4]; 145 UnimplementedDeviceState gfx; 146 UnimplementedDeviceState cldc; 147 UnimplementedDeviceState usb; 148 PL031State rtc; 149 PL080State dma[4]; 150 TZMSC msc[4]; 151 CMSDKAPBUART uart[6]; 152 SplitIRQ sec_resp_splitter; 153 qemu_or_irq uart_irq_orgate; 154 DeviceState *lan9118; 155 SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; 156 Clock *sysclk; 157 Clock *s32kclk; 158 159 bool remap; 160 qemu_irq remap_irq; 161 }; 162 163 #define TYPE_MPS2TZ_MACHINE "mps2tz" 164 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") 165 #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") 166 #define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524") 167 #define TYPE_MPS3TZ_AN547_MACHINE MACHINE_TYPE_NAME("mps3-an547") 168 169 OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) 170 171 /* Slow 32Khz S32KCLK frequency in Hz */ 172 #define S32KCLK_FRQ (32 * 1000) 173 174 /* 175 * The MPS3 DDR is 2GiB, but on a 32-bit host QEMU doesn't permit 176 * emulation of that much guest RAM, so artificially make it smaller. 177 */ 178 #if HOST_LONG_BITS == 32 179 #define MPS3_DDR_SIZE (1 * GiB) 180 #else 181 #define MPS3_DDR_SIZE (2 * GiB) 182 #endif 183 184 static const uint32_t an505_oscclk[] = { 185 40000000, 186 24580000, 187 25000000, 188 }; 189 190 static const uint32_t an524_oscclk[] = { 191 24000000, 192 32000000, 193 50000000, 194 50000000, 195 24576000, 196 23750000, 197 }; 198 199 static const RAMInfo an505_raminfo[] = { { 200 .name = "ssram-0", 201 .base = 0x00000000, 202 .size = 0x00400000, 203 .mpc = 0, 204 .mrindex = 0, 205 }, { 206 .name = "ssram-1", 207 .base = 0x28000000, 208 .size = 0x00200000, 209 .mpc = 1, 210 .mrindex = 1, 211 }, { 212 .name = "ssram-2", 213 .base = 0x28200000, 214 .size = 0x00200000, 215 .mpc = 2, 216 .mrindex = 2, 217 }, { 218 .name = "ssram-0-alias", 219 .base = 0x00400000, 220 .size = 0x00400000, 221 .mpc = 0, 222 .mrindex = 3, 223 .flags = IS_ALIAS, 224 }, { 225 /* Use the largest bit of contiguous RAM as our "system memory" */ 226 .name = "mps.ram", 227 .base = 0x80000000, 228 .size = 16 * MiB, 229 .mpc = -1, 230 .mrindex = -1, 231 }, { 232 .name = NULL, 233 }, 234 }; 235 236 /* 237 * Note that the addresses and MPC numbering here should match up 238 * with those used in remap_memory(), which can swap the BRAM and QSPI. 239 */ 240 static const RAMInfo an524_raminfo[] = { { 241 .name = "bram", 242 .base = 0x00000000, 243 .size = 512 * KiB, 244 .mpc = 0, 245 .mrindex = 0, 246 }, { 247 .name = "sram", 248 .base = 0x20000000, 249 .size = 32 * 4 * KiB, 250 .mpc = -1, 251 .mrindex = 1, 252 }, { 253 /* We don't model QSPI flash yet; for now expose it as simple ROM */ 254 .name = "QSPI", 255 .base = 0x28000000, 256 .size = 8 * MiB, 257 .mpc = 1, 258 .mrindex = 2, 259 .flags = IS_ROM, 260 }, { 261 .name = "DDR", 262 .base = 0x60000000, 263 .size = MPS3_DDR_SIZE, 264 .mpc = 2, 265 .mrindex = -1, 266 }, { 267 .name = NULL, 268 }, 269 }; 270 271 static const RAMInfo an547_raminfo[] = { { 272 .name = "itcm", 273 .base = 0x00000000, 274 .size = 512 * KiB, 275 .mpc = -1, 276 .mrindex = 0, 277 }, { 278 .name = "sram", 279 .base = 0x01000000, 280 .size = 2 * MiB, 281 .mpc = 0, 282 .mrindex = 1, 283 }, { 284 .name = "dtcm", 285 .base = 0x20000000, 286 .size = 4 * 128 * KiB, 287 .mpc = -1, 288 .mrindex = 2, 289 }, { 290 .name = "sram 2", 291 .base = 0x21000000, 292 .size = 4 * MiB, 293 .mpc = -1, 294 .mrindex = 3, 295 }, { 296 /* We don't model QSPI flash yet; for now expose it as simple ROM */ 297 .name = "QSPI", 298 .base = 0x28000000, 299 .size = 8 * MiB, 300 .mpc = 1, 301 .mrindex = 4, 302 .flags = IS_ROM, 303 }, { 304 .name = "DDR", 305 .base = 0x60000000, 306 .size = MPS3_DDR_SIZE, 307 .mpc = 2, 308 .mrindex = -1, 309 }, { 310 .name = NULL, 311 }, 312 }; 313 314 static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc) 315 { 316 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 317 const RAMInfo *p; 318 const RAMInfo *found = NULL; 319 320 for (p = mmc->raminfo; p->name; p++) { 321 if (p->mpc == mpc && !(p->flags & IS_ALIAS)) { 322 /* There should only be one entry in the array for this MPC */ 323 g_assert(!found); 324 found = p; 325 } 326 } 327 /* if raminfo array doesn't have an entry for each MPC this is a bug */ 328 assert(found); 329 return found; 330 } 331 332 static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms, 333 const RAMInfo *raminfo) 334 { 335 /* Return an initialized MemoryRegion for the RAMInfo. */ 336 MemoryRegion *ram; 337 338 if (raminfo->mrindex < 0) { 339 /* Means this RAMInfo is for QEMU's "system memory" */ 340 MachineState *machine = MACHINE(mms); 341 assert(!(raminfo->flags & IS_ROM)); 342 return machine->ram; 343 } 344 345 assert(raminfo->mrindex < MPS2TZ_RAM_MAX); 346 ram = &mms->ram[raminfo->mrindex]; 347 348 memory_region_init_ram(ram, NULL, raminfo->name, 349 raminfo->size, &error_fatal); 350 if (raminfo->flags & IS_ROM) { 351 memory_region_set_readonly(ram, true); 352 } 353 return ram; 354 } 355 356 /* Create an alias of an entire original MemoryRegion @orig 357 * located at @base in the memory map. 358 */ 359 static void make_ram_alias(MemoryRegion *mr, const char *name, 360 MemoryRegion *orig, hwaddr base) 361 { 362 memory_region_init_alias(mr, NULL, name, orig, 0, 363 memory_region_size(orig)); 364 memory_region_add_subregion(get_system_memory(), base, mr); 365 } 366 367 static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) 368 { 369 /* 370 * Return a qemu_irq which will signal IRQ n to all CPUs in the 371 * SSE. The irqno should be as the CPU sees it, so the first 372 * external-to-the-SSE interrupt is 32. 373 */ 374 MachineClass *mc = MACHINE_GET_CLASS(mms); 375 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 376 377 assert(irqno >= 32 && irqno < (mmc->numirq + 32)); 378 379 /* 380 * Convert from "CPU irq number" (as listed in the FPGA image 381 * documentation) to the SSE external-interrupt number. 382 */ 383 irqno -= 32; 384 385 if (mc->max_cpus > 1) { 386 return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); 387 } else { 388 return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno); 389 } 390 } 391 392 /* Most of the devices in the AN505 FPGA image sit behind 393 * Peripheral Protection Controllers. These data structures 394 * define the layout of which devices sit behind which PPCs. 395 * The devfn for each port is a function which creates, configures 396 * and initializes the device, returning the MemoryRegion which 397 * needs to be plugged into the downstream end of the PPC port. 398 */ 399 typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, 400 const char *name, hwaddr size, 401 const int *irqs); 402 403 typedef struct PPCPortInfo { 404 const char *name; 405 MakeDevFn *devfn; 406 void *opaque; 407 hwaddr addr; 408 hwaddr size; 409 int irqs[3]; /* currently no device needs more IRQ lines than this */ 410 } PPCPortInfo; 411 412 typedef struct PPCInfo { 413 const char *name; 414 PPCPortInfo ports[TZ_NUM_PORTS]; 415 } PPCInfo; 416 417 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, 418 void *opaque, 419 const char *name, hwaddr size, 420 const int *irqs) 421 { 422 /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, 423 * and return a pointer to its MemoryRegion. 424 */ 425 UnimplementedDeviceState *uds = opaque; 426 427 object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE); 428 qdev_prop_set_string(DEVICE(uds), "name", name); 429 qdev_prop_set_uint64(DEVICE(uds), "size", size); 430 sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); 431 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); 432 } 433 434 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, 435 const char *name, hwaddr size, 436 const int *irqs) 437 { 438 /* The irq[] array is tx, rx, combined, in that order */ 439 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 440 CMSDKAPBUART *uart = opaque; 441 int i = uart - &mms->uart[0]; 442 SysBusDevice *s; 443 DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); 444 445 object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART); 446 qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); 447 qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->apb_periph_frq); 448 sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); 449 s = SYS_BUS_DEVICE(uart); 450 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 451 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); 452 sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); 453 sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); 454 sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2])); 455 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); 456 } 457 458 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, 459 const char *name, hwaddr size, 460 const int *irqs) 461 { 462 MPS2SCC *scc = opaque; 463 DeviceState *sccdev; 464 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 465 uint32_t i; 466 467 object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); 468 sccdev = DEVICE(scc); 469 qdev_prop_set_uint32(sccdev, "scc-cfg0", mms->remap ? 1 : 0); 470 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); 471 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); 472 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); 473 qdev_prop_set_uint32(sccdev, "len-oscclk", mmc->len_oscclk); 474 for (i = 0; i < mmc->len_oscclk; i++) { 475 g_autofree char *propname = g_strdup_printf("oscclk[%u]", i); 476 qdev_prop_set_uint32(sccdev, propname, mmc->oscclk[i]); 477 } 478 sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); 479 return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); 480 } 481 482 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, 483 const char *name, hwaddr size, 484 const int *irqs) 485 { 486 MPS2FPGAIO *fpgaio = opaque; 487 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 488 489 object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO); 490 qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds); 491 qdev_prop_set_bit(DEVICE(fpgaio), "has-switches", mmc->fpgaio_has_switches); 492 qdev_prop_set_bit(DEVICE(fpgaio), "has-dbgctrl", mmc->fpgaio_has_dbgctrl); 493 sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); 494 return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); 495 } 496 497 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, 498 const char *name, hwaddr size, 499 const int *irqs) 500 { 501 SysBusDevice *s; 502 NICInfo *nd = &nd_table[0]; 503 504 /* In hardware this is a LAN9220; the LAN9118 is software compatible 505 * except that it doesn't support the checksum-offload feature. 506 */ 507 qemu_check_nic_model(nd, "lan9118"); 508 mms->lan9118 = qdev_new(TYPE_LAN9118); 509 qdev_set_nic_properties(mms->lan9118, nd); 510 511 s = SYS_BUS_DEVICE(mms->lan9118); 512 sysbus_realize_and_unref(s, &error_fatal); 513 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 514 return sysbus_mmio_get_region(s, 0); 515 } 516 517 static MemoryRegion *make_eth_usb(MPS2TZMachineState *mms, void *opaque, 518 const char *name, hwaddr size, 519 const int *irqs) 520 { 521 /* 522 * The AN524 makes the ethernet and USB share a PPC port. 523 * irqs[] is the ethernet IRQ. 524 */ 525 SysBusDevice *s; 526 NICInfo *nd = &nd_table[0]; 527 528 memory_region_init(&mms->eth_usb_container, OBJECT(mms), 529 "mps2-tz-eth-usb-container", 0x200000); 530 531 /* 532 * In hardware this is a LAN9220; the LAN9118 is software compatible 533 * except that it doesn't support the checksum-offload feature. 534 */ 535 qemu_check_nic_model(nd, "lan9118"); 536 mms->lan9118 = qdev_new(TYPE_LAN9118); 537 qdev_set_nic_properties(mms->lan9118, nd); 538 539 s = SYS_BUS_DEVICE(mms->lan9118); 540 sysbus_realize_and_unref(s, &error_fatal); 541 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 542 543 memory_region_add_subregion(&mms->eth_usb_container, 544 0, sysbus_mmio_get_region(s, 0)); 545 546 /* The USB OTG controller is an ISP1763; we don't have a model of it. */ 547 object_initialize_child(OBJECT(mms), "usb-otg", 548 &mms->usb, TYPE_UNIMPLEMENTED_DEVICE); 549 qdev_prop_set_string(DEVICE(&mms->usb), "name", "usb-otg"); 550 qdev_prop_set_uint64(DEVICE(&mms->usb), "size", 0x100000); 551 s = SYS_BUS_DEVICE(&mms->usb); 552 sysbus_realize(s, &error_fatal); 553 554 memory_region_add_subregion(&mms->eth_usb_container, 555 0x100000, sysbus_mmio_get_region(s, 0)); 556 557 return &mms->eth_usb_container; 558 } 559 560 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, 561 const char *name, hwaddr size, 562 const int *irqs) 563 { 564 TZMPC *mpc = opaque; 565 int i = mpc - &mms->mpc[0]; 566 MemoryRegion *upstream; 567 const RAMInfo *raminfo = find_raminfo_for_mpc(mms, i); 568 MemoryRegion *ram = mr_for_raminfo(mms, raminfo); 569 570 object_initialize_child(OBJECT(mms), name, mpc, TYPE_TZ_MPC); 571 object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ram), 572 &error_fatal); 573 sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); 574 /* Map the upstream end of the MPC into system memory */ 575 upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); 576 memory_region_add_subregion(get_system_memory(), raminfo->base, upstream); 577 /* and connect its interrupt to the IoTKit */ 578 qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, 579 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 580 "mpcexp_status", i)); 581 582 /* Return the register interface MR for our caller to map behind the PPC */ 583 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); 584 } 585 586 static hwaddr boot_mem_base(MPS2TZMachineState *mms) 587 { 588 /* 589 * Return the canonical address of the block which will be mapped 590 * at address 0x0 (i.e. where the vector table is). 591 * This is usually 0, but if the AN524 alternate memory map is 592 * enabled it will be the base address of the QSPI block. 593 */ 594 return mms->remap ? 0x28000000 : 0; 595 } 596 597 static void remap_memory(MPS2TZMachineState *mms, int map) 598 { 599 /* 600 * Remap the memory for the AN524. 'map' is the value of 601 * SCC CFG_REG0 bit 0, i.e. 0 for the default map and 1 602 * for the "option 1" mapping where QSPI is at address 0. 603 * 604 * Effectively we need to swap around the "upstream" ends of 605 * MPC 0 and MPC 1. 606 */ 607 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 608 int i; 609 610 if (mmc->fpga_type != FPGA_AN524) { 611 return; 612 } 613 614 memory_region_transaction_begin(); 615 for (i = 0; i < 2; i++) { 616 TZMPC *mpc = &mms->mpc[i]; 617 MemoryRegion *upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); 618 hwaddr addr = (i ^ map) ? 0x28000000 : 0; 619 620 memory_region_set_address(upstream, addr); 621 } 622 memory_region_transaction_commit(); 623 } 624 625 static void remap_irq_fn(void *opaque, int n, int level) 626 { 627 MPS2TZMachineState *mms = opaque; 628 629 remap_memory(mms, level); 630 } 631 632 static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, 633 const char *name, hwaddr size, 634 const int *irqs) 635 { 636 /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */ 637 PL080State *dma = opaque; 638 int i = dma - &mms->dma[0]; 639 SysBusDevice *s; 640 char *mscname = g_strdup_printf("%s-msc", name); 641 TZMSC *msc = &mms->msc[i]; 642 DeviceState *iotkitdev = DEVICE(&mms->iotkit); 643 MemoryRegion *msc_upstream; 644 MemoryRegion *msc_downstream; 645 646 /* 647 * Each DMA device is a PL081 whose transaction master interface 648 * is guarded by a Master Security Controller. The downstream end of 649 * the MSC connects to the IoTKit AHB Slave Expansion port, so the 650 * DMA devices can see all devices and memory that the CPU does. 651 */ 652 object_initialize_child(OBJECT(mms), mscname, msc, TYPE_TZ_MSC); 653 msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0); 654 object_property_set_link(OBJECT(msc), "downstream", 655 OBJECT(msc_downstream), &error_fatal); 656 object_property_set_link(OBJECT(msc), "idau", OBJECT(mms), &error_fatal); 657 sysbus_realize(SYS_BUS_DEVICE(msc), &error_fatal); 658 659 qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0, 660 qdev_get_gpio_in_named(iotkitdev, 661 "mscexp_status", i)); 662 qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i, 663 qdev_get_gpio_in_named(DEVICE(msc), 664 "irq_clear", 0)); 665 qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i, 666 qdev_get_gpio_in_named(DEVICE(msc), 667 "cfg_nonsec", 0)); 668 qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter), 669 ARRAY_SIZE(mms->ppc) + i, 670 qdev_get_gpio_in_named(DEVICE(msc), 671 "cfg_sec_resp", 0)); 672 msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0); 673 674 object_initialize_child(OBJECT(mms), name, dma, TYPE_PL081); 675 object_property_set_link(OBJECT(dma), "downstream", OBJECT(msc_upstream), 676 &error_fatal); 677 sysbus_realize(SYS_BUS_DEVICE(dma), &error_fatal); 678 679 s = SYS_BUS_DEVICE(dma); 680 /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ 681 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 682 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); 683 sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqs[2])); 684 685 g_free(mscname); 686 return sysbus_mmio_get_region(s, 0); 687 } 688 689 static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, 690 const char *name, hwaddr size, 691 const int *irqs) 692 { 693 /* 694 * The AN505 has five PL022 SPI controllers. 695 * One of these should have the LCD controller behind it; the others 696 * are connected only to the FPGA's "general purpose SPI connector" 697 * or "shield" expansion connectors. 698 * Note that if we do implement devices behind SPI, the chip select 699 * lines are set via the "MISC" register in the MPS2 FPGAIO device. 700 */ 701 PL022State *spi = opaque; 702 SysBusDevice *s; 703 704 object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022); 705 sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal); 706 s = SYS_BUS_DEVICE(spi); 707 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 708 return sysbus_mmio_get_region(s, 0); 709 } 710 711 static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, 712 const char *name, hwaddr size, 713 const int *irqs) 714 { 715 ArmSbconI2CState *i2c = opaque; 716 SysBusDevice *s; 717 718 object_initialize_child(OBJECT(mms), name, i2c, TYPE_ARM_SBCON_I2C); 719 s = SYS_BUS_DEVICE(i2c); 720 sysbus_realize(s, &error_fatal); 721 return sysbus_mmio_get_region(s, 0); 722 } 723 724 static MemoryRegion *make_rtc(MPS2TZMachineState *mms, void *opaque, 725 const char *name, hwaddr size, 726 const int *irqs) 727 { 728 PL031State *pl031 = opaque; 729 SysBusDevice *s; 730 731 object_initialize_child(OBJECT(mms), name, pl031, TYPE_PL031); 732 s = SYS_BUS_DEVICE(pl031); 733 sysbus_realize(s, &error_fatal); 734 /* 735 * The board docs don't give an IRQ number for the PL031, so 736 * presumably it is not connected. 737 */ 738 return sysbus_mmio_get_region(s, 0); 739 } 740 741 static void create_non_mpc_ram(MPS2TZMachineState *mms) 742 { 743 /* 744 * Handle the RAMs which are either not behind MPCs or which are 745 * aliases to another MPC. 746 */ 747 const RAMInfo *p; 748 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 749 750 for (p = mmc->raminfo; p->name; p++) { 751 if (p->flags & IS_ALIAS) { 752 SysBusDevice *mpc_sbd = SYS_BUS_DEVICE(&mms->mpc[p->mpc]); 753 MemoryRegion *upstream = sysbus_mmio_get_region(mpc_sbd, 1); 754 make_ram_alias(&mms->ram[p->mrindex], p->name, upstream, p->base); 755 } else if (p->mpc == -1) { 756 /* RAM not behind an MPC */ 757 MemoryRegion *mr = mr_for_raminfo(mms, p); 758 memory_region_add_subregion(get_system_memory(), p->base, mr); 759 } 760 } 761 } 762 763 static uint32_t boot_ram_size(MPS2TZMachineState *mms) 764 { 765 /* Return the size of the RAM block at guest address zero */ 766 const RAMInfo *p; 767 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 768 769 for (p = mmc->raminfo; p->name; p++) { 770 if (p->base == boot_mem_base(mms)) { 771 return p->size; 772 } 773 } 774 g_assert_not_reached(); 775 } 776 777 static void mps2tz_common_init(MachineState *machine) 778 { 779 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); 780 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 781 MachineClass *mc = MACHINE_GET_CLASS(machine); 782 MemoryRegion *system_memory = get_system_memory(); 783 DeviceState *iotkitdev; 784 DeviceState *dev_splitter; 785 const PPCInfo *ppcs; 786 int num_ppcs; 787 int i; 788 789 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { 790 error_report("This board can only be used with CPU %s", 791 mc->default_cpu_type); 792 exit(1); 793 } 794 795 if (machine->ram_size != mc->default_ram_size) { 796 char *sz = size_to_str(mc->default_ram_size); 797 error_report("Invalid RAM size, should be %s", sz); 798 g_free(sz); 799 exit(EXIT_FAILURE); 800 } 801 802 /* These clocks don't need migration because they are fixed-frequency */ 803 mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); 804 clock_set_hz(mms->sysclk, mmc->sysclk_frq); 805 mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); 806 clock_set_hz(mms->s32kclk, S32KCLK_FRQ); 807 808 object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit, 809 mmc->armsse_type); 810 iotkitdev = DEVICE(&mms->iotkit); 811 object_property_set_link(OBJECT(&mms->iotkit), "memory", 812 OBJECT(system_memory), &error_abort); 813 qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); 814 qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor); 815 qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); 816 qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); 817 sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); 818 819 /* 820 * If this board has more than one CPU, then we need to create splitters 821 * to feed the IRQ inputs for each CPU in the SSE from each device in the 822 * board. If there is only one CPU, we can just wire the device IRQ 823 * directly to the SSE's IRQ input. 824 */ 825 assert(mmc->numirq <= MPS2TZ_NUMIRQ_MAX); 826 if (mc->max_cpus > 1) { 827 for (i = 0; i < mmc->numirq; i++) { 828 char *name = g_strdup_printf("mps2-irq-splitter%d", i); 829 SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; 830 831 object_initialize_child_with_props(OBJECT(machine), name, 832 splitter, sizeof(*splitter), 833 TYPE_SPLIT_IRQ, &error_fatal, 834 NULL); 835 g_free(name); 836 837 object_property_set_int(OBJECT(splitter), "num-lines", 2, 838 &error_fatal); 839 qdev_realize(DEVICE(splitter), NULL, &error_fatal); 840 qdev_connect_gpio_out(DEVICE(splitter), 0, 841 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 842 "EXP_IRQ", i)); 843 qdev_connect_gpio_out(DEVICE(splitter), 1, 844 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 845 "EXP_CPU1_IRQ", i)); 846 } 847 } 848 849 /* The sec_resp_cfg output from the IoTKit must be split into multiple 850 * lines, one for each of the PPCs we create here, plus one per MSC. 851 */ 852 object_initialize_child(OBJECT(machine), "sec-resp-splitter", 853 &mms->sec_resp_splitter, TYPE_SPLIT_IRQ); 854 object_property_set_int(OBJECT(&mms->sec_resp_splitter), "num-lines", 855 ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc), 856 &error_fatal); 857 qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal); 858 dev_splitter = DEVICE(&mms->sec_resp_splitter); 859 qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, 860 qdev_get_gpio_in(dev_splitter, 0)); 861 862 /* 863 * The IoTKit sets up much of the memory layout, including 864 * the aliases between secure and non-secure regions in the 865 * address space, and also most of the devices in the system. 866 * The FPGA itself contains various RAMs and some additional devices. 867 * The FPGA images have an odd combination of different RAMs, 868 * because in hardware they are different implementations and 869 * connected to different buses, giving varying performance/size 870 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily 871 * call the largest lump our "system memory". 872 */ 873 874 /* 875 * The overflow IRQs for all UARTs are ORed together. 876 * Tx, Rx and "combined" IRQs are sent to the NVIC separately. 877 * Create the OR gate for this: it has one input for the TX overflow 878 * and one for the RX overflow for each UART we might have. 879 * (If the board has fewer than the maximum possible number of UARTs 880 * those inputs are never wired up and are treated as always-zero.) 881 */ 882 object_initialize_child(OBJECT(mms), "uart-irq-orgate", 883 &mms->uart_irq_orgate, TYPE_OR_IRQ); 884 object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", 885 2 * ARRAY_SIZE(mms->uart), 886 &error_fatal); 887 qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); 888 qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, 889 get_sse_irq_in(mms, mmc->uart_overflow_irq)); 890 891 /* Most of the devices in the FPGA are behind Peripheral Protection 892 * Controllers. The required order for initializing things is: 893 * + initialize the PPC 894 * + initialize, configure and realize downstream devices 895 * + connect downstream device MemoryRegions to the PPC 896 * + realize the PPC 897 * + map the PPC's MemoryRegions to the places in the address map 898 * where the downstream devices should appear 899 * + wire up the PPC's control lines to the IoTKit object 900 */ 901 902 const PPCInfo an505_ppcs[] = { { 903 .name = "apb_ppcexp0", 904 .ports = { 905 { "ssram-0-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, 906 { "ssram-1-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, 907 { "ssram-2-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, 908 }, 909 }, { 910 .name = "apb_ppcexp1", 911 .ports = { 912 { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000, { 51 } }, 913 { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000, { 52 } }, 914 { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000, { 53 } }, 915 { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000, { 54 } }, 916 { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000, { 55 } }, 917 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000, { 32, 33, 42 } }, 918 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000, { 34, 35, 43 } }, 919 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000, { 36, 37, 44 } }, 920 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000, { 38, 39, 45 } }, 921 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000, { 40, 41, 46 } }, 922 { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 }, 923 { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 }, 924 { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 }, 925 { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000 }, 926 }, 927 }, { 928 .name = "apb_ppcexp2", 929 .ports = { 930 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, 931 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 932 0x40301000, 0x1000 }, 933 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, 934 }, 935 }, { 936 .name = "ahb_ppcexp0", 937 .ports = { 938 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, 939 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, 940 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, 941 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, 942 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, 943 { "eth", make_eth_dev, NULL, 0x42000000, 0x100000, { 48 } }, 944 }, 945 }, { 946 .name = "ahb_ppcexp1", 947 .ports = { 948 { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000, { 58, 56, 57 } }, 949 { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000, { 61, 59, 60 } }, 950 { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000, { 64, 62, 63 } }, 951 { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000, { 67, 65, 66 } }, 952 }, 953 }, 954 }; 955 956 const PPCInfo an524_ppcs[] = { { 957 .name = "apb_ppcexp0", 958 .ports = { 959 { "bram-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, 960 { "qspi-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, 961 { "ddr-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, 962 }, 963 }, { 964 .name = "apb_ppcexp1", 965 .ports = { 966 { "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000 }, 967 { "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000 }, 968 { "spi0", make_spi, &mms->spi[0], 0x41202000, 0x1000, { 52 } }, 969 { "spi1", make_spi, &mms->spi[1], 0x41203000, 0x1000, { 53 } }, 970 { "spi2", make_spi, &mms->spi[2], 0x41204000, 0x1000, { 54 } }, 971 { "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000 }, 972 { "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000 }, 973 { /* port 7 reserved */ }, 974 { "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000 }, 975 }, 976 }, { 977 .name = "apb_ppcexp2", 978 .ports = { 979 { "scc", make_scc, &mms->scc, 0x41300000, 0x1000 }, 980 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 981 0x41301000, 0x1000 }, 982 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x41302000, 0x1000 }, 983 { "uart0", make_uart, &mms->uart[0], 0x41303000, 0x1000, { 32, 33, 42 } }, 984 { "uart1", make_uart, &mms->uart[1], 0x41304000, 0x1000, { 34, 35, 43 } }, 985 { "uart2", make_uart, &mms->uart[2], 0x41305000, 0x1000, { 36, 37, 44 } }, 986 { "uart3", make_uart, &mms->uart[3], 0x41306000, 0x1000, { 38, 39, 45 } }, 987 { "uart4", make_uart, &mms->uart[4], 0x41307000, 0x1000, { 40, 41, 46 } }, 988 { "uart5", make_uart, &mms->uart[5], 0x41308000, 0x1000, { 124, 125, 126 } }, 989 990 { /* port 9 reserved */ }, 991 { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 }, 992 { "rtc", make_rtc, &mms->rtc, 0x4130b000, 0x1000 }, 993 }, 994 }, { 995 .name = "ahb_ppcexp0", 996 .ports = { 997 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 }, 998 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, 999 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, 1000 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, 1001 { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 48 } }, 1002 }, 1003 }, 1004 }; 1005 1006 const PPCInfo an547_ppcs[] = { { 1007 .name = "apb_ppcexp0", 1008 .ports = { 1009 { "ssram-mpc", make_mpc, &mms->mpc[0], 0x57000000, 0x1000 }, 1010 { "qspi-mpc", make_mpc, &mms->mpc[1], 0x57001000, 0x1000 }, 1011 { "ddr-mpc", make_mpc, &mms->mpc[2], 0x57002000, 0x1000 }, 1012 }, 1013 }, { 1014 .name = "apb_ppcexp1", 1015 .ports = { 1016 { "i2c0", make_i2c, &mms->i2c[0], 0x49200000, 0x1000 }, 1017 { "i2c1", make_i2c, &mms->i2c[1], 0x49201000, 0x1000 }, 1018 { "spi0", make_spi, &mms->spi[0], 0x49202000, 0x1000, { 53 } }, 1019 { "spi1", make_spi, &mms->spi[1], 0x49203000, 0x1000, { 54 } }, 1020 { "spi2", make_spi, &mms->spi[2], 0x49204000, 0x1000, { 55 } }, 1021 { "i2c2", make_i2c, &mms->i2c[2], 0x49205000, 0x1000 }, 1022 { "i2c3", make_i2c, &mms->i2c[3], 0x49206000, 0x1000 }, 1023 { /* port 7 reserved */ }, 1024 { "i2c4", make_i2c, &mms->i2c[4], 0x49208000, 0x1000 }, 1025 }, 1026 }, { 1027 .name = "apb_ppcexp2", 1028 .ports = { 1029 { "scc", make_scc, &mms->scc, 0x49300000, 0x1000 }, 1030 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 0x49301000, 0x1000 }, 1031 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x49302000, 0x1000 }, 1032 { "uart0", make_uart, &mms->uart[0], 0x49303000, 0x1000, { 33, 34, 43 } }, 1033 { "uart1", make_uart, &mms->uart[1], 0x49304000, 0x1000, { 35, 36, 44 } }, 1034 { "uart2", make_uart, &mms->uart[2], 0x49305000, 0x1000, { 37, 38, 45 } }, 1035 { "uart3", make_uart, &mms->uart[3], 0x49306000, 0x1000, { 39, 40, 46 } }, 1036 { "uart4", make_uart, &mms->uart[4], 0x49307000, 0x1000, { 41, 42, 47 } }, 1037 { "uart5", make_uart, &mms->uart[5], 0x49308000, 0x1000, { 125, 126, 127 } }, 1038 1039 { /* port 9 reserved */ }, 1040 { "clcd", make_unimp_dev, &mms->cldc, 0x4930a000, 0x1000 }, 1041 { "rtc", make_rtc, &mms->rtc, 0x4930b000, 0x1000 }, 1042 }, 1043 }, { 1044 .name = "ahb_ppcexp0", 1045 .ports = { 1046 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 }, 1047 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, 1048 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, 1049 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, 1050 { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 49 } }, 1051 }, 1052 }, 1053 }; 1054 1055 switch (mmc->fpga_type) { 1056 case FPGA_AN505: 1057 case FPGA_AN521: 1058 ppcs = an505_ppcs; 1059 num_ppcs = ARRAY_SIZE(an505_ppcs); 1060 break; 1061 case FPGA_AN524: 1062 ppcs = an524_ppcs; 1063 num_ppcs = ARRAY_SIZE(an524_ppcs); 1064 break; 1065 case FPGA_AN547: 1066 ppcs = an547_ppcs; 1067 num_ppcs = ARRAY_SIZE(an547_ppcs); 1068 break; 1069 default: 1070 g_assert_not_reached(); 1071 } 1072 1073 for (i = 0; i < num_ppcs; i++) { 1074 const PPCInfo *ppcinfo = &ppcs[i]; 1075 TZPPC *ppc = &mms->ppc[i]; 1076 DeviceState *ppcdev; 1077 int port; 1078 char *gpioname; 1079 1080 object_initialize_child(OBJECT(machine), ppcinfo->name, ppc, 1081 TYPE_TZ_PPC); 1082 ppcdev = DEVICE(ppc); 1083 1084 for (port = 0; port < TZ_NUM_PORTS; port++) { 1085 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 1086 MemoryRegion *mr; 1087 char *portname; 1088 1089 if (!pinfo->devfn) { 1090 continue; 1091 } 1092 1093 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size, 1094 pinfo->irqs); 1095 portname = g_strdup_printf("port[%d]", port); 1096 object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), 1097 &error_fatal); 1098 g_free(portname); 1099 } 1100 1101 sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal); 1102 1103 for (port = 0; port < TZ_NUM_PORTS; port++) { 1104 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 1105 1106 if (!pinfo->devfn) { 1107 continue; 1108 } 1109 sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); 1110 1111 gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); 1112 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 1113 qdev_get_gpio_in_named(ppcdev, 1114 "cfg_nonsec", 1115 port)); 1116 g_free(gpioname); 1117 gpioname = g_strdup_printf("%s_ap", ppcinfo->name); 1118 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 1119 qdev_get_gpio_in_named(ppcdev, 1120 "cfg_ap", port)); 1121 g_free(gpioname); 1122 } 1123 1124 gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); 1125 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 1126 qdev_get_gpio_in_named(ppcdev, 1127 "irq_enable", 0)); 1128 g_free(gpioname); 1129 gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); 1130 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 1131 qdev_get_gpio_in_named(ppcdev, 1132 "irq_clear", 0)); 1133 g_free(gpioname); 1134 gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); 1135 qdev_connect_gpio_out_named(ppcdev, "irq", 0, 1136 qdev_get_gpio_in_named(iotkitdev, 1137 gpioname, 0)); 1138 g_free(gpioname); 1139 1140 qdev_connect_gpio_out(dev_splitter, i, 1141 qdev_get_gpio_in_named(ppcdev, 1142 "cfg_sec_resp", 0)); 1143 } 1144 1145 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); 1146 1147 if (mmc->fpga_type == FPGA_AN547) { 1148 create_unimplemented_device("U55 timing adapter 0", 0x48102000, 0x1000); 1149 create_unimplemented_device("U55 timing adapter 1", 0x48103000, 0x1000); 1150 } 1151 1152 create_non_mpc_ram(mms); 1153 1154 if (mmc->fpga_type == FPGA_AN524) { 1155 /* 1156 * Connect the line from the SCC so that we can remap when the 1157 * guest updates that register. 1158 */ 1159 mms->remap_irq = qemu_allocate_irq(remap_irq_fn, mms, 0); 1160 qdev_connect_gpio_out_named(DEVICE(&mms->scc), "remap", 0, 1161 mms->remap_irq); 1162 } 1163 1164 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 1165 boot_ram_size(mms)); 1166 } 1167 1168 static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, 1169 int *iregion, bool *exempt, bool *ns, bool *nsc) 1170 { 1171 /* 1172 * The MPS2 TZ FPGA images have IDAUs in them which are connected to 1173 * the Master Security Controllers. Thes have the same logic as 1174 * is used by the IoTKit for the IDAU connected to the CPU, except 1175 * that MSCs don't care about the NSC attribute. 1176 */ 1177 int region = extract32(address, 28, 4); 1178 1179 *ns = !(region & 1); 1180 *nsc = false; 1181 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 1182 *exempt = (address & 0xeff00000) == 0xe0000000; 1183 *iregion = region; 1184 } 1185 1186 static char *mps2_get_remap(Object *obj, Error **errp) 1187 { 1188 MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); 1189 const char *val = mms->remap ? "QSPI" : "BRAM"; 1190 return g_strdup(val); 1191 } 1192 1193 static void mps2_set_remap(Object *obj, const char *value, Error **errp) 1194 { 1195 MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); 1196 1197 if (!strcmp(value, "BRAM")) { 1198 mms->remap = false; 1199 } else if (!strcmp(value, "QSPI")) { 1200 mms->remap = true; 1201 } else { 1202 error_setg(errp, "Invalid remap value"); 1203 error_append_hint(errp, "Valid values are BRAM and QSPI.\n"); 1204 } 1205 } 1206 1207 static void mps2_machine_reset(MachineState *machine) 1208 { 1209 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); 1210 1211 /* 1212 * Set the initial memory mapping before triggering the reset of 1213 * the rest of the system, so that the guest image loader and CPU 1214 * reset see the correct mapping. 1215 */ 1216 remap_memory(mms, mms->remap); 1217 qemu_devices_reset(); 1218 } 1219 1220 static void mps2tz_class_init(ObjectClass *oc, void *data) 1221 { 1222 MachineClass *mc = MACHINE_CLASS(oc); 1223 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); 1224 1225 mc->init = mps2tz_common_init; 1226 mc->reset = mps2_machine_reset; 1227 iic->check = mps2_tz_idau_check; 1228 } 1229 1230 static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc) 1231 { 1232 /* 1233 * Set mc->default_ram_size and default_ram_id from the 1234 * information in mmc->raminfo. 1235 */ 1236 MachineClass *mc = MACHINE_CLASS(mmc); 1237 const RAMInfo *p; 1238 1239 for (p = mmc->raminfo; p->name; p++) { 1240 if (p->mrindex < 0) { 1241 /* Found the entry for "system memory" */ 1242 mc->default_ram_size = p->size; 1243 mc->default_ram_id = p->name; 1244 return; 1245 } 1246 } 1247 g_assert_not_reached(); 1248 } 1249 1250 static void mps2tz_an505_class_init(ObjectClass *oc, void *data) 1251 { 1252 MachineClass *mc = MACHINE_CLASS(oc); 1253 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1254 1255 mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; 1256 mc->default_cpus = 1; 1257 mc->min_cpus = mc->default_cpus; 1258 mc->max_cpus = mc->default_cpus; 1259 mmc->fpga_type = FPGA_AN505; 1260 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 1261 mmc->scc_id = 0x41045050; 1262 mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ 1263 mmc->apb_periph_frq = mmc->sysclk_frq; 1264 mmc->oscclk = an505_oscclk; 1265 mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); 1266 mmc->fpgaio_num_leds = 2; 1267 mmc->fpgaio_has_switches = false; 1268 mmc->fpgaio_has_dbgctrl = false; 1269 mmc->numirq = 92; 1270 mmc->uart_overflow_irq = 47; 1271 mmc->init_svtor = 0x10000000; 1272 mmc->raminfo = an505_raminfo; 1273 mmc->armsse_type = TYPE_IOTKIT; 1274 mps2tz_set_default_ram_info(mmc); 1275 } 1276 1277 static void mps2tz_an521_class_init(ObjectClass *oc, void *data) 1278 { 1279 MachineClass *mc = MACHINE_CLASS(oc); 1280 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1281 1282 mc->desc = "ARM MPS2 with AN521 FPGA image for dual Cortex-M33"; 1283 mc->default_cpus = 2; 1284 mc->min_cpus = mc->default_cpus; 1285 mc->max_cpus = mc->default_cpus; 1286 mmc->fpga_type = FPGA_AN521; 1287 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 1288 mmc->scc_id = 0x41045210; 1289 mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ 1290 mmc->apb_periph_frq = mmc->sysclk_frq; 1291 mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */ 1292 mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); 1293 mmc->fpgaio_num_leds = 2; 1294 mmc->fpgaio_has_switches = false; 1295 mmc->fpgaio_has_dbgctrl = false; 1296 mmc->numirq = 92; 1297 mmc->uart_overflow_irq = 47; 1298 mmc->init_svtor = 0x10000000; 1299 mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */ 1300 mmc->armsse_type = TYPE_SSE200; 1301 mps2tz_set_default_ram_info(mmc); 1302 } 1303 1304 static void mps3tz_an524_class_init(ObjectClass *oc, void *data) 1305 { 1306 MachineClass *mc = MACHINE_CLASS(oc); 1307 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1308 1309 mc->desc = "ARM MPS3 with AN524 FPGA image for dual Cortex-M33"; 1310 mc->default_cpus = 2; 1311 mc->min_cpus = mc->default_cpus; 1312 mc->max_cpus = mc->default_cpus; 1313 mmc->fpga_type = FPGA_AN524; 1314 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 1315 mmc->scc_id = 0x41045240; 1316 mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */ 1317 mmc->apb_periph_frq = mmc->sysclk_frq; 1318 mmc->oscclk = an524_oscclk; 1319 mmc->len_oscclk = ARRAY_SIZE(an524_oscclk); 1320 mmc->fpgaio_num_leds = 10; 1321 mmc->fpgaio_has_switches = true; 1322 mmc->fpgaio_has_dbgctrl = false; 1323 mmc->numirq = 95; 1324 mmc->uart_overflow_irq = 47; 1325 mmc->init_svtor = 0x10000000; 1326 mmc->raminfo = an524_raminfo; 1327 mmc->armsse_type = TYPE_SSE200; 1328 mps2tz_set_default_ram_info(mmc); 1329 1330 object_class_property_add_str(oc, "remap", mps2_get_remap, mps2_set_remap); 1331 object_class_property_set_description(oc, "remap", 1332 "Set memory mapping. Valid values " 1333 "are BRAM (default) and QSPI."); 1334 } 1335 1336 static void mps3tz_an547_class_init(ObjectClass *oc, void *data) 1337 { 1338 MachineClass *mc = MACHINE_CLASS(oc); 1339 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1340 1341 mc->desc = "ARM MPS3 with AN547 FPGA image for Cortex-M55"; 1342 mc->default_cpus = 1; 1343 mc->min_cpus = mc->default_cpus; 1344 mc->max_cpus = mc->default_cpus; 1345 mmc->fpga_type = FPGA_AN547; 1346 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m55"); 1347 mmc->scc_id = 0x41055470; 1348 mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */ 1349 mmc->apb_periph_frq = 25 * 1000 * 1000; /* 25MHz */ 1350 mmc->oscclk = an524_oscclk; /* same as AN524 */ 1351 mmc->len_oscclk = ARRAY_SIZE(an524_oscclk); 1352 mmc->fpgaio_num_leds = 10; 1353 mmc->fpgaio_has_switches = true; 1354 mmc->fpgaio_has_dbgctrl = true; 1355 mmc->numirq = 96; 1356 mmc->uart_overflow_irq = 48; 1357 mmc->init_svtor = 0x00000000; 1358 mmc->raminfo = an547_raminfo; 1359 mmc->armsse_type = TYPE_SSE300; 1360 mps2tz_set_default_ram_info(mmc); 1361 } 1362 1363 static const TypeInfo mps2tz_info = { 1364 .name = TYPE_MPS2TZ_MACHINE, 1365 .parent = TYPE_MACHINE, 1366 .abstract = true, 1367 .instance_size = sizeof(MPS2TZMachineState), 1368 .class_size = sizeof(MPS2TZMachineClass), 1369 .class_init = mps2tz_class_init, 1370 .interfaces = (InterfaceInfo[]) { 1371 { TYPE_IDAU_INTERFACE }, 1372 { } 1373 }, 1374 }; 1375 1376 static const TypeInfo mps2tz_an505_info = { 1377 .name = TYPE_MPS2TZ_AN505_MACHINE, 1378 .parent = TYPE_MPS2TZ_MACHINE, 1379 .class_init = mps2tz_an505_class_init, 1380 }; 1381 1382 static const TypeInfo mps2tz_an521_info = { 1383 .name = TYPE_MPS2TZ_AN521_MACHINE, 1384 .parent = TYPE_MPS2TZ_MACHINE, 1385 .class_init = mps2tz_an521_class_init, 1386 }; 1387 1388 static const TypeInfo mps3tz_an524_info = { 1389 .name = TYPE_MPS3TZ_AN524_MACHINE, 1390 .parent = TYPE_MPS2TZ_MACHINE, 1391 .class_init = mps3tz_an524_class_init, 1392 }; 1393 1394 static const TypeInfo mps3tz_an547_info = { 1395 .name = TYPE_MPS3TZ_AN547_MACHINE, 1396 .parent = TYPE_MPS2TZ_MACHINE, 1397 .class_init = mps3tz_an547_class_init, 1398 }; 1399 1400 static void mps2tz_machine_init(void) 1401 { 1402 type_register_static(&mps2tz_info); 1403 type_register_static(&mps2tz_an505_info); 1404 type_register_static(&mps2tz_an521_info); 1405 type_register_static(&mps3tz_an524_info); 1406 type_register_static(&mps3tz_an547_info); 1407 } 1408 1409 type_init(mps2tz_machine_init); 1410