1 /* 2 * ARM V2M MPS2 board emulation, trustzone aware FPGA images 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger 13 * FPGA but is otherwise the same as the 2). Since the CPU itself 14 * and most of the devices are in the FPGA, the details of the board 15 * as seen by the guest depend significantly on the FPGA image. 16 * This source file covers the following FPGA images, for TrustZone cores: 17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 18 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521 19 * 20 * Links to the TRM for the board itself and to the various Application 21 * Notes which document the FPGA images can be found here: 22 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 23 * 24 * Board TRM: 25 * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf 26 * Application Note AN505: 27 * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html 28 * Application Note AN521: 29 * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html 30 * 31 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide 32 * (ARM ECM0601256) for the details of some of the device layout: 33 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html 34 * Similarly, the AN521 uses the SSE-200, and the SSE-200 TRM defines 35 * most of the device layout: 36 * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf 37 * 38 */ 39 40 #include "qemu/osdep.h" 41 #include "qemu/units.h" 42 #include "qemu/cutils.h" 43 #include "qapi/error.h" 44 #include "qemu/error-report.h" 45 #include "hw/arm/boot.h" 46 #include "hw/arm/armv7m.h" 47 #include "hw/or-irq.h" 48 #include "hw/boards.h" 49 #include "exec/address-spaces.h" 50 #include "sysemu/sysemu.h" 51 #include "hw/misc/unimp.h" 52 #include "hw/char/cmsdk-apb-uart.h" 53 #include "hw/timer/cmsdk-apb-timer.h" 54 #include "hw/misc/mps2-scc.h" 55 #include "hw/misc/mps2-fpgaio.h" 56 #include "hw/misc/tz-mpc.h" 57 #include "hw/misc/tz-msc.h" 58 #include "hw/arm/armsse.h" 59 #include "hw/dma/pl080.h" 60 #include "hw/ssi/pl022.h" 61 #include "hw/i2c/arm_sbcon_i2c.h" 62 #include "hw/net/lan9118.h" 63 #include "net/net.h" 64 #include "hw/core/split-irq.h" 65 #include "hw/qdev-clock.h" 66 #include "qom/object.h" 67 68 #define MPS2TZ_NUMIRQ 92 69 70 typedef enum MPS2TZFPGAType { 71 FPGA_AN505, 72 FPGA_AN521, 73 } MPS2TZFPGAType; 74 75 struct MPS2TZMachineClass { 76 MachineClass parent; 77 MPS2TZFPGAType fpga_type; 78 uint32_t scc_id; 79 const char *armsse_type; 80 }; 81 82 struct MPS2TZMachineState { 83 MachineState parent; 84 85 ARMSSE iotkit; 86 MemoryRegion ssram[3]; 87 MemoryRegion ssram1_m; 88 MPS2SCC scc; 89 MPS2FPGAIO fpgaio; 90 TZPPC ppc[5]; 91 TZMPC ssram_mpc[3]; 92 PL022State spi[5]; 93 ArmSbconI2CState i2c[4]; 94 UnimplementedDeviceState i2s_audio; 95 UnimplementedDeviceState gpio[4]; 96 UnimplementedDeviceState gfx; 97 PL080State dma[4]; 98 TZMSC msc[4]; 99 CMSDKAPBUART uart[5]; 100 SplitIRQ sec_resp_splitter; 101 qemu_or_irq uart_irq_orgate; 102 DeviceState *lan9118; 103 SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ]; 104 Clock *sysclk; 105 Clock *s32kclk; 106 }; 107 108 #define TYPE_MPS2TZ_MACHINE "mps2tz" 109 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") 110 #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") 111 112 OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) 113 114 /* Main SYSCLK frequency in Hz */ 115 #define SYSCLK_FRQ 20000000 116 /* Slow 32Khz S32KCLK frequency in Hz */ 117 #define S32KCLK_FRQ (32 * 1000) 118 119 /* Create an alias of an entire original MemoryRegion @orig 120 * located at @base in the memory map. 121 */ 122 static void make_ram_alias(MemoryRegion *mr, const char *name, 123 MemoryRegion *orig, hwaddr base) 124 { 125 memory_region_init_alias(mr, NULL, name, orig, 0, 126 memory_region_size(orig)); 127 memory_region_add_subregion(get_system_memory(), base, mr); 128 } 129 130 static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) 131 { 132 /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ 133 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 134 135 assert(irqno < MPS2TZ_NUMIRQ); 136 137 switch (mmc->fpga_type) { 138 case FPGA_AN505: 139 return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno); 140 case FPGA_AN521: 141 return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); 142 default: 143 g_assert_not_reached(); 144 } 145 } 146 147 /* Most of the devices in the AN505 FPGA image sit behind 148 * Peripheral Protection Controllers. These data structures 149 * define the layout of which devices sit behind which PPCs. 150 * The devfn for each port is a function which creates, configures 151 * and initializes the device, returning the MemoryRegion which 152 * needs to be plugged into the downstream end of the PPC port. 153 */ 154 typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, 155 const char *name, hwaddr size); 156 157 typedef struct PPCPortInfo { 158 const char *name; 159 MakeDevFn *devfn; 160 void *opaque; 161 hwaddr addr; 162 hwaddr size; 163 } PPCPortInfo; 164 165 typedef struct PPCInfo { 166 const char *name; 167 PPCPortInfo ports[TZ_NUM_PORTS]; 168 } PPCInfo; 169 170 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, 171 void *opaque, 172 const char *name, hwaddr size) 173 { 174 /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, 175 * and return a pointer to its MemoryRegion. 176 */ 177 UnimplementedDeviceState *uds = opaque; 178 179 object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE); 180 qdev_prop_set_string(DEVICE(uds), "name", name); 181 qdev_prop_set_uint64(DEVICE(uds), "size", size); 182 sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); 183 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); 184 } 185 186 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, 187 const char *name, hwaddr size) 188 { 189 CMSDKAPBUART *uart = opaque; 190 int i = uart - &mms->uart[0]; 191 int rxirqno = i * 2; 192 int txirqno = i * 2 + 1; 193 int combirqno = i + 10; 194 SysBusDevice *s; 195 DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); 196 197 object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART); 198 qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); 199 qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); 200 sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); 201 s = SYS_BUS_DEVICE(uart); 202 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno)); 203 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno)); 204 sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); 205 sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); 206 sysbus_connect_irq(s, 4, get_sse_irq_in(mms, combirqno)); 207 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); 208 } 209 210 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, 211 const char *name, hwaddr size) 212 { 213 MPS2SCC *scc = opaque; 214 DeviceState *sccdev; 215 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 216 217 object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); 218 sccdev = DEVICE(scc); 219 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); 220 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); 221 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); 222 sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); 223 return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); 224 } 225 226 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, 227 const char *name, hwaddr size) 228 { 229 MPS2FPGAIO *fpgaio = opaque; 230 231 object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO); 232 sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); 233 return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); 234 } 235 236 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, 237 const char *name, hwaddr size) 238 { 239 SysBusDevice *s; 240 NICInfo *nd = &nd_table[0]; 241 242 /* In hardware this is a LAN9220; the LAN9118 is software compatible 243 * except that it doesn't support the checksum-offload feature. 244 */ 245 qemu_check_nic_model(nd, "lan9118"); 246 mms->lan9118 = qdev_new(TYPE_LAN9118); 247 qdev_set_nic_properties(mms->lan9118, nd); 248 249 s = SYS_BUS_DEVICE(mms->lan9118); 250 sysbus_realize_and_unref(s, &error_fatal); 251 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16)); 252 return sysbus_mmio_get_region(s, 0); 253 } 254 255 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, 256 const char *name, hwaddr size) 257 { 258 TZMPC *mpc = opaque; 259 int i = mpc - &mms->ssram_mpc[0]; 260 MemoryRegion *ssram = &mms->ssram[i]; 261 MemoryRegion *upstream; 262 char *mpcname = g_strdup_printf("%s-mpc", name); 263 static uint32_t ramsize[] = { 0x00400000, 0x00200000, 0x00200000 }; 264 static uint32_t rambase[] = { 0x00000000, 0x28000000, 0x28200000 }; 265 266 memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal); 267 268 object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC); 269 object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ssram), 270 &error_fatal); 271 sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); 272 /* Map the upstream end of the MPC into system memory */ 273 upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); 274 memory_region_add_subregion(get_system_memory(), rambase[i], upstream); 275 /* and connect its interrupt to the IoTKit */ 276 qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, 277 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 278 "mpcexp_status", i)); 279 280 /* The first SSRAM is a special case as it has an alias; accesses to 281 * the alias region at 0x00400000 must also go to the MPC upstream. 282 */ 283 if (i == 0) { 284 make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x00400000); 285 } 286 287 g_free(mpcname); 288 /* Return the register interface MR for our caller to map behind the PPC */ 289 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); 290 } 291 292 static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, 293 const char *name, hwaddr size) 294 { 295 PL080State *dma = opaque; 296 int i = dma - &mms->dma[0]; 297 SysBusDevice *s; 298 char *mscname = g_strdup_printf("%s-msc", name); 299 TZMSC *msc = &mms->msc[i]; 300 DeviceState *iotkitdev = DEVICE(&mms->iotkit); 301 MemoryRegion *msc_upstream; 302 MemoryRegion *msc_downstream; 303 304 /* 305 * Each DMA device is a PL081 whose transaction master interface 306 * is guarded by a Master Security Controller. The downstream end of 307 * the MSC connects to the IoTKit AHB Slave Expansion port, so the 308 * DMA devices can see all devices and memory that the CPU does. 309 */ 310 object_initialize_child(OBJECT(mms), mscname, msc, TYPE_TZ_MSC); 311 msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0); 312 object_property_set_link(OBJECT(msc), "downstream", 313 OBJECT(msc_downstream), &error_fatal); 314 object_property_set_link(OBJECT(msc), "idau", OBJECT(mms), &error_fatal); 315 sysbus_realize(SYS_BUS_DEVICE(msc), &error_fatal); 316 317 qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0, 318 qdev_get_gpio_in_named(iotkitdev, 319 "mscexp_status", i)); 320 qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i, 321 qdev_get_gpio_in_named(DEVICE(msc), 322 "irq_clear", 0)); 323 qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i, 324 qdev_get_gpio_in_named(DEVICE(msc), 325 "cfg_nonsec", 0)); 326 qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter), 327 ARRAY_SIZE(mms->ppc) + i, 328 qdev_get_gpio_in_named(DEVICE(msc), 329 "cfg_sec_resp", 0)); 330 msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0); 331 332 object_initialize_child(OBJECT(mms), name, dma, TYPE_PL081); 333 object_property_set_link(OBJECT(dma), "downstream", OBJECT(msc_upstream), 334 &error_fatal); 335 sysbus_realize(SYS_BUS_DEVICE(dma), &error_fatal); 336 337 s = SYS_BUS_DEVICE(dma); 338 /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ 339 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 58 + i * 3)); 340 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, 56 + i * 3)); 341 sysbus_connect_irq(s, 2, get_sse_irq_in(mms, 57 + i * 3)); 342 343 g_free(mscname); 344 return sysbus_mmio_get_region(s, 0); 345 } 346 347 static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, 348 const char *name, hwaddr size) 349 { 350 /* 351 * The AN505 has five PL022 SPI controllers. 352 * One of these should have the LCD controller behind it; the others 353 * are connected only to the FPGA's "general purpose SPI connector" 354 * or "shield" expansion connectors. 355 * Note that if we do implement devices behind SPI, the chip select 356 * lines are set via the "MISC" register in the MPS2 FPGAIO device. 357 */ 358 PL022State *spi = opaque; 359 int i = spi - &mms->spi[0]; 360 SysBusDevice *s; 361 362 object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022); 363 sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal); 364 s = SYS_BUS_DEVICE(spi); 365 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 51 + i)); 366 return sysbus_mmio_get_region(s, 0); 367 } 368 369 static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, 370 const char *name, hwaddr size) 371 { 372 ArmSbconI2CState *i2c = opaque; 373 SysBusDevice *s; 374 375 object_initialize_child(OBJECT(mms), name, i2c, TYPE_ARM_SBCON_I2C); 376 s = SYS_BUS_DEVICE(i2c); 377 sysbus_realize(s, &error_fatal); 378 return sysbus_mmio_get_region(s, 0); 379 } 380 381 static void mps2tz_common_init(MachineState *machine) 382 { 383 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); 384 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 385 MachineClass *mc = MACHINE_GET_CLASS(machine); 386 MemoryRegion *system_memory = get_system_memory(); 387 DeviceState *iotkitdev; 388 DeviceState *dev_splitter; 389 int i; 390 391 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { 392 error_report("This board can only be used with CPU %s", 393 mc->default_cpu_type); 394 exit(1); 395 } 396 397 if (machine->ram_size != mc->default_ram_size) { 398 char *sz = size_to_str(mc->default_ram_size); 399 error_report("Invalid RAM size, should be %s", sz); 400 g_free(sz); 401 exit(EXIT_FAILURE); 402 } 403 404 /* These clocks don't need migration because they are fixed-frequency */ 405 mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); 406 clock_set_hz(mms->sysclk, SYSCLK_FRQ); 407 mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); 408 clock_set_hz(mms->s32kclk, S32KCLK_FRQ); 409 410 object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit, 411 mmc->armsse_type); 412 iotkitdev = DEVICE(&mms->iotkit); 413 object_property_set_link(OBJECT(&mms->iotkit), "memory", 414 OBJECT(system_memory), &error_abort); 415 qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); 416 qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); 417 qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); 418 sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); 419 420 /* 421 * The AN521 needs us to create splitters to feed the IRQ inputs 422 * for each CPU in the SSE-200 from each device in the board. 423 */ 424 if (mmc->fpga_type == FPGA_AN521) { 425 for (i = 0; i < MPS2TZ_NUMIRQ; i++) { 426 char *name = g_strdup_printf("mps2-irq-splitter%d", i); 427 SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; 428 429 object_initialize_child_with_props(OBJECT(machine), name, 430 splitter, sizeof(*splitter), 431 TYPE_SPLIT_IRQ, &error_fatal, 432 NULL); 433 g_free(name); 434 435 object_property_set_int(OBJECT(splitter), "num-lines", 2, 436 &error_fatal); 437 qdev_realize(DEVICE(splitter), NULL, &error_fatal); 438 qdev_connect_gpio_out(DEVICE(splitter), 0, 439 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 440 "EXP_IRQ", i)); 441 qdev_connect_gpio_out(DEVICE(splitter), 1, 442 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 443 "EXP_CPU1_IRQ", i)); 444 } 445 } 446 447 /* The sec_resp_cfg output from the IoTKit must be split into multiple 448 * lines, one for each of the PPCs we create here, plus one per MSC. 449 */ 450 object_initialize_child(OBJECT(machine), "sec-resp-splitter", 451 &mms->sec_resp_splitter, TYPE_SPLIT_IRQ); 452 object_property_set_int(OBJECT(&mms->sec_resp_splitter), "num-lines", 453 ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc), 454 &error_fatal); 455 qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal); 456 dev_splitter = DEVICE(&mms->sec_resp_splitter); 457 qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, 458 qdev_get_gpio_in(dev_splitter, 0)); 459 460 /* The IoTKit sets up much of the memory layout, including 461 * the aliases between secure and non-secure regions in the 462 * address space. The FPGA itself contains: 463 * 464 * 0x00000000..0x003fffff SSRAM1 465 * 0x00400000..0x007fffff alias of SSRAM1 466 * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3 467 * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices 468 * 0x80000000..0x80ffffff 16MB PSRAM 469 */ 470 471 /* The FPGA images have an odd combination of different RAMs, 472 * because in hardware they are different implementations and 473 * connected to different buses, giving varying performance/size 474 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily 475 * call the 16MB our "system memory", as it's the largest lump. 476 */ 477 memory_region_add_subregion(system_memory, 0x80000000, machine->ram); 478 479 /* The overflow IRQs for all UARTs are ORed together. 480 * Tx, Rx and "combined" IRQs are sent to the NVIC separately. 481 * Create the OR gate for this. 482 */ 483 object_initialize_child(OBJECT(mms), "uart-irq-orgate", 484 &mms->uart_irq_orgate, TYPE_OR_IRQ); 485 object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", 10, 486 &error_fatal); 487 qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); 488 qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, 489 get_sse_irq_in(mms, 15)); 490 491 /* Most of the devices in the FPGA are behind Peripheral Protection 492 * Controllers. The required order for initializing things is: 493 * + initialize the PPC 494 * + initialize, configure and realize downstream devices 495 * + connect downstream device MemoryRegions to the PPC 496 * + realize the PPC 497 * + map the PPC's MemoryRegions to the places in the address map 498 * where the downstream devices should appear 499 * + wire up the PPC's control lines to the IoTKit object 500 */ 501 502 const PPCInfo ppcs[] = { { 503 .name = "apb_ppcexp0", 504 .ports = { 505 { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 }, 506 { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1000 }, 507 { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1000 }, 508 }, 509 }, { 510 .name = "apb_ppcexp1", 511 .ports = { 512 { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000 }, 513 { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000 }, 514 { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000 }, 515 { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000 }, 516 { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000 }, 517 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 }, 518 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 }, 519 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 }, 520 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 }, 521 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 }, 522 { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 }, 523 { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 }, 524 { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 }, 525 { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000 }, 526 }, 527 }, { 528 .name = "apb_ppcexp2", 529 .ports = { 530 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, 531 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 532 0x40301000, 0x1000 }, 533 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, 534 }, 535 }, { 536 .name = "ahb_ppcexp0", 537 .ports = { 538 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, 539 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, 540 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, 541 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, 542 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, 543 { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 }, 544 }, 545 }, { 546 .name = "ahb_ppcexp1", 547 .ports = { 548 { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000 }, 549 { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000 }, 550 { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000 }, 551 { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000 }, 552 }, 553 }, 554 }; 555 556 for (i = 0; i < ARRAY_SIZE(ppcs); i++) { 557 const PPCInfo *ppcinfo = &ppcs[i]; 558 TZPPC *ppc = &mms->ppc[i]; 559 DeviceState *ppcdev; 560 int port; 561 char *gpioname; 562 563 object_initialize_child(OBJECT(machine), ppcinfo->name, ppc, 564 TYPE_TZ_PPC); 565 ppcdev = DEVICE(ppc); 566 567 for (port = 0; port < TZ_NUM_PORTS; port++) { 568 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 569 MemoryRegion *mr; 570 char *portname; 571 572 if (!pinfo->devfn) { 573 continue; 574 } 575 576 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); 577 portname = g_strdup_printf("port[%d]", port); 578 object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), 579 &error_fatal); 580 g_free(portname); 581 } 582 583 sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal); 584 585 for (port = 0; port < TZ_NUM_PORTS; port++) { 586 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 587 588 if (!pinfo->devfn) { 589 continue; 590 } 591 sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); 592 593 gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); 594 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 595 qdev_get_gpio_in_named(ppcdev, 596 "cfg_nonsec", 597 port)); 598 g_free(gpioname); 599 gpioname = g_strdup_printf("%s_ap", ppcinfo->name); 600 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 601 qdev_get_gpio_in_named(ppcdev, 602 "cfg_ap", port)); 603 g_free(gpioname); 604 } 605 606 gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); 607 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 608 qdev_get_gpio_in_named(ppcdev, 609 "irq_enable", 0)); 610 g_free(gpioname); 611 gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); 612 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 613 qdev_get_gpio_in_named(ppcdev, 614 "irq_clear", 0)); 615 g_free(gpioname); 616 gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); 617 qdev_connect_gpio_out_named(ppcdev, "irq", 0, 618 qdev_get_gpio_in_named(iotkitdev, 619 gpioname, 0)); 620 g_free(gpioname); 621 622 qdev_connect_gpio_out(dev_splitter, i, 623 qdev_get_gpio_in_named(ppcdev, 624 "cfg_sec_resp", 0)); 625 } 626 627 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); 628 629 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); 630 } 631 632 static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, 633 int *iregion, bool *exempt, bool *ns, bool *nsc) 634 { 635 /* 636 * The MPS2 TZ FPGA images have IDAUs in them which are connected to 637 * the Master Security Controllers. Thes have the same logic as 638 * is used by the IoTKit for the IDAU connected to the CPU, except 639 * that MSCs don't care about the NSC attribute. 640 */ 641 int region = extract32(address, 28, 4); 642 643 *ns = !(region & 1); 644 *nsc = false; 645 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 646 *exempt = (address & 0xeff00000) == 0xe0000000; 647 *iregion = region; 648 } 649 650 static void mps2tz_class_init(ObjectClass *oc, void *data) 651 { 652 MachineClass *mc = MACHINE_CLASS(oc); 653 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); 654 655 mc->init = mps2tz_common_init; 656 iic->check = mps2_tz_idau_check; 657 mc->default_ram_size = 16 * MiB; 658 mc->default_ram_id = "mps.ram"; 659 } 660 661 static void mps2tz_an505_class_init(ObjectClass *oc, void *data) 662 { 663 MachineClass *mc = MACHINE_CLASS(oc); 664 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 665 666 mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; 667 mc->default_cpus = 1; 668 mc->min_cpus = mc->default_cpus; 669 mc->max_cpus = mc->default_cpus; 670 mmc->fpga_type = FPGA_AN505; 671 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 672 mmc->scc_id = 0x41045050; 673 mmc->armsse_type = TYPE_IOTKIT; 674 } 675 676 static void mps2tz_an521_class_init(ObjectClass *oc, void *data) 677 { 678 MachineClass *mc = MACHINE_CLASS(oc); 679 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 680 681 mc->desc = "ARM MPS2 with AN521 FPGA image for dual Cortex-M33"; 682 mc->default_cpus = 2; 683 mc->min_cpus = mc->default_cpus; 684 mc->max_cpus = mc->default_cpus; 685 mmc->fpga_type = FPGA_AN521; 686 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 687 mmc->scc_id = 0x41045210; 688 mmc->armsse_type = TYPE_SSE200; 689 } 690 691 static const TypeInfo mps2tz_info = { 692 .name = TYPE_MPS2TZ_MACHINE, 693 .parent = TYPE_MACHINE, 694 .abstract = true, 695 .instance_size = sizeof(MPS2TZMachineState), 696 .class_size = sizeof(MPS2TZMachineClass), 697 .class_init = mps2tz_class_init, 698 .interfaces = (InterfaceInfo[]) { 699 { TYPE_IDAU_INTERFACE }, 700 { } 701 }, 702 }; 703 704 static const TypeInfo mps2tz_an505_info = { 705 .name = TYPE_MPS2TZ_AN505_MACHINE, 706 .parent = TYPE_MPS2TZ_MACHINE, 707 .class_init = mps2tz_an505_class_init, 708 }; 709 710 static const TypeInfo mps2tz_an521_info = { 711 .name = TYPE_MPS2TZ_AN521_MACHINE, 712 .parent = TYPE_MPS2TZ_MACHINE, 713 .class_init = mps2tz_an521_class_init, 714 }; 715 716 static void mps2tz_machine_init(void) 717 { 718 type_register_static(&mps2tz_info); 719 type_register_static(&mps2tz_an505_info); 720 type_register_static(&mps2tz_an521_info); 721 } 722 723 type_init(mps2tz_machine_init); 724