1 /* 2 * ARM V2M MPS2 board emulation, trustzone aware FPGA images 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger 13 * FPGA but is otherwise the same as the 2). Since the CPU itself 14 * and most of the devices are in the FPGA, the details of the board 15 * as seen by the guest depend significantly on the FPGA image. 16 * This source file covers the following FPGA images, for TrustZone cores: 17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 18 * 19 * Links to the TRM for the board itself and to the various Application 20 * Notes which document the FPGA images can be found here: 21 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 22 * 23 * Board TRM: 24 * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf 25 * Application Note AN505: 26 * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html 27 * 28 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide 29 * (ARM ECM0601256) for the details of some of the device layout: 30 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html 31 */ 32 33 #include "qemu/osdep.h" 34 #include "qapi/error.h" 35 #include "qemu/error-report.h" 36 #include "hw/arm/arm.h" 37 #include "hw/arm/armv7m.h" 38 #include "hw/or-irq.h" 39 #include "hw/boards.h" 40 #include "exec/address-spaces.h" 41 #include "sysemu/sysemu.h" 42 #include "hw/misc/unimp.h" 43 #include "hw/char/cmsdk-apb-uart.h" 44 #include "hw/timer/cmsdk-apb-timer.h" 45 #include "hw/misc/mps2-scc.h" 46 #include "hw/misc/mps2-fpgaio.h" 47 #include "hw/misc/tz-mpc.h" 48 #include "hw/misc/tz-msc.h" 49 #include "hw/arm/iotkit.h" 50 #include "hw/dma/pl080.h" 51 #include "hw/ssi/pl022.h" 52 #include "hw/devices.h" 53 #include "net/net.h" 54 #include "hw/core/split-irq.h" 55 56 typedef enum MPS2TZFPGAType { 57 FPGA_AN505, 58 } MPS2TZFPGAType; 59 60 typedef struct { 61 MachineClass parent; 62 MPS2TZFPGAType fpga_type; 63 uint32_t scc_id; 64 } MPS2TZMachineClass; 65 66 typedef struct { 67 MachineState parent; 68 69 IoTKit iotkit; 70 MemoryRegion psram; 71 MemoryRegion ssram[3]; 72 MemoryRegion ssram1_m; 73 MPS2SCC scc; 74 MPS2FPGAIO fpgaio; 75 TZPPC ppc[5]; 76 TZMPC ssram_mpc[3]; 77 PL022State spi[5]; 78 UnimplementedDeviceState i2c[4]; 79 UnimplementedDeviceState i2s_audio; 80 UnimplementedDeviceState gpio[4]; 81 UnimplementedDeviceState gfx; 82 PL080State dma[4]; 83 TZMSC msc[4]; 84 CMSDKAPBUART uart[5]; 85 SplitIRQ sec_resp_splitter; 86 qemu_or_irq uart_irq_orgate; 87 DeviceState *lan9118; 88 } MPS2TZMachineState; 89 90 #define TYPE_MPS2TZ_MACHINE "mps2tz" 91 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") 92 93 #define MPS2TZ_MACHINE(obj) \ 94 OBJECT_CHECK(MPS2TZMachineState, obj, TYPE_MPS2TZ_MACHINE) 95 #define MPS2TZ_MACHINE_GET_CLASS(obj) \ 96 OBJECT_GET_CLASS(MPS2TZMachineClass, obj, TYPE_MPS2TZ_MACHINE) 97 #define MPS2TZ_MACHINE_CLASS(klass) \ 98 OBJECT_CLASS_CHECK(MPS2TZMachineClass, klass, TYPE_MPS2TZ_MACHINE) 99 100 /* Main SYSCLK frequency in Hz */ 101 #define SYSCLK_FRQ 20000000 102 103 /* Create an alias of an entire original MemoryRegion @orig 104 * located at @base in the memory map. 105 */ 106 static void make_ram_alias(MemoryRegion *mr, const char *name, 107 MemoryRegion *orig, hwaddr base) 108 { 109 memory_region_init_alias(mr, NULL, name, orig, 0, 110 memory_region_size(orig)); 111 memory_region_add_subregion(get_system_memory(), base, mr); 112 } 113 114 /* Most of the devices in the AN505 FPGA image sit behind 115 * Peripheral Protection Controllers. These data structures 116 * define the layout of which devices sit behind which PPCs. 117 * The devfn for each port is a function which creates, configures 118 * and initializes the device, returning the MemoryRegion which 119 * needs to be plugged into the downstream end of the PPC port. 120 */ 121 typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, 122 const char *name, hwaddr size); 123 124 typedef struct PPCPortInfo { 125 const char *name; 126 MakeDevFn *devfn; 127 void *opaque; 128 hwaddr addr; 129 hwaddr size; 130 } PPCPortInfo; 131 132 typedef struct PPCInfo { 133 const char *name; 134 PPCPortInfo ports[TZ_NUM_PORTS]; 135 } PPCInfo; 136 137 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, 138 void *opaque, 139 const char *name, hwaddr size) 140 { 141 /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, 142 * and return a pointer to its MemoryRegion. 143 */ 144 UnimplementedDeviceState *uds = opaque; 145 146 sysbus_init_child_obj(OBJECT(mms), name, uds, 147 sizeof(UnimplementedDeviceState), 148 TYPE_UNIMPLEMENTED_DEVICE); 149 qdev_prop_set_string(DEVICE(uds), "name", name); 150 qdev_prop_set_uint64(DEVICE(uds), "size", size); 151 object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal); 152 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); 153 } 154 155 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, 156 const char *name, hwaddr size) 157 { 158 CMSDKAPBUART *uart = opaque; 159 int i = uart - &mms->uart[0]; 160 int rxirqno = i * 2; 161 int txirqno = i * 2 + 1; 162 int combirqno = i + 10; 163 SysBusDevice *s; 164 DeviceState *iotkitdev = DEVICE(&mms->iotkit); 165 DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); 166 167 sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]), 168 TYPE_CMSDK_APB_UART); 169 qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); 170 qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); 171 object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal); 172 s = SYS_BUS_DEVICE(uart); 173 sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, 174 "EXP_IRQ", txirqno)); 175 sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev, 176 "EXP_IRQ", rxirqno)); 177 sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); 178 sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); 179 sysbus_connect_irq(s, 4, qdev_get_gpio_in_named(iotkitdev, 180 "EXP_IRQ", combirqno)); 181 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); 182 } 183 184 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, 185 const char *name, hwaddr size) 186 { 187 MPS2SCC *scc = opaque; 188 DeviceState *sccdev; 189 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 190 191 object_initialize(scc, sizeof(mms->scc), TYPE_MPS2_SCC); 192 sccdev = DEVICE(scc); 193 qdev_set_parent_bus(sccdev, sysbus_get_default()); 194 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); 195 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); 196 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); 197 object_property_set_bool(OBJECT(scc), true, "realized", &error_fatal); 198 return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); 199 } 200 201 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, 202 const char *name, hwaddr size) 203 { 204 MPS2FPGAIO *fpgaio = opaque; 205 206 object_initialize(fpgaio, sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO); 207 qdev_set_parent_bus(DEVICE(fpgaio), sysbus_get_default()); 208 object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal); 209 return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); 210 } 211 212 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, 213 const char *name, hwaddr size) 214 { 215 SysBusDevice *s; 216 DeviceState *iotkitdev = DEVICE(&mms->iotkit); 217 NICInfo *nd = &nd_table[0]; 218 219 /* In hardware this is a LAN9220; the LAN9118 is software compatible 220 * except that it doesn't support the checksum-offload feature. 221 */ 222 qemu_check_nic_model(nd, "lan9118"); 223 mms->lan9118 = qdev_create(NULL, "lan9118"); 224 qdev_set_nic_properties(mms->lan9118, nd); 225 qdev_init_nofail(mms->lan9118); 226 227 s = SYS_BUS_DEVICE(mms->lan9118); 228 sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 16)); 229 return sysbus_mmio_get_region(s, 0); 230 } 231 232 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, 233 const char *name, hwaddr size) 234 { 235 TZMPC *mpc = opaque; 236 int i = mpc - &mms->ssram_mpc[0]; 237 MemoryRegion *ssram = &mms->ssram[i]; 238 MemoryRegion *upstream; 239 char *mpcname = g_strdup_printf("%s-mpc", name); 240 static uint32_t ramsize[] = { 0x00400000, 0x00200000, 0x00200000 }; 241 static uint32_t rambase[] = { 0x00000000, 0x28000000, 0x28200000 }; 242 243 memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal); 244 245 sysbus_init_child_obj(OBJECT(mms), mpcname, mpc, sizeof(mms->ssram_mpc[0]), 246 TYPE_TZ_MPC); 247 object_property_set_link(OBJECT(mpc), OBJECT(ssram), 248 "downstream", &error_fatal); 249 object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal); 250 /* Map the upstream end of the MPC into system memory */ 251 upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); 252 memory_region_add_subregion(get_system_memory(), rambase[i], upstream); 253 /* and connect its interrupt to the IoTKit */ 254 qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, 255 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 256 "mpcexp_status", i)); 257 258 /* The first SSRAM is a special case as it has an alias; accesses to 259 * the alias region at 0x00400000 must also go to the MPC upstream. 260 */ 261 if (i == 0) { 262 make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x00400000); 263 } 264 265 g_free(mpcname); 266 /* Return the register interface MR for our caller to map behind the PPC */ 267 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); 268 } 269 270 static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, 271 const char *name, hwaddr size) 272 { 273 PL080State *dma = opaque; 274 int i = dma - &mms->dma[0]; 275 SysBusDevice *s; 276 char *mscname = g_strdup_printf("%s-msc", name); 277 TZMSC *msc = &mms->msc[i]; 278 DeviceState *iotkitdev = DEVICE(&mms->iotkit); 279 MemoryRegion *msc_upstream; 280 MemoryRegion *msc_downstream; 281 282 /* 283 * Each DMA device is a PL081 whose transaction master interface 284 * is guarded by a Master Security Controller. The downstream end of 285 * the MSC connects to the IoTKit AHB Slave Expansion port, so the 286 * DMA devices can see all devices and memory that the CPU does. 287 */ 288 sysbus_init_child_obj(OBJECT(mms), mscname, msc, sizeof(*msc), TYPE_TZ_MSC); 289 msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0); 290 object_property_set_link(OBJECT(msc), OBJECT(msc_downstream), 291 "downstream", &error_fatal); 292 object_property_set_link(OBJECT(msc), OBJECT(mms), 293 "idau", &error_fatal); 294 object_property_set_bool(OBJECT(msc), true, "realized", &error_fatal); 295 296 qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0, 297 qdev_get_gpio_in_named(iotkitdev, 298 "mscexp_status", i)); 299 qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i, 300 qdev_get_gpio_in_named(DEVICE(msc), 301 "irq_clear", 0)); 302 qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i, 303 qdev_get_gpio_in_named(DEVICE(msc), 304 "cfg_nonsec", 0)); 305 qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter), 306 ARRAY_SIZE(mms->ppc) + i, 307 qdev_get_gpio_in_named(DEVICE(msc), 308 "cfg_sec_resp", 0)); 309 msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0); 310 311 sysbus_init_child_obj(OBJECT(mms), name, dma, sizeof(*dma), TYPE_PL081); 312 object_property_set_link(OBJECT(dma), OBJECT(msc_upstream), 313 "downstream", &error_fatal); 314 object_property_set_bool(OBJECT(dma), true, "realized", &error_fatal); 315 316 s = SYS_BUS_DEVICE(dma); 317 /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ 318 sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, 319 "EXP_IRQ", 58 + i * 3)); 320 sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev, 321 "EXP_IRQ", 56 + i * 3)); 322 sysbus_connect_irq(s, 2, qdev_get_gpio_in_named(iotkitdev, 323 "EXP_IRQ", 57 + i * 3)); 324 325 return sysbus_mmio_get_region(s, 0); 326 } 327 328 static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, 329 const char *name, hwaddr size) 330 { 331 /* 332 * The AN505 has five PL022 SPI controllers. 333 * One of these should have the LCD controller behind it; the others 334 * are connected only to the FPGA's "general purpose SPI connector" 335 * or "shield" expansion connectors. 336 * Note that if we do implement devices behind SPI, the chip select 337 * lines are set via the "MISC" register in the MPS2 FPGAIO device. 338 */ 339 PL022State *spi = opaque; 340 int i = spi - &mms->spi[0]; 341 DeviceState *iotkitdev = DEVICE(&mms->iotkit); 342 SysBusDevice *s; 343 344 sysbus_init_child_obj(OBJECT(mms), name, spi, sizeof(mms->spi[0]), 345 TYPE_PL022); 346 object_property_set_bool(OBJECT(spi), true, "realized", &error_fatal); 347 s = SYS_BUS_DEVICE(spi); 348 sysbus_connect_irq(s, 0, 349 qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 51 + i)); 350 return sysbus_mmio_get_region(s, 0); 351 } 352 353 static void mps2tz_common_init(MachineState *machine) 354 { 355 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); 356 MachineClass *mc = MACHINE_GET_CLASS(machine); 357 MemoryRegion *system_memory = get_system_memory(); 358 DeviceState *iotkitdev; 359 DeviceState *dev_splitter; 360 int i; 361 362 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { 363 error_report("This board can only be used with CPU %s", 364 mc->default_cpu_type); 365 exit(1); 366 } 367 368 sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit, 369 sizeof(mms->iotkit), TYPE_IOTKIT); 370 iotkitdev = DEVICE(&mms->iotkit); 371 object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory), 372 "memory", &error_abort); 373 qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", 92); 374 qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); 375 object_property_set_bool(OBJECT(&mms->iotkit), true, "realized", 376 &error_fatal); 377 378 /* The sec_resp_cfg output from the IoTKit must be split into multiple 379 * lines, one for each of the PPCs we create here, plus one per MSC. 380 */ 381 object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter), 382 TYPE_SPLIT_IRQ); 383 object_property_add_child(OBJECT(machine), "sec-resp-splitter", 384 OBJECT(&mms->sec_resp_splitter), &error_abort); 385 object_property_set_int(OBJECT(&mms->sec_resp_splitter), 386 ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc), 387 "num-lines", &error_fatal); 388 object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true, 389 "realized", &error_fatal); 390 dev_splitter = DEVICE(&mms->sec_resp_splitter); 391 qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, 392 qdev_get_gpio_in(dev_splitter, 0)); 393 394 /* The IoTKit sets up much of the memory layout, including 395 * the aliases between secure and non-secure regions in the 396 * address space. The FPGA itself contains: 397 * 398 * 0x00000000..0x003fffff SSRAM1 399 * 0x00400000..0x007fffff alias of SSRAM1 400 * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3 401 * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices 402 * 0x80000000..0x80ffffff 16MB PSRAM 403 */ 404 405 /* The FPGA images have an odd combination of different RAMs, 406 * because in hardware they are different implementations and 407 * connected to different buses, giving varying performance/size 408 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily 409 * call the 16MB our "system memory", as it's the largest lump. 410 */ 411 memory_region_allocate_system_memory(&mms->psram, 412 NULL, "mps.ram", 0x01000000); 413 memory_region_add_subregion(system_memory, 0x80000000, &mms->psram); 414 415 /* The overflow IRQs for all UARTs are ORed together. 416 * Tx, Rx and "combined" IRQs are sent to the NVIC separately. 417 * Create the OR gate for this. 418 */ 419 object_initialize(&mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate), 420 TYPE_OR_IRQ); 421 object_property_add_child(OBJECT(mms), "uart-irq-orgate", 422 OBJECT(&mms->uart_irq_orgate), &error_abort); 423 object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines", 424 &error_fatal); 425 object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true, 426 "realized", &error_fatal); 427 qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, 428 qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 15)); 429 430 /* Most of the devices in the FPGA are behind Peripheral Protection 431 * Controllers. The required order for initializing things is: 432 * + initialize the PPC 433 * + initialize, configure and realize downstream devices 434 * + connect downstream device MemoryRegions to the PPC 435 * + realize the PPC 436 * + map the PPC's MemoryRegions to the places in the address map 437 * where the downstream devices should appear 438 * + wire up the PPC's control lines to the IoTKit object 439 */ 440 441 const PPCInfo ppcs[] = { { 442 .name = "apb_ppcexp0", 443 .ports = { 444 { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 }, 445 { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1000 }, 446 { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1000 }, 447 }, 448 }, { 449 .name = "apb_ppcexp1", 450 .ports = { 451 { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000 }, 452 { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000 }, 453 { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000 }, 454 { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000 }, 455 { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000 }, 456 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 }, 457 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 }, 458 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 }, 459 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 }, 460 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 }, 461 { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40207000, 0x1000 }, 462 { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40208000, 0x1000 }, 463 { "i2c2", make_unimp_dev, &mms->i2c[2], 0x4020c000, 0x1000 }, 464 { "i2c3", make_unimp_dev, &mms->i2c[3], 0x4020d000, 0x1000 }, 465 }, 466 }, { 467 .name = "apb_ppcexp2", 468 .ports = { 469 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, 470 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 471 0x40301000, 0x1000 }, 472 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, 473 }, 474 }, { 475 .name = "ahb_ppcexp0", 476 .ports = { 477 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, 478 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, 479 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, 480 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, 481 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, 482 { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 }, 483 }, 484 }, { 485 .name = "ahb_ppcexp1", 486 .ports = { 487 { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000 }, 488 { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000 }, 489 { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000 }, 490 { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000 }, 491 }, 492 }, 493 }; 494 495 for (i = 0; i < ARRAY_SIZE(ppcs); i++) { 496 const PPCInfo *ppcinfo = &ppcs[i]; 497 TZPPC *ppc = &mms->ppc[i]; 498 DeviceState *ppcdev; 499 int port; 500 char *gpioname; 501 502 sysbus_init_child_obj(OBJECT(machine), ppcinfo->name, ppc, 503 sizeof(TZPPC), TYPE_TZ_PPC); 504 ppcdev = DEVICE(ppc); 505 506 for (port = 0; port < TZ_NUM_PORTS; port++) { 507 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 508 MemoryRegion *mr; 509 char *portname; 510 511 if (!pinfo->devfn) { 512 continue; 513 } 514 515 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); 516 portname = g_strdup_printf("port[%d]", port); 517 object_property_set_link(OBJECT(ppc), OBJECT(mr), 518 portname, &error_fatal); 519 g_free(portname); 520 } 521 522 object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal); 523 524 for (port = 0; port < TZ_NUM_PORTS; port++) { 525 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 526 527 if (!pinfo->devfn) { 528 continue; 529 } 530 sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); 531 532 gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); 533 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 534 qdev_get_gpio_in_named(ppcdev, 535 "cfg_nonsec", 536 port)); 537 g_free(gpioname); 538 gpioname = g_strdup_printf("%s_ap", ppcinfo->name); 539 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 540 qdev_get_gpio_in_named(ppcdev, 541 "cfg_ap", port)); 542 g_free(gpioname); 543 } 544 545 gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); 546 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 547 qdev_get_gpio_in_named(ppcdev, 548 "irq_enable", 0)); 549 g_free(gpioname); 550 gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); 551 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 552 qdev_get_gpio_in_named(ppcdev, 553 "irq_clear", 0)); 554 g_free(gpioname); 555 gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); 556 qdev_connect_gpio_out_named(ppcdev, "irq", 0, 557 qdev_get_gpio_in_named(iotkitdev, 558 gpioname, 0)); 559 g_free(gpioname); 560 561 qdev_connect_gpio_out(dev_splitter, i, 562 qdev_get_gpio_in_named(ppcdev, 563 "cfg_sec_resp", 0)); 564 } 565 566 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); 567 568 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); 569 } 570 571 static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, 572 int *iregion, bool *exempt, bool *ns, bool *nsc) 573 { 574 /* 575 * The MPS2 TZ FPGA images have IDAUs in them which are connected to 576 * the Master Security Controllers. Thes have the same logic as 577 * is used by the IoTKit for the IDAU connected to the CPU, except 578 * that MSCs don't care about the NSC attribute. 579 */ 580 int region = extract32(address, 28, 4); 581 582 *ns = !(region & 1); 583 *nsc = false; 584 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 585 *exempt = (address & 0xeff00000) == 0xe0000000; 586 *iregion = region; 587 } 588 589 static void mps2tz_class_init(ObjectClass *oc, void *data) 590 { 591 MachineClass *mc = MACHINE_CLASS(oc); 592 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); 593 594 mc->init = mps2tz_common_init; 595 mc->max_cpus = 1; 596 iic->check = mps2_tz_idau_check; 597 } 598 599 static void mps2tz_an505_class_init(ObjectClass *oc, void *data) 600 { 601 MachineClass *mc = MACHINE_CLASS(oc); 602 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 603 604 mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; 605 mmc->fpga_type = FPGA_AN505; 606 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 607 mmc->scc_id = 0x41045050; 608 } 609 610 static const TypeInfo mps2tz_info = { 611 .name = TYPE_MPS2TZ_MACHINE, 612 .parent = TYPE_MACHINE, 613 .abstract = true, 614 .instance_size = sizeof(MPS2TZMachineState), 615 .class_size = sizeof(MPS2TZMachineClass), 616 .class_init = mps2tz_class_init, 617 .interfaces = (InterfaceInfo[]) { 618 { TYPE_IDAU_INTERFACE }, 619 { } 620 }, 621 }; 622 623 static const TypeInfo mps2tz_an505_info = { 624 .name = TYPE_MPS2TZ_AN505_MACHINE, 625 .parent = TYPE_MPS2TZ_MACHINE, 626 .class_init = mps2tz_an505_class_init, 627 }; 628 629 static void mps2tz_machine_init(void) 630 { 631 type_register_static(&mps2tz_info); 632 type_register_static(&mps2tz_an505_info); 633 } 634 635 type_init(mps2tz_machine_init); 636