1 /* 2 * ARM V2M MPS2 board emulation, trustzone aware FPGA images 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger 13 * FPGA but is otherwise the same as the 2). Since the CPU itself 14 * and most of the devices are in the FPGA, the details of the board 15 * as seen by the guest depend significantly on the FPGA image. 16 * This source file covers the following FPGA images, for TrustZone cores: 17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 18 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521 19 * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524 20 * "mps2-an547" -- Single Cortex-M55 as documented in Application Note AN547 21 * 22 * Links to the TRM for the board itself and to the various Application 23 * Notes which document the FPGA images can be found here: 24 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 25 * 26 * Board TRM: 27 * https://developer.arm.com/documentation/100112/latest/ 28 * Application Note AN505: 29 * https://developer.arm.com/documentation/dai0505/latest/ 30 * Application Note AN521: 31 * https://developer.arm.com/documentation/dai0521/latest/ 32 * Application Note AN524: 33 * https://developer.arm.com/documentation/dai0524/latest/ 34 * Application Note AN547: 35 * https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf 36 * 37 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide 38 * (ARM ECM0601256) for the details of some of the device layout: 39 * https://developer.arm.com/documentation/ecm0601256/latest 40 * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines 41 * most of the device layout: 42 * https://developer.arm.com/documentation/101104/latest/ 43 * and the AN547 uses the SSE-300, whose layout is in the SSE-300 TRM: 44 * https://developer.arm.com/documentation/101773/latest/ 45 */ 46 47 #include "qemu/osdep.h" 48 #include "qemu/units.h" 49 #include "qemu/cutils.h" 50 #include "qapi/error.h" 51 #include "qemu/error-report.h" 52 #include "hw/arm/boot.h" 53 #include "hw/arm/armv7m.h" 54 #include "hw/or-irq.h" 55 #include "hw/boards.h" 56 #include "exec/address-spaces.h" 57 #include "sysemu/sysemu.h" 58 #include "sysemu/reset.h" 59 #include "hw/misc/unimp.h" 60 #include "hw/char/cmsdk-apb-uart.h" 61 #include "hw/timer/cmsdk-apb-timer.h" 62 #include "hw/misc/mps2-scc.h" 63 #include "hw/misc/mps2-fpgaio.h" 64 #include "hw/misc/tz-mpc.h" 65 #include "hw/misc/tz-msc.h" 66 #include "hw/arm/armsse.h" 67 #include "hw/dma/pl080.h" 68 #include "hw/rtc/pl031.h" 69 #include "hw/ssi/pl022.h" 70 #include "hw/i2c/arm_sbcon_i2c.h" 71 #include "hw/net/lan9118.h" 72 #include "net/net.h" 73 #include "hw/core/split-irq.h" 74 #include "hw/qdev-clock.h" 75 #include "qom/object.h" 76 #include "hw/irq.h" 77 78 #define MPS2TZ_NUMIRQ_MAX 96 79 #define MPS2TZ_RAM_MAX 5 80 81 typedef enum MPS2TZFPGAType { 82 FPGA_AN505, 83 FPGA_AN521, 84 FPGA_AN524, 85 FPGA_AN547, 86 } MPS2TZFPGAType; 87 88 /* 89 * Define the layout of RAM in a board, including which parts are 90 * behind which MPCs. 91 * mrindex specifies the index into mms->ram[] to use for the backing RAM; 92 * -1 means "use the system RAM". 93 */ 94 typedef struct RAMInfo { 95 const char *name; 96 uint32_t base; 97 uint32_t size; 98 int mpc; /* MPC number, -1 for "not behind an MPC" */ 99 int mrindex; 100 int flags; 101 } RAMInfo; 102 103 /* 104 * Flag values: 105 * IS_ALIAS: this RAM area is an alias to the upstream end of the 106 * MPC specified by its .mpc value 107 * IS_ROM: this RAM area is read-only 108 */ 109 #define IS_ALIAS 1 110 #define IS_ROM 2 111 112 struct MPS2TZMachineClass { 113 MachineClass parent; 114 MPS2TZFPGAType fpga_type; 115 uint32_t scc_id; 116 uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ 117 uint32_t apb_periph_frq; /* APB peripheral frequency in Hz */ 118 uint32_t len_oscclk; 119 const uint32_t *oscclk; 120 uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ 121 bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ 122 bool fpgaio_has_dbgctrl; /* Does FPGAIO have DBGCTRL register? */ 123 int numirq; /* Number of external interrupts */ 124 int uart_overflow_irq; /* number of the combined UART overflow IRQ */ 125 uint32_t init_svtor; /* init-svtor setting for SSE */ 126 uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */ 127 const RAMInfo *raminfo; 128 const char *armsse_type; 129 uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */ 130 }; 131 132 struct MPS2TZMachineState { 133 MachineState parent; 134 135 ARMSSE iotkit; 136 MemoryRegion ram[MPS2TZ_RAM_MAX]; 137 MemoryRegion eth_usb_container; 138 139 MPS2SCC scc; 140 MPS2FPGAIO fpgaio; 141 TZPPC ppc[5]; 142 TZMPC mpc[3]; 143 PL022State spi[5]; 144 ArmSbconI2CState i2c[5]; 145 UnimplementedDeviceState i2s_audio; 146 UnimplementedDeviceState gpio[4]; 147 UnimplementedDeviceState gfx; 148 UnimplementedDeviceState cldc; 149 UnimplementedDeviceState usb; 150 PL031State rtc; 151 PL080State dma[4]; 152 TZMSC msc[4]; 153 CMSDKAPBUART uart[6]; 154 SplitIRQ sec_resp_splitter; 155 qemu_or_irq uart_irq_orgate; 156 DeviceState *lan9118; 157 SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; 158 Clock *sysclk; 159 Clock *s32kclk; 160 161 bool remap; 162 qemu_irq remap_irq; 163 }; 164 165 #define TYPE_MPS2TZ_MACHINE "mps2tz" 166 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") 167 #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") 168 #define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524") 169 #define TYPE_MPS3TZ_AN547_MACHINE MACHINE_TYPE_NAME("mps3-an547") 170 171 OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) 172 173 /* Slow 32Khz S32KCLK frequency in Hz */ 174 #define S32KCLK_FRQ (32 * 1000) 175 176 /* 177 * The MPS3 DDR is 2GiB, but on a 32-bit host QEMU doesn't permit 178 * emulation of that much guest RAM, so artificially make it smaller. 179 */ 180 #if HOST_LONG_BITS == 32 181 #define MPS3_DDR_SIZE (1 * GiB) 182 #else 183 #define MPS3_DDR_SIZE (2 * GiB) 184 #endif 185 186 static const uint32_t an505_oscclk[] = { 187 40000000, 188 24580000, 189 25000000, 190 }; 191 192 static const uint32_t an524_oscclk[] = { 193 24000000, 194 32000000, 195 50000000, 196 50000000, 197 24576000, 198 23750000, 199 }; 200 201 static const RAMInfo an505_raminfo[] = { { 202 .name = "ssram-0", 203 .base = 0x00000000, 204 .size = 0x00400000, 205 .mpc = 0, 206 .mrindex = 0, 207 }, { 208 .name = "ssram-1", 209 .base = 0x28000000, 210 .size = 0x00200000, 211 .mpc = 1, 212 .mrindex = 1, 213 }, { 214 .name = "ssram-2", 215 .base = 0x28200000, 216 .size = 0x00200000, 217 .mpc = 2, 218 .mrindex = 2, 219 }, { 220 .name = "ssram-0-alias", 221 .base = 0x00400000, 222 .size = 0x00400000, 223 .mpc = 0, 224 .mrindex = 3, 225 .flags = IS_ALIAS, 226 }, { 227 /* Use the largest bit of contiguous RAM as our "system memory" */ 228 .name = "mps.ram", 229 .base = 0x80000000, 230 .size = 16 * MiB, 231 .mpc = -1, 232 .mrindex = -1, 233 }, { 234 .name = NULL, 235 }, 236 }; 237 238 /* 239 * Note that the addresses and MPC numbering here should match up 240 * with those used in remap_memory(), which can swap the BRAM and QSPI. 241 */ 242 static const RAMInfo an524_raminfo[] = { { 243 .name = "bram", 244 .base = 0x00000000, 245 .size = 512 * KiB, 246 .mpc = 0, 247 .mrindex = 0, 248 }, { 249 /* We don't model QSPI flash yet; for now expose it as simple ROM */ 250 .name = "QSPI", 251 .base = 0x28000000, 252 .size = 8 * MiB, 253 .mpc = 1, 254 .mrindex = 1, 255 .flags = IS_ROM, 256 }, { 257 .name = "DDR", 258 .base = 0x60000000, 259 .size = MPS3_DDR_SIZE, 260 .mpc = 2, 261 .mrindex = -1, 262 }, { 263 .name = NULL, 264 }, 265 }; 266 267 static const RAMInfo an547_raminfo[] = { { 268 .name = "sram", 269 .base = 0x01000000, 270 .size = 2 * MiB, 271 .mpc = 0, 272 .mrindex = 1, 273 }, { 274 .name = "sram 2", 275 .base = 0x21000000, 276 .size = 4 * MiB, 277 .mpc = -1, 278 .mrindex = 3, 279 }, { 280 /* We don't model QSPI flash yet; for now expose it as simple ROM */ 281 .name = "QSPI", 282 .base = 0x28000000, 283 .size = 8 * MiB, 284 .mpc = 1, 285 .mrindex = 4, 286 .flags = IS_ROM, 287 }, { 288 .name = "DDR", 289 .base = 0x60000000, 290 .size = MPS3_DDR_SIZE, 291 .mpc = 2, 292 .mrindex = -1, 293 }, { 294 .name = NULL, 295 }, 296 }; 297 298 static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc) 299 { 300 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 301 const RAMInfo *p; 302 const RAMInfo *found = NULL; 303 304 for (p = mmc->raminfo; p->name; p++) { 305 if (p->mpc == mpc && !(p->flags & IS_ALIAS)) { 306 /* There should only be one entry in the array for this MPC */ 307 g_assert(!found); 308 found = p; 309 } 310 } 311 /* if raminfo array doesn't have an entry for each MPC this is a bug */ 312 assert(found); 313 return found; 314 } 315 316 static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms, 317 const RAMInfo *raminfo) 318 { 319 /* Return an initialized MemoryRegion for the RAMInfo. */ 320 MemoryRegion *ram; 321 322 if (raminfo->mrindex < 0) { 323 /* Means this RAMInfo is for QEMU's "system memory" */ 324 MachineState *machine = MACHINE(mms); 325 assert(!(raminfo->flags & IS_ROM)); 326 return machine->ram; 327 } 328 329 assert(raminfo->mrindex < MPS2TZ_RAM_MAX); 330 ram = &mms->ram[raminfo->mrindex]; 331 332 memory_region_init_ram(ram, NULL, raminfo->name, 333 raminfo->size, &error_fatal); 334 if (raminfo->flags & IS_ROM) { 335 memory_region_set_readonly(ram, true); 336 } 337 return ram; 338 } 339 340 /* Create an alias of an entire original MemoryRegion @orig 341 * located at @base in the memory map. 342 */ 343 static void make_ram_alias(MemoryRegion *mr, const char *name, 344 MemoryRegion *orig, hwaddr base) 345 { 346 memory_region_init_alias(mr, NULL, name, orig, 0, 347 memory_region_size(orig)); 348 memory_region_add_subregion(get_system_memory(), base, mr); 349 } 350 351 static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) 352 { 353 /* 354 * Return a qemu_irq which will signal IRQ n to all CPUs in the 355 * SSE. The irqno should be as the CPU sees it, so the first 356 * external-to-the-SSE interrupt is 32. 357 */ 358 MachineClass *mc = MACHINE_GET_CLASS(mms); 359 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 360 361 assert(irqno >= 32 && irqno < (mmc->numirq + 32)); 362 363 /* 364 * Convert from "CPU irq number" (as listed in the FPGA image 365 * documentation) to the SSE external-interrupt number. 366 */ 367 irqno -= 32; 368 369 if (mc->max_cpus > 1) { 370 return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); 371 } else { 372 return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno); 373 } 374 } 375 376 /* Most of the devices in the AN505 FPGA image sit behind 377 * Peripheral Protection Controllers. These data structures 378 * define the layout of which devices sit behind which PPCs. 379 * The devfn for each port is a function which creates, configures 380 * and initializes the device, returning the MemoryRegion which 381 * needs to be plugged into the downstream end of the PPC port. 382 */ 383 typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, 384 const char *name, hwaddr size, 385 const int *irqs); 386 387 typedef struct PPCPortInfo { 388 const char *name; 389 MakeDevFn *devfn; 390 void *opaque; 391 hwaddr addr; 392 hwaddr size; 393 int irqs[3]; /* currently no device needs more IRQ lines than this */ 394 } PPCPortInfo; 395 396 typedef struct PPCInfo { 397 const char *name; 398 PPCPortInfo ports[TZ_NUM_PORTS]; 399 } PPCInfo; 400 401 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, 402 void *opaque, 403 const char *name, hwaddr size, 404 const int *irqs) 405 { 406 /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, 407 * and return a pointer to its MemoryRegion. 408 */ 409 UnimplementedDeviceState *uds = opaque; 410 411 object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE); 412 qdev_prop_set_string(DEVICE(uds), "name", name); 413 qdev_prop_set_uint64(DEVICE(uds), "size", size); 414 sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); 415 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); 416 } 417 418 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, 419 const char *name, hwaddr size, 420 const int *irqs) 421 { 422 /* The irq[] array is tx, rx, combined, in that order */ 423 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 424 CMSDKAPBUART *uart = opaque; 425 int i = uart - &mms->uart[0]; 426 SysBusDevice *s; 427 DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); 428 429 object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART); 430 qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); 431 qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->apb_periph_frq); 432 sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); 433 s = SYS_BUS_DEVICE(uart); 434 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 435 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); 436 sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); 437 sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); 438 sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2])); 439 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); 440 } 441 442 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, 443 const char *name, hwaddr size, 444 const int *irqs) 445 { 446 MPS2SCC *scc = opaque; 447 DeviceState *sccdev; 448 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 449 uint32_t i; 450 451 object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); 452 sccdev = DEVICE(scc); 453 qdev_prop_set_uint32(sccdev, "scc-cfg0", mms->remap ? 1 : 0); 454 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); 455 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); 456 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); 457 qdev_prop_set_uint32(sccdev, "len-oscclk", mmc->len_oscclk); 458 for (i = 0; i < mmc->len_oscclk; i++) { 459 g_autofree char *propname = g_strdup_printf("oscclk[%u]", i); 460 qdev_prop_set_uint32(sccdev, propname, mmc->oscclk[i]); 461 } 462 sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); 463 return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); 464 } 465 466 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, 467 const char *name, hwaddr size, 468 const int *irqs) 469 { 470 MPS2FPGAIO *fpgaio = opaque; 471 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 472 473 object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO); 474 qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds); 475 qdev_prop_set_bit(DEVICE(fpgaio), "has-switches", mmc->fpgaio_has_switches); 476 qdev_prop_set_bit(DEVICE(fpgaio), "has-dbgctrl", mmc->fpgaio_has_dbgctrl); 477 sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); 478 return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); 479 } 480 481 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, 482 const char *name, hwaddr size, 483 const int *irqs) 484 { 485 SysBusDevice *s; 486 NICInfo *nd = &nd_table[0]; 487 488 /* In hardware this is a LAN9220; the LAN9118 is software compatible 489 * except that it doesn't support the checksum-offload feature. 490 */ 491 qemu_check_nic_model(nd, "lan9118"); 492 mms->lan9118 = qdev_new(TYPE_LAN9118); 493 qdev_set_nic_properties(mms->lan9118, nd); 494 495 s = SYS_BUS_DEVICE(mms->lan9118); 496 sysbus_realize_and_unref(s, &error_fatal); 497 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 498 return sysbus_mmio_get_region(s, 0); 499 } 500 501 static MemoryRegion *make_eth_usb(MPS2TZMachineState *mms, void *opaque, 502 const char *name, hwaddr size, 503 const int *irqs) 504 { 505 /* 506 * The AN524 makes the ethernet and USB share a PPC port. 507 * irqs[] is the ethernet IRQ. 508 */ 509 SysBusDevice *s; 510 NICInfo *nd = &nd_table[0]; 511 512 memory_region_init(&mms->eth_usb_container, OBJECT(mms), 513 "mps2-tz-eth-usb-container", 0x200000); 514 515 /* 516 * In hardware this is a LAN9220; the LAN9118 is software compatible 517 * except that it doesn't support the checksum-offload feature. 518 */ 519 qemu_check_nic_model(nd, "lan9118"); 520 mms->lan9118 = qdev_new(TYPE_LAN9118); 521 qdev_set_nic_properties(mms->lan9118, nd); 522 523 s = SYS_BUS_DEVICE(mms->lan9118); 524 sysbus_realize_and_unref(s, &error_fatal); 525 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 526 527 memory_region_add_subregion(&mms->eth_usb_container, 528 0, sysbus_mmio_get_region(s, 0)); 529 530 /* The USB OTG controller is an ISP1763; we don't have a model of it. */ 531 object_initialize_child(OBJECT(mms), "usb-otg", 532 &mms->usb, TYPE_UNIMPLEMENTED_DEVICE); 533 qdev_prop_set_string(DEVICE(&mms->usb), "name", "usb-otg"); 534 qdev_prop_set_uint64(DEVICE(&mms->usb), "size", 0x100000); 535 s = SYS_BUS_DEVICE(&mms->usb); 536 sysbus_realize(s, &error_fatal); 537 538 memory_region_add_subregion(&mms->eth_usb_container, 539 0x100000, sysbus_mmio_get_region(s, 0)); 540 541 return &mms->eth_usb_container; 542 } 543 544 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, 545 const char *name, hwaddr size, 546 const int *irqs) 547 { 548 TZMPC *mpc = opaque; 549 int i = mpc - &mms->mpc[0]; 550 MemoryRegion *upstream; 551 const RAMInfo *raminfo = find_raminfo_for_mpc(mms, i); 552 MemoryRegion *ram = mr_for_raminfo(mms, raminfo); 553 554 object_initialize_child(OBJECT(mms), name, mpc, TYPE_TZ_MPC); 555 object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ram), 556 &error_fatal); 557 sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); 558 /* Map the upstream end of the MPC into system memory */ 559 upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); 560 memory_region_add_subregion(get_system_memory(), raminfo->base, upstream); 561 /* and connect its interrupt to the IoTKit */ 562 qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, 563 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 564 "mpcexp_status", i)); 565 566 /* Return the register interface MR for our caller to map behind the PPC */ 567 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); 568 } 569 570 static hwaddr boot_mem_base(MPS2TZMachineState *mms) 571 { 572 /* 573 * Return the canonical address of the block which will be mapped 574 * at address 0x0 (i.e. where the vector table is). 575 * This is usually 0, but if the AN524 alternate memory map is 576 * enabled it will be the base address of the QSPI block. 577 */ 578 return mms->remap ? 0x28000000 : 0; 579 } 580 581 static void remap_memory(MPS2TZMachineState *mms, int map) 582 { 583 /* 584 * Remap the memory for the AN524. 'map' is the value of 585 * SCC CFG_REG0 bit 0, i.e. 0 for the default map and 1 586 * for the "option 1" mapping where QSPI is at address 0. 587 * 588 * Effectively we need to swap around the "upstream" ends of 589 * MPC 0 and MPC 1. 590 */ 591 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 592 int i; 593 594 if (mmc->fpga_type != FPGA_AN524) { 595 return; 596 } 597 598 memory_region_transaction_begin(); 599 for (i = 0; i < 2; i++) { 600 TZMPC *mpc = &mms->mpc[i]; 601 MemoryRegion *upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); 602 hwaddr addr = (i ^ map) ? 0x28000000 : 0; 603 604 memory_region_set_address(upstream, addr); 605 } 606 memory_region_transaction_commit(); 607 } 608 609 static void remap_irq_fn(void *opaque, int n, int level) 610 { 611 MPS2TZMachineState *mms = opaque; 612 613 remap_memory(mms, level); 614 } 615 616 static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, 617 const char *name, hwaddr size, 618 const int *irqs) 619 { 620 /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */ 621 PL080State *dma = opaque; 622 int i = dma - &mms->dma[0]; 623 SysBusDevice *s; 624 char *mscname = g_strdup_printf("%s-msc", name); 625 TZMSC *msc = &mms->msc[i]; 626 DeviceState *iotkitdev = DEVICE(&mms->iotkit); 627 MemoryRegion *msc_upstream; 628 MemoryRegion *msc_downstream; 629 630 /* 631 * Each DMA device is a PL081 whose transaction master interface 632 * is guarded by a Master Security Controller. The downstream end of 633 * the MSC connects to the IoTKit AHB Slave Expansion port, so the 634 * DMA devices can see all devices and memory that the CPU does. 635 */ 636 object_initialize_child(OBJECT(mms), mscname, msc, TYPE_TZ_MSC); 637 msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0); 638 object_property_set_link(OBJECT(msc), "downstream", 639 OBJECT(msc_downstream), &error_fatal); 640 object_property_set_link(OBJECT(msc), "idau", OBJECT(mms), &error_fatal); 641 sysbus_realize(SYS_BUS_DEVICE(msc), &error_fatal); 642 643 qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0, 644 qdev_get_gpio_in_named(iotkitdev, 645 "mscexp_status", i)); 646 qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i, 647 qdev_get_gpio_in_named(DEVICE(msc), 648 "irq_clear", 0)); 649 qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i, 650 qdev_get_gpio_in_named(DEVICE(msc), 651 "cfg_nonsec", 0)); 652 qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter), 653 ARRAY_SIZE(mms->ppc) + i, 654 qdev_get_gpio_in_named(DEVICE(msc), 655 "cfg_sec_resp", 0)); 656 msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0); 657 658 object_initialize_child(OBJECT(mms), name, dma, TYPE_PL081); 659 object_property_set_link(OBJECT(dma), "downstream", OBJECT(msc_upstream), 660 &error_fatal); 661 sysbus_realize(SYS_BUS_DEVICE(dma), &error_fatal); 662 663 s = SYS_BUS_DEVICE(dma); 664 /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ 665 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 666 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); 667 sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqs[2])); 668 669 g_free(mscname); 670 return sysbus_mmio_get_region(s, 0); 671 } 672 673 static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, 674 const char *name, hwaddr size, 675 const int *irqs) 676 { 677 /* 678 * The AN505 has five PL022 SPI controllers. 679 * One of these should have the LCD controller behind it; the others 680 * are connected only to the FPGA's "general purpose SPI connector" 681 * or "shield" expansion connectors. 682 * Note that if we do implement devices behind SPI, the chip select 683 * lines are set via the "MISC" register in the MPS2 FPGAIO device. 684 */ 685 PL022State *spi = opaque; 686 SysBusDevice *s; 687 688 object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022); 689 sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal); 690 s = SYS_BUS_DEVICE(spi); 691 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); 692 return sysbus_mmio_get_region(s, 0); 693 } 694 695 static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, 696 const char *name, hwaddr size, 697 const int *irqs) 698 { 699 ArmSbconI2CState *i2c = opaque; 700 SysBusDevice *s; 701 702 object_initialize_child(OBJECT(mms), name, i2c, TYPE_ARM_SBCON_I2C); 703 s = SYS_BUS_DEVICE(i2c); 704 sysbus_realize(s, &error_fatal); 705 return sysbus_mmio_get_region(s, 0); 706 } 707 708 static MemoryRegion *make_rtc(MPS2TZMachineState *mms, void *opaque, 709 const char *name, hwaddr size, 710 const int *irqs) 711 { 712 PL031State *pl031 = opaque; 713 SysBusDevice *s; 714 715 object_initialize_child(OBJECT(mms), name, pl031, TYPE_PL031); 716 s = SYS_BUS_DEVICE(pl031); 717 sysbus_realize(s, &error_fatal); 718 /* 719 * The board docs don't give an IRQ number for the PL031, so 720 * presumably it is not connected. 721 */ 722 return sysbus_mmio_get_region(s, 0); 723 } 724 725 static void create_non_mpc_ram(MPS2TZMachineState *mms) 726 { 727 /* 728 * Handle the RAMs which are either not behind MPCs or which are 729 * aliases to another MPC. 730 */ 731 const RAMInfo *p; 732 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 733 734 for (p = mmc->raminfo; p->name; p++) { 735 if (p->flags & IS_ALIAS) { 736 SysBusDevice *mpc_sbd = SYS_BUS_DEVICE(&mms->mpc[p->mpc]); 737 MemoryRegion *upstream = sysbus_mmio_get_region(mpc_sbd, 1); 738 make_ram_alias(&mms->ram[p->mrindex], p->name, upstream, p->base); 739 } else if (p->mpc == -1) { 740 /* RAM not behind an MPC */ 741 MemoryRegion *mr = mr_for_raminfo(mms, p); 742 memory_region_add_subregion(get_system_memory(), p->base, mr); 743 } 744 } 745 } 746 747 static uint32_t boot_ram_size(MPS2TZMachineState *mms) 748 { 749 /* Return the size of the RAM block at guest address zero */ 750 const RAMInfo *p; 751 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 752 753 /* 754 * Use a per-board specification (for when the boot RAM is in 755 * the SSE and so doesn't have a RAMInfo list entry) 756 */ 757 if (mmc->boot_ram_size) { 758 return mmc->boot_ram_size; 759 } 760 761 for (p = mmc->raminfo; p->name; p++) { 762 if (p->base == boot_mem_base(mms)) { 763 return p->size; 764 } 765 } 766 g_assert_not_reached(); 767 } 768 769 static void mps2tz_common_init(MachineState *machine) 770 { 771 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); 772 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 773 MachineClass *mc = MACHINE_GET_CLASS(machine); 774 MemoryRegion *system_memory = get_system_memory(); 775 DeviceState *iotkitdev; 776 DeviceState *dev_splitter; 777 const PPCInfo *ppcs; 778 int num_ppcs; 779 int i; 780 781 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { 782 error_report("This board can only be used with CPU %s", 783 mc->default_cpu_type); 784 exit(1); 785 } 786 787 if (machine->ram_size != mc->default_ram_size) { 788 char *sz = size_to_str(mc->default_ram_size); 789 error_report("Invalid RAM size, should be %s", sz); 790 g_free(sz); 791 exit(EXIT_FAILURE); 792 } 793 794 /* These clocks don't need migration because they are fixed-frequency */ 795 mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); 796 clock_set_hz(mms->sysclk, mmc->sysclk_frq); 797 mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); 798 clock_set_hz(mms->s32kclk, S32KCLK_FRQ); 799 800 object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit, 801 mmc->armsse_type); 802 iotkitdev = DEVICE(&mms->iotkit); 803 object_property_set_link(OBJECT(&mms->iotkit), "memory", 804 OBJECT(system_memory), &error_abort); 805 qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); 806 qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor); 807 qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); 808 qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); 809 qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); 810 sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); 811 812 /* 813 * If this board has more than one CPU, then we need to create splitters 814 * to feed the IRQ inputs for each CPU in the SSE from each device in the 815 * board. If there is only one CPU, we can just wire the device IRQ 816 * directly to the SSE's IRQ input. 817 */ 818 assert(mmc->numirq <= MPS2TZ_NUMIRQ_MAX); 819 if (mc->max_cpus > 1) { 820 for (i = 0; i < mmc->numirq; i++) { 821 char *name = g_strdup_printf("mps2-irq-splitter%d", i); 822 SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; 823 824 object_initialize_child_with_props(OBJECT(machine), name, 825 splitter, sizeof(*splitter), 826 TYPE_SPLIT_IRQ, &error_fatal, 827 NULL); 828 g_free(name); 829 830 object_property_set_int(OBJECT(splitter), "num-lines", 2, 831 &error_fatal); 832 qdev_realize(DEVICE(splitter), NULL, &error_fatal); 833 qdev_connect_gpio_out(DEVICE(splitter), 0, 834 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 835 "EXP_IRQ", i)); 836 qdev_connect_gpio_out(DEVICE(splitter), 1, 837 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 838 "EXP_CPU1_IRQ", i)); 839 } 840 } 841 842 /* The sec_resp_cfg output from the IoTKit must be split into multiple 843 * lines, one for each of the PPCs we create here, plus one per MSC. 844 */ 845 object_initialize_child(OBJECT(machine), "sec-resp-splitter", 846 &mms->sec_resp_splitter, TYPE_SPLIT_IRQ); 847 object_property_set_int(OBJECT(&mms->sec_resp_splitter), "num-lines", 848 ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc), 849 &error_fatal); 850 qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal); 851 dev_splitter = DEVICE(&mms->sec_resp_splitter); 852 qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, 853 qdev_get_gpio_in(dev_splitter, 0)); 854 855 /* 856 * The IoTKit sets up much of the memory layout, including 857 * the aliases between secure and non-secure regions in the 858 * address space, and also most of the devices in the system. 859 * The FPGA itself contains various RAMs and some additional devices. 860 * The FPGA images have an odd combination of different RAMs, 861 * because in hardware they are different implementations and 862 * connected to different buses, giving varying performance/size 863 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily 864 * call the largest lump our "system memory". 865 */ 866 867 /* 868 * The overflow IRQs for all UARTs are ORed together. 869 * Tx, Rx and "combined" IRQs are sent to the NVIC separately. 870 * Create the OR gate for this: it has one input for the TX overflow 871 * and one for the RX overflow for each UART we might have. 872 * (If the board has fewer than the maximum possible number of UARTs 873 * those inputs are never wired up and are treated as always-zero.) 874 */ 875 object_initialize_child(OBJECT(mms), "uart-irq-orgate", 876 &mms->uart_irq_orgate, TYPE_OR_IRQ); 877 object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", 878 2 * ARRAY_SIZE(mms->uart), 879 &error_fatal); 880 qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); 881 qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, 882 get_sse_irq_in(mms, mmc->uart_overflow_irq)); 883 884 /* Most of the devices in the FPGA are behind Peripheral Protection 885 * Controllers. The required order for initializing things is: 886 * + initialize the PPC 887 * + initialize, configure and realize downstream devices 888 * + connect downstream device MemoryRegions to the PPC 889 * + realize the PPC 890 * + map the PPC's MemoryRegions to the places in the address map 891 * where the downstream devices should appear 892 * + wire up the PPC's control lines to the IoTKit object 893 */ 894 895 const PPCInfo an505_ppcs[] = { { 896 .name = "apb_ppcexp0", 897 .ports = { 898 { "ssram-0-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, 899 { "ssram-1-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, 900 { "ssram-2-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, 901 }, 902 }, { 903 .name = "apb_ppcexp1", 904 .ports = { 905 { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000, { 51 } }, 906 { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000, { 52 } }, 907 { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000, { 53 } }, 908 { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000, { 54 } }, 909 { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000, { 55 } }, 910 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000, { 32, 33, 42 } }, 911 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000, { 34, 35, 43 } }, 912 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000, { 36, 37, 44 } }, 913 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000, { 38, 39, 45 } }, 914 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000, { 40, 41, 46 } }, 915 { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 }, 916 { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 }, 917 { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 }, 918 { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000 }, 919 }, 920 }, { 921 .name = "apb_ppcexp2", 922 .ports = { 923 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, 924 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 925 0x40301000, 0x1000 }, 926 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, 927 }, 928 }, { 929 .name = "ahb_ppcexp0", 930 .ports = { 931 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, 932 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, 933 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, 934 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, 935 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, 936 { "eth", make_eth_dev, NULL, 0x42000000, 0x100000, { 48 } }, 937 }, 938 }, { 939 .name = "ahb_ppcexp1", 940 .ports = { 941 { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000, { 58, 56, 57 } }, 942 { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000, { 61, 59, 60 } }, 943 { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000, { 64, 62, 63 } }, 944 { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000, { 67, 65, 66 } }, 945 }, 946 }, 947 }; 948 949 const PPCInfo an524_ppcs[] = { { 950 .name = "apb_ppcexp0", 951 .ports = { 952 { "bram-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, 953 { "qspi-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, 954 { "ddr-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, 955 }, 956 }, { 957 .name = "apb_ppcexp1", 958 .ports = { 959 { "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000 }, 960 { "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000 }, 961 { "spi0", make_spi, &mms->spi[0], 0x41202000, 0x1000, { 52 } }, 962 { "spi1", make_spi, &mms->spi[1], 0x41203000, 0x1000, { 53 } }, 963 { "spi2", make_spi, &mms->spi[2], 0x41204000, 0x1000, { 54 } }, 964 { "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000 }, 965 { "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000 }, 966 { /* port 7 reserved */ }, 967 { "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000 }, 968 }, 969 }, { 970 .name = "apb_ppcexp2", 971 .ports = { 972 { "scc", make_scc, &mms->scc, 0x41300000, 0x1000 }, 973 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 974 0x41301000, 0x1000 }, 975 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x41302000, 0x1000 }, 976 { "uart0", make_uart, &mms->uart[0], 0x41303000, 0x1000, { 32, 33, 42 } }, 977 { "uart1", make_uart, &mms->uart[1], 0x41304000, 0x1000, { 34, 35, 43 } }, 978 { "uart2", make_uart, &mms->uart[2], 0x41305000, 0x1000, { 36, 37, 44 } }, 979 { "uart3", make_uart, &mms->uart[3], 0x41306000, 0x1000, { 38, 39, 45 } }, 980 { "uart4", make_uart, &mms->uart[4], 0x41307000, 0x1000, { 40, 41, 46 } }, 981 { "uart5", make_uart, &mms->uart[5], 0x41308000, 0x1000, { 124, 125, 126 } }, 982 983 { /* port 9 reserved */ }, 984 { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 }, 985 { "rtc", make_rtc, &mms->rtc, 0x4130b000, 0x1000 }, 986 }, 987 }, { 988 .name = "ahb_ppcexp0", 989 .ports = { 990 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 }, 991 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, 992 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, 993 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, 994 { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 48 } }, 995 }, 996 }, 997 }; 998 999 const PPCInfo an547_ppcs[] = { { 1000 .name = "apb_ppcexp0", 1001 .ports = { 1002 { "ssram-mpc", make_mpc, &mms->mpc[0], 0x57000000, 0x1000 }, 1003 { "qspi-mpc", make_mpc, &mms->mpc[1], 0x57001000, 0x1000 }, 1004 { "ddr-mpc", make_mpc, &mms->mpc[2], 0x57002000, 0x1000 }, 1005 }, 1006 }, { 1007 .name = "apb_ppcexp1", 1008 .ports = { 1009 { "i2c0", make_i2c, &mms->i2c[0], 0x49200000, 0x1000 }, 1010 { "i2c1", make_i2c, &mms->i2c[1], 0x49201000, 0x1000 }, 1011 { "spi0", make_spi, &mms->spi[0], 0x49202000, 0x1000, { 53 } }, 1012 { "spi1", make_spi, &mms->spi[1], 0x49203000, 0x1000, { 54 } }, 1013 { "spi2", make_spi, &mms->spi[2], 0x49204000, 0x1000, { 55 } }, 1014 { "i2c2", make_i2c, &mms->i2c[2], 0x49205000, 0x1000 }, 1015 { "i2c3", make_i2c, &mms->i2c[3], 0x49206000, 0x1000 }, 1016 { /* port 7 reserved */ }, 1017 { "i2c4", make_i2c, &mms->i2c[4], 0x49208000, 0x1000 }, 1018 }, 1019 }, { 1020 .name = "apb_ppcexp2", 1021 .ports = { 1022 { "scc", make_scc, &mms->scc, 0x49300000, 0x1000 }, 1023 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 0x49301000, 0x1000 }, 1024 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x49302000, 0x1000 }, 1025 { "uart0", make_uart, &mms->uart[0], 0x49303000, 0x1000, { 33, 34, 43 } }, 1026 { "uart1", make_uart, &mms->uart[1], 0x49304000, 0x1000, { 35, 36, 44 } }, 1027 { "uart2", make_uart, &mms->uart[2], 0x49305000, 0x1000, { 37, 38, 45 } }, 1028 { "uart3", make_uart, &mms->uart[3], 0x49306000, 0x1000, { 39, 40, 46 } }, 1029 { "uart4", make_uart, &mms->uart[4], 0x49307000, 0x1000, { 41, 42, 47 } }, 1030 { "uart5", make_uart, &mms->uart[5], 0x49308000, 0x1000, { 125, 126, 127 } }, 1031 1032 { /* port 9 reserved */ }, 1033 { "clcd", make_unimp_dev, &mms->cldc, 0x4930a000, 0x1000 }, 1034 { "rtc", make_rtc, &mms->rtc, 0x4930b000, 0x1000 }, 1035 }, 1036 }, { 1037 .name = "ahb_ppcexp0", 1038 .ports = { 1039 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 }, 1040 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, 1041 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, 1042 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, 1043 { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 49 } }, 1044 }, 1045 }, 1046 }; 1047 1048 switch (mmc->fpga_type) { 1049 case FPGA_AN505: 1050 case FPGA_AN521: 1051 ppcs = an505_ppcs; 1052 num_ppcs = ARRAY_SIZE(an505_ppcs); 1053 break; 1054 case FPGA_AN524: 1055 ppcs = an524_ppcs; 1056 num_ppcs = ARRAY_SIZE(an524_ppcs); 1057 break; 1058 case FPGA_AN547: 1059 ppcs = an547_ppcs; 1060 num_ppcs = ARRAY_SIZE(an547_ppcs); 1061 break; 1062 default: 1063 g_assert_not_reached(); 1064 } 1065 1066 for (i = 0; i < num_ppcs; i++) { 1067 const PPCInfo *ppcinfo = &ppcs[i]; 1068 TZPPC *ppc = &mms->ppc[i]; 1069 DeviceState *ppcdev; 1070 int port; 1071 char *gpioname; 1072 1073 object_initialize_child(OBJECT(machine), ppcinfo->name, ppc, 1074 TYPE_TZ_PPC); 1075 ppcdev = DEVICE(ppc); 1076 1077 for (port = 0; port < TZ_NUM_PORTS; port++) { 1078 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 1079 MemoryRegion *mr; 1080 char *portname; 1081 1082 if (!pinfo->devfn) { 1083 continue; 1084 } 1085 1086 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size, 1087 pinfo->irqs); 1088 portname = g_strdup_printf("port[%d]", port); 1089 object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), 1090 &error_fatal); 1091 g_free(portname); 1092 } 1093 1094 sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal); 1095 1096 for (port = 0; port < TZ_NUM_PORTS; port++) { 1097 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 1098 1099 if (!pinfo->devfn) { 1100 continue; 1101 } 1102 sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); 1103 1104 gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); 1105 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 1106 qdev_get_gpio_in_named(ppcdev, 1107 "cfg_nonsec", 1108 port)); 1109 g_free(gpioname); 1110 gpioname = g_strdup_printf("%s_ap", ppcinfo->name); 1111 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 1112 qdev_get_gpio_in_named(ppcdev, 1113 "cfg_ap", port)); 1114 g_free(gpioname); 1115 } 1116 1117 gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); 1118 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 1119 qdev_get_gpio_in_named(ppcdev, 1120 "irq_enable", 0)); 1121 g_free(gpioname); 1122 gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); 1123 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 1124 qdev_get_gpio_in_named(ppcdev, 1125 "irq_clear", 0)); 1126 g_free(gpioname); 1127 gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); 1128 qdev_connect_gpio_out_named(ppcdev, "irq", 0, 1129 qdev_get_gpio_in_named(iotkitdev, 1130 gpioname, 0)); 1131 g_free(gpioname); 1132 1133 qdev_connect_gpio_out(dev_splitter, i, 1134 qdev_get_gpio_in_named(ppcdev, 1135 "cfg_sec_resp", 0)); 1136 } 1137 1138 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); 1139 1140 if (mmc->fpga_type == FPGA_AN547) { 1141 create_unimplemented_device("U55 timing adapter 0", 0x48102000, 0x1000); 1142 create_unimplemented_device("U55 timing adapter 1", 0x48103000, 0x1000); 1143 } 1144 1145 create_non_mpc_ram(mms); 1146 1147 if (mmc->fpga_type == FPGA_AN524) { 1148 /* 1149 * Connect the line from the SCC so that we can remap when the 1150 * guest updates that register. 1151 */ 1152 mms->remap_irq = qemu_allocate_irq(remap_irq_fn, mms, 0); 1153 qdev_connect_gpio_out_named(DEVICE(&mms->scc), "remap", 0, 1154 mms->remap_irq); 1155 } 1156 1157 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 1158 boot_ram_size(mms)); 1159 } 1160 1161 static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, 1162 int *iregion, bool *exempt, bool *ns, bool *nsc) 1163 { 1164 /* 1165 * The MPS2 TZ FPGA images have IDAUs in them which are connected to 1166 * the Master Security Controllers. Thes have the same logic as 1167 * is used by the IoTKit for the IDAU connected to the CPU, except 1168 * that MSCs don't care about the NSC attribute. 1169 */ 1170 int region = extract32(address, 28, 4); 1171 1172 *ns = !(region & 1); 1173 *nsc = false; 1174 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 1175 *exempt = (address & 0xeff00000) == 0xe0000000; 1176 *iregion = region; 1177 } 1178 1179 static char *mps2_get_remap(Object *obj, Error **errp) 1180 { 1181 MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); 1182 const char *val = mms->remap ? "QSPI" : "BRAM"; 1183 return g_strdup(val); 1184 } 1185 1186 static void mps2_set_remap(Object *obj, const char *value, Error **errp) 1187 { 1188 MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); 1189 1190 if (!strcmp(value, "BRAM")) { 1191 mms->remap = false; 1192 } else if (!strcmp(value, "QSPI")) { 1193 mms->remap = true; 1194 } else { 1195 error_setg(errp, "Invalid remap value"); 1196 error_append_hint(errp, "Valid values are BRAM and QSPI.\n"); 1197 } 1198 } 1199 1200 static void mps2_machine_reset(MachineState *machine) 1201 { 1202 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); 1203 1204 /* 1205 * Set the initial memory mapping before triggering the reset of 1206 * the rest of the system, so that the guest image loader and CPU 1207 * reset see the correct mapping. 1208 */ 1209 remap_memory(mms, mms->remap); 1210 qemu_devices_reset(); 1211 } 1212 1213 static void mps2tz_class_init(ObjectClass *oc, void *data) 1214 { 1215 MachineClass *mc = MACHINE_CLASS(oc); 1216 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); 1217 1218 mc->init = mps2tz_common_init; 1219 mc->reset = mps2_machine_reset; 1220 iic->check = mps2_tz_idau_check; 1221 } 1222 1223 static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc) 1224 { 1225 /* 1226 * Set mc->default_ram_size and default_ram_id from the 1227 * information in mmc->raminfo. 1228 */ 1229 MachineClass *mc = MACHINE_CLASS(mmc); 1230 const RAMInfo *p; 1231 1232 for (p = mmc->raminfo; p->name; p++) { 1233 if (p->mrindex < 0) { 1234 /* Found the entry for "system memory" */ 1235 mc->default_ram_size = p->size; 1236 mc->default_ram_id = p->name; 1237 return; 1238 } 1239 } 1240 g_assert_not_reached(); 1241 } 1242 1243 static void mps2tz_an505_class_init(ObjectClass *oc, void *data) 1244 { 1245 MachineClass *mc = MACHINE_CLASS(oc); 1246 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1247 1248 mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; 1249 mc->default_cpus = 1; 1250 mc->min_cpus = mc->default_cpus; 1251 mc->max_cpus = mc->default_cpus; 1252 mmc->fpga_type = FPGA_AN505; 1253 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 1254 mmc->scc_id = 0x41045050; 1255 mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ 1256 mmc->apb_periph_frq = mmc->sysclk_frq; 1257 mmc->oscclk = an505_oscclk; 1258 mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); 1259 mmc->fpgaio_num_leds = 2; 1260 mmc->fpgaio_has_switches = false; 1261 mmc->fpgaio_has_dbgctrl = false; 1262 mmc->numirq = 92; 1263 mmc->uart_overflow_irq = 47; 1264 mmc->init_svtor = 0x10000000; 1265 mmc->sram_addr_width = 15; 1266 mmc->raminfo = an505_raminfo; 1267 mmc->armsse_type = TYPE_IOTKIT; 1268 mmc->boot_ram_size = 0; 1269 mps2tz_set_default_ram_info(mmc); 1270 } 1271 1272 static void mps2tz_an521_class_init(ObjectClass *oc, void *data) 1273 { 1274 MachineClass *mc = MACHINE_CLASS(oc); 1275 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1276 1277 mc->desc = "ARM MPS2 with AN521 FPGA image for dual Cortex-M33"; 1278 mc->default_cpus = 2; 1279 mc->min_cpus = mc->default_cpus; 1280 mc->max_cpus = mc->default_cpus; 1281 mmc->fpga_type = FPGA_AN521; 1282 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 1283 mmc->scc_id = 0x41045210; 1284 mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ 1285 mmc->apb_periph_frq = mmc->sysclk_frq; 1286 mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */ 1287 mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); 1288 mmc->fpgaio_num_leds = 2; 1289 mmc->fpgaio_has_switches = false; 1290 mmc->fpgaio_has_dbgctrl = false; 1291 mmc->numirq = 92; 1292 mmc->uart_overflow_irq = 47; 1293 mmc->init_svtor = 0x10000000; 1294 mmc->sram_addr_width = 15; 1295 mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */ 1296 mmc->armsse_type = TYPE_SSE200; 1297 mmc->boot_ram_size = 0; 1298 mps2tz_set_default_ram_info(mmc); 1299 } 1300 1301 static void mps3tz_an524_class_init(ObjectClass *oc, void *data) 1302 { 1303 MachineClass *mc = MACHINE_CLASS(oc); 1304 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1305 1306 mc->desc = "ARM MPS3 with AN524 FPGA image for dual Cortex-M33"; 1307 mc->default_cpus = 2; 1308 mc->min_cpus = mc->default_cpus; 1309 mc->max_cpus = mc->default_cpus; 1310 mmc->fpga_type = FPGA_AN524; 1311 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 1312 mmc->scc_id = 0x41045240; 1313 mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */ 1314 mmc->apb_periph_frq = mmc->sysclk_frq; 1315 mmc->oscclk = an524_oscclk; 1316 mmc->len_oscclk = ARRAY_SIZE(an524_oscclk); 1317 mmc->fpgaio_num_leds = 10; 1318 mmc->fpgaio_has_switches = true; 1319 mmc->fpgaio_has_dbgctrl = false; 1320 mmc->numirq = 95; 1321 mmc->uart_overflow_irq = 47; 1322 mmc->init_svtor = 0x10000000; 1323 mmc->sram_addr_width = 15; 1324 mmc->raminfo = an524_raminfo; 1325 mmc->armsse_type = TYPE_SSE200; 1326 mmc->boot_ram_size = 0; 1327 mps2tz_set_default_ram_info(mmc); 1328 1329 object_class_property_add_str(oc, "remap", mps2_get_remap, mps2_set_remap); 1330 object_class_property_set_description(oc, "remap", 1331 "Set memory mapping. Valid values " 1332 "are BRAM (default) and QSPI."); 1333 } 1334 1335 static void mps3tz_an547_class_init(ObjectClass *oc, void *data) 1336 { 1337 MachineClass *mc = MACHINE_CLASS(oc); 1338 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 1339 1340 mc->desc = "ARM MPS3 with AN547 FPGA image for Cortex-M55"; 1341 mc->default_cpus = 1; 1342 mc->min_cpus = mc->default_cpus; 1343 mc->max_cpus = mc->default_cpus; 1344 mmc->fpga_type = FPGA_AN547; 1345 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m55"); 1346 mmc->scc_id = 0x41055470; 1347 mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */ 1348 mmc->apb_periph_frq = 25 * 1000 * 1000; /* 25MHz */ 1349 mmc->oscclk = an524_oscclk; /* same as AN524 */ 1350 mmc->len_oscclk = ARRAY_SIZE(an524_oscclk); 1351 mmc->fpgaio_num_leds = 10; 1352 mmc->fpgaio_has_switches = true; 1353 mmc->fpgaio_has_dbgctrl = true; 1354 mmc->numirq = 96; 1355 mmc->uart_overflow_irq = 48; 1356 mmc->init_svtor = 0x00000000; 1357 mmc->sram_addr_width = 21; 1358 mmc->raminfo = an547_raminfo; 1359 mmc->armsse_type = TYPE_SSE300; 1360 mmc->boot_ram_size = 512 * KiB; 1361 mps2tz_set_default_ram_info(mmc); 1362 } 1363 1364 static const TypeInfo mps2tz_info = { 1365 .name = TYPE_MPS2TZ_MACHINE, 1366 .parent = TYPE_MACHINE, 1367 .abstract = true, 1368 .instance_size = sizeof(MPS2TZMachineState), 1369 .class_size = sizeof(MPS2TZMachineClass), 1370 .class_init = mps2tz_class_init, 1371 .interfaces = (InterfaceInfo[]) { 1372 { TYPE_IDAU_INTERFACE }, 1373 { } 1374 }, 1375 }; 1376 1377 static const TypeInfo mps2tz_an505_info = { 1378 .name = TYPE_MPS2TZ_AN505_MACHINE, 1379 .parent = TYPE_MPS2TZ_MACHINE, 1380 .class_init = mps2tz_an505_class_init, 1381 }; 1382 1383 static const TypeInfo mps2tz_an521_info = { 1384 .name = TYPE_MPS2TZ_AN521_MACHINE, 1385 .parent = TYPE_MPS2TZ_MACHINE, 1386 .class_init = mps2tz_an521_class_init, 1387 }; 1388 1389 static const TypeInfo mps3tz_an524_info = { 1390 .name = TYPE_MPS3TZ_AN524_MACHINE, 1391 .parent = TYPE_MPS2TZ_MACHINE, 1392 .class_init = mps3tz_an524_class_init, 1393 }; 1394 1395 static const TypeInfo mps3tz_an547_info = { 1396 .name = TYPE_MPS3TZ_AN547_MACHINE, 1397 .parent = TYPE_MPS2TZ_MACHINE, 1398 .class_init = mps3tz_an547_class_init, 1399 }; 1400 1401 static void mps2tz_machine_init(void) 1402 { 1403 type_register_static(&mps2tz_info); 1404 type_register_static(&mps2tz_an505_info); 1405 type_register_static(&mps2tz_an521_info); 1406 type_register_static(&mps3tz_an524_info); 1407 type_register_static(&mps3tz_an547_info); 1408 } 1409 1410 type_init(mps2tz_machine_init); 1411