1 /* 2 * ARM V2M MPS2 board emulation, trustzone aware FPGA images 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger 13 * FPGA but is otherwise the same as the 2). Since the CPU itself 14 * and most of the devices are in the FPGA, the details of the board 15 * as seen by the guest depend significantly on the FPGA image. 16 * This source file covers the following FPGA images, for TrustZone cores: 17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 18 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521 19 * 20 * Links to the TRM for the board itself and to the various Application 21 * Notes which document the FPGA images can be found here: 22 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 23 * 24 * Board TRM: 25 * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf 26 * Application Note AN505: 27 * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html 28 * Application Note AN521: 29 * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html 30 * 31 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide 32 * (ARM ECM0601256) for the details of some of the device layout: 33 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html 34 * Similarly, the AN521 uses the SSE-200, and the SSE-200 TRM defines 35 * most of the device layout: 36 * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf 37 * 38 */ 39 40 #include "qemu/osdep.h" 41 #include "qemu/units.h" 42 #include "qemu/cutils.h" 43 #include "qapi/error.h" 44 #include "qemu/error-report.h" 45 #include "hw/arm/boot.h" 46 #include "hw/arm/armv7m.h" 47 #include "hw/or-irq.h" 48 #include "hw/boards.h" 49 #include "exec/address-spaces.h" 50 #include "sysemu/sysemu.h" 51 #include "hw/misc/unimp.h" 52 #include "hw/char/cmsdk-apb-uart.h" 53 #include "hw/timer/cmsdk-apb-timer.h" 54 #include "hw/misc/mps2-scc.h" 55 #include "hw/misc/mps2-fpgaio.h" 56 #include "hw/misc/tz-mpc.h" 57 #include "hw/misc/tz-msc.h" 58 #include "hw/arm/armsse.h" 59 #include "hw/dma/pl080.h" 60 #include "hw/ssi/pl022.h" 61 #include "hw/net/lan9118.h" 62 #include "net/net.h" 63 #include "hw/core/split-irq.h" 64 65 #define MPS2TZ_NUMIRQ 92 66 67 typedef enum MPS2TZFPGAType { 68 FPGA_AN505, 69 FPGA_AN521, 70 } MPS2TZFPGAType; 71 72 typedef struct { 73 MachineClass parent; 74 MPS2TZFPGAType fpga_type; 75 uint32_t scc_id; 76 const char *armsse_type; 77 } MPS2TZMachineClass; 78 79 typedef struct { 80 MachineState parent; 81 82 ARMSSE iotkit; 83 MemoryRegion ssram[3]; 84 MemoryRegion ssram1_m; 85 MPS2SCC scc; 86 MPS2FPGAIO fpgaio; 87 TZPPC ppc[5]; 88 TZMPC ssram_mpc[3]; 89 PL022State spi[5]; 90 UnimplementedDeviceState i2c[4]; 91 UnimplementedDeviceState i2s_audio; 92 UnimplementedDeviceState gpio[4]; 93 UnimplementedDeviceState gfx; 94 PL080State dma[4]; 95 TZMSC msc[4]; 96 CMSDKAPBUART uart[5]; 97 SplitIRQ sec_resp_splitter; 98 qemu_or_irq uart_irq_orgate; 99 DeviceState *lan9118; 100 SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ]; 101 } MPS2TZMachineState; 102 103 #define TYPE_MPS2TZ_MACHINE "mps2tz" 104 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") 105 #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") 106 107 #define MPS2TZ_MACHINE(obj) \ 108 OBJECT_CHECK(MPS2TZMachineState, obj, TYPE_MPS2TZ_MACHINE) 109 #define MPS2TZ_MACHINE_GET_CLASS(obj) \ 110 OBJECT_GET_CLASS(MPS2TZMachineClass, obj, TYPE_MPS2TZ_MACHINE) 111 #define MPS2TZ_MACHINE_CLASS(klass) \ 112 OBJECT_CLASS_CHECK(MPS2TZMachineClass, klass, TYPE_MPS2TZ_MACHINE) 113 114 /* Main SYSCLK frequency in Hz */ 115 #define SYSCLK_FRQ 20000000 116 117 /* Create an alias of an entire original MemoryRegion @orig 118 * located at @base in the memory map. 119 */ 120 static void make_ram_alias(MemoryRegion *mr, const char *name, 121 MemoryRegion *orig, hwaddr base) 122 { 123 memory_region_init_alias(mr, NULL, name, orig, 0, 124 memory_region_size(orig)); 125 memory_region_add_subregion(get_system_memory(), base, mr); 126 } 127 128 static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) 129 { 130 /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ 131 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 132 133 assert(irqno < MPS2TZ_NUMIRQ); 134 135 switch (mmc->fpga_type) { 136 case FPGA_AN505: 137 return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno); 138 case FPGA_AN521: 139 return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); 140 default: 141 g_assert_not_reached(); 142 } 143 } 144 145 /* Most of the devices in the AN505 FPGA image sit behind 146 * Peripheral Protection Controllers. These data structures 147 * define the layout of which devices sit behind which PPCs. 148 * The devfn for each port is a function which creates, configures 149 * and initializes the device, returning the MemoryRegion which 150 * needs to be plugged into the downstream end of the PPC port. 151 */ 152 typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, 153 const char *name, hwaddr size); 154 155 typedef struct PPCPortInfo { 156 const char *name; 157 MakeDevFn *devfn; 158 void *opaque; 159 hwaddr addr; 160 hwaddr size; 161 } PPCPortInfo; 162 163 typedef struct PPCInfo { 164 const char *name; 165 PPCPortInfo ports[TZ_NUM_PORTS]; 166 } PPCInfo; 167 168 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, 169 void *opaque, 170 const char *name, hwaddr size) 171 { 172 /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, 173 * and return a pointer to its MemoryRegion. 174 */ 175 UnimplementedDeviceState *uds = opaque; 176 177 object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE); 178 qdev_prop_set_string(DEVICE(uds), "name", name); 179 qdev_prop_set_uint64(DEVICE(uds), "size", size); 180 sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); 181 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); 182 } 183 184 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, 185 const char *name, hwaddr size) 186 { 187 CMSDKAPBUART *uart = opaque; 188 int i = uart - &mms->uart[0]; 189 int rxirqno = i * 2; 190 int txirqno = i * 2 + 1; 191 int combirqno = i + 10; 192 SysBusDevice *s; 193 DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); 194 195 object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART); 196 qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); 197 qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); 198 sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); 199 s = SYS_BUS_DEVICE(uart); 200 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno)); 201 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno)); 202 sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); 203 sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); 204 sysbus_connect_irq(s, 4, get_sse_irq_in(mms, combirqno)); 205 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); 206 } 207 208 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, 209 const char *name, hwaddr size) 210 { 211 MPS2SCC *scc = opaque; 212 DeviceState *sccdev; 213 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 214 215 object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); 216 sccdev = DEVICE(scc); 217 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); 218 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); 219 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); 220 sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); 221 return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); 222 } 223 224 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, 225 const char *name, hwaddr size) 226 { 227 MPS2FPGAIO *fpgaio = opaque; 228 229 object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO); 230 sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); 231 return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); 232 } 233 234 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, 235 const char *name, hwaddr size) 236 { 237 SysBusDevice *s; 238 NICInfo *nd = &nd_table[0]; 239 240 /* In hardware this is a LAN9220; the LAN9118 is software compatible 241 * except that it doesn't support the checksum-offload feature. 242 */ 243 qemu_check_nic_model(nd, "lan9118"); 244 mms->lan9118 = qdev_new(TYPE_LAN9118); 245 qdev_set_nic_properties(mms->lan9118, nd); 246 247 s = SYS_BUS_DEVICE(mms->lan9118); 248 sysbus_realize_and_unref(s, &error_fatal); 249 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16)); 250 return sysbus_mmio_get_region(s, 0); 251 } 252 253 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, 254 const char *name, hwaddr size) 255 { 256 TZMPC *mpc = opaque; 257 int i = mpc - &mms->ssram_mpc[0]; 258 MemoryRegion *ssram = &mms->ssram[i]; 259 MemoryRegion *upstream; 260 char *mpcname = g_strdup_printf("%s-mpc", name); 261 static uint32_t ramsize[] = { 0x00400000, 0x00200000, 0x00200000 }; 262 static uint32_t rambase[] = { 0x00000000, 0x28000000, 0x28200000 }; 263 264 memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal); 265 266 object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC); 267 object_property_set_link(OBJECT(mpc), OBJECT(ssram), 268 "downstream", &error_fatal); 269 sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); 270 /* Map the upstream end of the MPC into system memory */ 271 upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); 272 memory_region_add_subregion(get_system_memory(), rambase[i], upstream); 273 /* and connect its interrupt to the IoTKit */ 274 qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, 275 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 276 "mpcexp_status", i)); 277 278 /* The first SSRAM is a special case as it has an alias; accesses to 279 * the alias region at 0x00400000 must also go to the MPC upstream. 280 */ 281 if (i == 0) { 282 make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x00400000); 283 } 284 285 g_free(mpcname); 286 /* Return the register interface MR for our caller to map behind the PPC */ 287 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); 288 } 289 290 static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, 291 const char *name, hwaddr size) 292 { 293 PL080State *dma = opaque; 294 int i = dma - &mms->dma[0]; 295 SysBusDevice *s; 296 char *mscname = g_strdup_printf("%s-msc", name); 297 TZMSC *msc = &mms->msc[i]; 298 DeviceState *iotkitdev = DEVICE(&mms->iotkit); 299 MemoryRegion *msc_upstream; 300 MemoryRegion *msc_downstream; 301 302 /* 303 * Each DMA device is a PL081 whose transaction master interface 304 * is guarded by a Master Security Controller. The downstream end of 305 * the MSC connects to the IoTKit AHB Slave Expansion port, so the 306 * DMA devices can see all devices and memory that the CPU does. 307 */ 308 object_initialize_child(OBJECT(mms), mscname, msc, TYPE_TZ_MSC); 309 msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0); 310 object_property_set_link(OBJECT(msc), OBJECT(msc_downstream), 311 "downstream", &error_fatal); 312 object_property_set_link(OBJECT(msc), OBJECT(mms), 313 "idau", &error_fatal); 314 sysbus_realize(SYS_BUS_DEVICE(msc), &error_fatal); 315 316 qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0, 317 qdev_get_gpio_in_named(iotkitdev, 318 "mscexp_status", i)); 319 qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i, 320 qdev_get_gpio_in_named(DEVICE(msc), 321 "irq_clear", 0)); 322 qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i, 323 qdev_get_gpio_in_named(DEVICE(msc), 324 "cfg_nonsec", 0)); 325 qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter), 326 ARRAY_SIZE(mms->ppc) + i, 327 qdev_get_gpio_in_named(DEVICE(msc), 328 "cfg_sec_resp", 0)); 329 msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0); 330 331 object_initialize_child(OBJECT(mms), name, dma, TYPE_PL081); 332 object_property_set_link(OBJECT(dma), OBJECT(msc_upstream), 333 "downstream", &error_fatal); 334 sysbus_realize(SYS_BUS_DEVICE(dma), &error_fatal); 335 336 s = SYS_BUS_DEVICE(dma); 337 /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ 338 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 58 + i * 3)); 339 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, 56 + i * 3)); 340 sysbus_connect_irq(s, 2, get_sse_irq_in(mms, 57 + i * 3)); 341 342 g_free(mscname); 343 return sysbus_mmio_get_region(s, 0); 344 } 345 346 static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, 347 const char *name, hwaddr size) 348 { 349 /* 350 * The AN505 has five PL022 SPI controllers. 351 * One of these should have the LCD controller behind it; the others 352 * are connected only to the FPGA's "general purpose SPI connector" 353 * or "shield" expansion connectors. 354 * Note that if we do implement devices behind SPI, the chip select 355 * lines are set via the "MISC" register in the MPS2 FPGAIO device. 356 */ 357 PL022State *spi = opaque; 358 int i = spi - &mms->spi[0]; 359 SysBusDevice *s; 360 361 object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022); 362 sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal); 363 s = SYS_BUS_DEVICE(spi); 364 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 51 + i)); 365 return sysbus_mmio_get_region(s, 0); 366 } 367 368 static void mps2tz_common_init(MachineState *machine) 369 { 370 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); 371 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 372 MachineClass *mc = MACHINE_GET_CLASS(machine); 373 MemoryRegion *system_memory = get_system_memory(); 374 DeviceState *iotkitdev; 375 DeviceState *dev_splitter; 376 int i; 377 378 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { 379 error_report("This board can only be used with CPU %s", 380 mc->default_cpu_type); 381 exit(1); 382 } 383 384 if (machine->ram_size != mc->default_ram_size) { 385 char *sz = size_to_str(mc->default_ram_size); 386 error_report("Invalid RAM size, should be %s", sz); 387 g_free(sz); 388 exit(EXIT_FAILURE); 389 } 390 391 object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit, 392 mmc->armsse_type); 393 iotkitdev = DEVICE(&mms->iotkit); 394 object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory), 395 "memory", &error_abort); 396 qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); 397 qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); 398 sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); 399 400 /* 401 * The AN521 needs us to create splitters to feed the IRQ inputs 402 * for each CPU in the SSE-200 from each device in the board. 403 */ 404 if (mmc->fpga_type == FPGA_AN521) { 405 for (i = 0; i < MPS2TZ_NUMIRQ; i++) { 406 char *name = g_strdup_printf("mps2-irq-splitter%d", i); 407 SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; 408 409 object_initialize_child_with_props(OBJECT(machine), name, 410 splitter, sizeof(*splitter), 411 TYPE_SPLIT_IRQ, &error_fatal, 412 NULL); 413 g_free(name); 414 415 object_property_set_int(OBJECT(splitter), 2, "num-lines", 416 &error_fatal); 417 qdev_realize(DEVICE(splitter), NULL, &error_fatal); 418 qdev_connect_gpio_out(DEVICE(splitter), 0, 419 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 420 "EXP_IRQ", i)); 421 qdev_connect_gpio_out(DEVICE(splitter), 1, 422 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 423 "EXP_CPU1_IRQ", i)); 424 } 425 } 426 427 /* The sec_resp_cfg output from the IoTKit must be split into multiple 428 * lines, one for each of the PPCs we create here, plus one per MSC. 429 */ 430 object_initialize_child(OBJECT(machine), "sec-resp-splitter", 431 &mms->sec_resp_splitter, TYPE_SPLIT_IRQ); 432 object_property_set_int(OBJECT(&mms->sec_resp_splitter), 433 ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc), 434 "num-lines", &error_fatal); 435 qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal); 436 dev_splitter = DEVICE(&mms->sec_resp_splitter); 437 qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, 438 qdev_get_gpio_in(dev_splitter, 0)); 439 440 /* The IoTKit sets up much of the memory layout, including 441 * the aliases between secure and non-secure regions in the 442 * address space. The FPGA itself contains: 443 * 444 * 0x00000000..0x003fffff SSRAM1 445 * 0x00400000..0x007fffff alias of SSRAM1 446 * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3 447 * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices 448 * 0x80000000..0x80ffffff 16MB PSRAM 449 */ 450 451 /* The FPGA images have an odd combination of different RAMs, 452 * because in hardware they are different implementations and 453 * connected to different buses, giving varying performance/size 454 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily 455 * call the 16MB our "system memory", as it's the largest lump. 456 */ 457 memory_region_add_subregion(system_memory, 0x80000000, machine->ram); 458 459 /* The overflow IRQs for all UARTs are ORed together. 460 * Tx, Rx and "combined" IRQs are sent to the NVIC separately. 461 * Create the OR gate for this. 462 */ 463 object_initialize_child(OBJECT(mms), "uart-irq-orgate", 464 &mms->uart_irq_orgate, TYPE_OR_IRQ); 465 object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines", 466 &error_fatal); 467 qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); 468 qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, 469 get_sse_irq_in(mms, 15)); 470 471 /* Most of the devices in the FPGA are behind Peripheral Protection 472 * Controllers. The required order for initializing things is: 473 * + initialize the PPC 474 * + initialize, configure and realize downstream devices 475 * + connect downstream device MemoryRegions to the PPC 476 * + realize the PPC 477 * + map the PPC's MemoryRegions to the places in the address map 478 * where the downstream devices should appear 479 * + wire up the PPC's control lines to the IoTKit object 480 */ 481 482 const PPCInfo ppcs[] = { { 483 .name = "apb_ppcexp0", 484 .ports = { 485 { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 }, 486 { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1000 }, 487 { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1000 }, 488 }, 489 }, { 490 .name = "apb_ppcexp1", 491 .ports = { 492 { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000 }, 493 { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000 }, 494 { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000 }, 495 { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000 }, 496 { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000 }, 497 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 }, 498 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 }, 499 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 }, 500 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 }, 501 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 }, 502 { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40207000, 0x1000 }, 503 { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40208000, 0x1000 }, 504 { "i2c2", make_unimp_dev, &mms->i2c[2], 0x4020c000, 0x1000 }, 505 { "i2c3", make_unimp_dev, &mms->i2c[3], 0x4020d000, 0x1000 }, 506 }, 507 }, { 508 .name = "apb_ppcexp2", 509 .ports = { 510 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, 511 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 512 0x40301000, 0x1000 }, 513 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, 514 }, 515 }, { 516 .name = "ahb_ppcexp0", 517 .ports = { 518 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, 519 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, 520 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, 521 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, 522 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, 523 { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 }, 524 }, 525 }, { 526 .name = "ahb_ppcexp1", 527 .ports = { 528 { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000 }, 529 { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000 }, 530 { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000 }, 531 { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000 }, 532 }, 533 }, 534 }; 535 536 for (i = 0; i < ARRAY_SIZE(ppcs); i++) { 537 const PPCInfo *ppcinfo = &ppcs[i]; 538 TZPPC *ppc = &mms->ppc[i]; 539 DeviceState *ppcdev; 540 int port; 541 char *gpioname; 542 543 object_initialize_child(OBJECT(machine), ppcinfo->name, ppc, 544 TYPE_TZ_PPC); 545 ppcdev = DEVICE(ppc); 546 547 for (port = 0; port < TZ_NUM_PORTS; port++) { 548 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 549 MemoryRegion *mr; 550 char *portname; 551 552 if (!pinfo->devfn) { 553 continue; 554 } 555 556 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); 557 portname = g_strdup_printf("port[%d]", port); 558 object_property_set_link(OBJECT(ppc), OBJECT(mr), 559 portname, &error_fatal); 560 g_free(portname); 561 } 562 563 sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal); 564 565 for (port = 0; port < TZ_NUM_PORTS; port++) { 566 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 567 568 if (!pinfo->devfn) { 569 continue; 570 } 571 sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); 572 573 gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); 574 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 575 qdev_get_gpio_in_named(ppcdev, 576 "cfg_nonsec", 577 port)); 578 g_free(gpioname); 579 gpioname = g_strdup_printf("%s_ap", ppcinfo->name); 580 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 581 qdev_get_gpio_in_named(ppcdev, 582 "cfg_ap", port)); 583 g_free(gpioname); 584 } 585 586 gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); 587 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 588 qdev_get_gpio_in_named(ppcdev, 589 "irq_enable", 0)); 590 g_free(gpioname); 591 gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); 592 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 593 qdev_get_gpio_in_named(ppcdev, 594 "irq_clear", 0)); 595 g_free(gpioname); 596 gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); 597 qdev_connect_gpio_out_named(ppcdev, "irq", 0, 598 qdev_get_gpio_in_named(iotkitdev, 599 gpioname, 0)); 600 g_free(gpioname); 601 602 qdev_connect_gpio_out(dev_splitter, i, 603 qdev_get_gpio_in_named(ppcdev, 604 "cfg_sec_resp", 0)); 605 } 606 607 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); 608 609 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); 610 } 611 612 static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, 613 int *iregion, bool *exempt, bool *ns, bool *nsc) 614 { 615 /* 616 * The MPS2 TZ FPGA images have IDAUs in them which are connected to 617 * the Master Security Controllers. Thes have the same logic as 618 * is used by the IoTKit for the IDAU connected to the CPU, except 619 * that MSCs don't care about the NSC attribute. 620 */ 621 int region = extract32(address, 28, 4); 622 623 *ns = !(region & 1); 624 *nsc = false; 625 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 626 *exempt = (address & 0xeff00000) == 0xe0000000; 627 *iregion = region; 628 } 629 630 static void mps2tz_class_init(ObjectClass *oc, void *data) 631 { 632 MachineClass *mc = MACHINE_CLASS(oc); 633 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); 634 635 mc->init = mps2tz_common_init; 636 iic->check = mps2_tz_idau_check; 637 mc->default_ram_size = 16 * MiB; 638 mc->default_ram_id = "mps.ram"; 639 } 640 641 static void mps2tz_an505_class_init(ObjectClass *oc, void *data) 642 { 643 MachineClass *mc = MACHINE_CLASS(oc); 644 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 645 646 mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; 647 mc->default_cpus = 1; 648 mc->min_cpus = mc->default_cpus; 649 mc->max_cpus = mc->default_cpus; 650 mmc->fpga_type = FPGA_AN505; 651 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 652 mmc->scc_id = 0x41045050; 653 mmc->armsse_type = TYPE_IOTKIT; 654 } 655 656 static void mps2tz_an521_class_init(ObjectClass *oc, void *data) 657 { 658 MachineClass *mc = MACHINE_CLASS(oc); 659 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 660 661 mc->desc = "ARM MPS2 with AN521 FPGA image for dual Cortex-M33"; 662 mc->default_cpus = 2; 663 mc->min_cpus = mc->default_cpus; 664 mc->max_cpus = mc->default_cpus; 665 mmc->fpga_type = FPGA_AN521; 666 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 667 mmc->scc_id = 0x41045210; 668 mmc->armsse_type = TYPE_SSE200; 669 } 670 671 static const TypeInfo mps2tz_info = { 672 .name = TYPE_MPS2TZ_MACHINE, 673 .parent = TYPE_MACHINE, 674 .abstract = true, 675 .instance_size = sizeof(MPS2TZMachineState), 676 .class_size = sizeof(MPS2TZMachineClass), 677 .class_init = mps2tz_class_init, 678 .interfaces = (InterfaceInfo[]) { 679 { TYPE_IDAU_INTERFACE }, 680 { } 681 }, 682 }; 683 684 static const TypeInfo mps2tz_an505_info = { 685 .name = TYPE_MPS2TZ_AN505_MACHINE, 686 .parent = TYPE_MPS2TZ_MACHINE, 687 .class_init = mps2tz_an505_class_init, 688 }; 689 690 static const TypeInfo mps2tz_an521_info = { 691 .name = TYPE_MPS2TZ_AN521_MACHINE, 692 .parent = TYPE_MPS2TZ_MACHINE, 693 .class_init = mps2tz_an521_class_init, 694 }; 695 696 static void mps2tz_machine_init(void) 697 { 698 type_register_static(&mps2tz_info); 699 type_register_static(&mps2tz_an505_info); 700 type_register_static(&mps2tz_an521_info); 701 } 702 703 type_init(mps2tz_machine_init); 704