1 /* 2 * ARM V2M MPS2 board emulation, trustzone aware FPGA images 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger 13 * FPGA but is otherwise the same as the 2). Since the CPU itself 14 * and most of the devices are in the FPGA, the details of the board 15 * as seen by the guest depend significantly on the FPGA image. 16 * This source file covers the following FPGA images, for TrustZone cores: 17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 18 * 19 * Links to the TRM for the board itself and to the various Application 20 * Notes which document the FPGA images can be found here: 21 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 22 * 23 * Board TRM: 24 * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf 25 * Application Note AN505: 26 * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html 27 * 28 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide 29 * (ARM ECM0601256) for the details of some of the device layout: 30 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html 31 */ 32 33 #include "qemu/osdep.h" 34 #include "qapi/error.h" 35 #include "qemu/error-report.h" 36 #include "hw/arm/arm.h" 37 #include "hw/arm/armv7m.h" 38 #include "hw/or-irq.h" 39 #include "hw/boards.h" 40 #include "exec/address-spaces.h" 41 #include "sysemu/sysemu.h" 42 #include "hw/misc/unimp.h" 43 #include "hw/char/cmsdk-apb-uart.h" 44 #include "hw/timer/cmsdk-apb-timer.h" 45 #include "hw/misc/mps2-scc.h" 46 #include "hw/misc/mps2-fpgaio.h" 47 #include "hw/misc/tz-mpc.h" 48 #include "hw/arm/iotkit.h" 49 #include "hw/devices.h" 50 #include "net/net.h" 51 #include "hw/core/split-irq.h" 52 53 typedef enum MPS2TZFPGAType { 54 FPGA_AN505, 55 } MPS2TZFPGAType; 56 57 typedef struct { 58 MachineClass parent; 59 MPS2TZFPGAType fpga_type; 60 uint32_t scc_id; 61 } MPS2TZMachineClass; 62 63 typedef struct { 64 MachineState parent; 65 66 IoTKit iotkit; 67 MemoryRegion psram; 68 MemoryRegion ssram[3]; 69 MemoryRegion ssram1_m; 70 MPS2SCC scc; 71 MPS2FPGAIO fpgaio; 72 TZPPC ppc[5]; 73 TZMPC ssram_mpc[3]; 74 UnimplementedDeviceState spi[5]; 75 UnimplementedDeviceState i2c[4]; 76 UnimplementedDeviceState i2s_audio; 77 UnimplementedDeviceState gpio[4]; 78 UnimplementedDeviceState dma[4]; 79 UnimplementedDeviceState gfx; 80 CMSDKAPBUART uart[5]; 81 SplitIRQ sec_resp_splitter; 82 qemu_or_irq uart_irq_orgate; 83 DeviceState *lan9118; 84 } MPS2TZMachineState; 85 86 #define TYPE_MPS2TZ_MACHINE "mps2tz" 87 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") 88 89 #define MPS2TZ_MACHINE(obj) \ 90 OBJECT_CHECK(MPS2TZMachineState, obj, TYPE_MPS2TZ_MACHINE) 91 #define MPS2TZ_MACHINE_GET_CLASS(obj) \ 92 OBJECT_GET_CLASS(MPS2TZMachineClass, obj, TYPE_MPS2TZ_MACHINE) 93 #define MPS2TZ_MACHINE_CLASS(klass) \ 94 OBJECT_CLASS_CHECK(MPS2TZMachineClass, klass, TYPE_MPS2TZ_MACHINE) 95 96 /* Main SYSCLK frequency in Hz */ 97 #define SYSCLK_FRQ 20000000 98 99 /* Create an alias of an entire original MemoryRegion @orig 100 * located at @base in the memory map. 101 */ 102 static void make_ram_alias(MemoryRegion *mr, const char *name, 103 MemoryRegion *orig, hwaddr base) 104 { 105 memory_region_init_alias(mr, NULL, name, orig, 0, 106 memory_region_size(orig)); 107 memory_region_add_subregion(get_system_memory(), base, mr); 108 } 109 110 /* Most of the devices in the AN505 FPGA image sit behind 111 * Peripheral Protection Controllers. These data structures 112 * define the layout of which devices sit behind which PPCs. 113 * The devfn for each port is a function which creates, configures 114 * and initializes the device, returning the MemoryRegion which 115 * needs to be plugged into the downstream end of the PPC port. 116 */ 117 typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, 118 const char *name, hwaddr size); 119 120 typedef struct PPCPortInfo { 121 const char *name; 122 MakeDevFn *devfn; 123 void *opaque; 124 hwaddr addr; 125 hwaddr size; 126 } PPCPortInfo; 127 128 typedef struct PPCInfo { 129 const char *name; 130 PPCPortInfo ports[TZ_NUM_PORTS]; 131 } PPCInfo; 132 133 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, 134 void *opaque, 135 const char *name, hwaddr size) 136 { 137 /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, 138 * and return a pointer to its MemoryRegion. 139 */ 140 UnimplementedDeviceState *uds = opaque; 141 142 sysbus_init_child_obj(OBJECT(mms), name, uds, 143 sizeof(UnimplementedDeviceState), 144 TYPE_UNIMPLEMENTED_DEVICE); 145 qdev_prop_set_string(DEVICE(uds), "name", name); 146 qdev_prop_set_uint64(DEVICE(uds), "size", size); 147 object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal); 148 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); 149 } 150 151 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, 152 const char *name, hwaddr size) 153 { 154 CMSDKAPBUART *uart = opaque; 155 int i = uart - &mms->uart[0]; 156 int rxirqno = i * 2; 157 int txirqno = i * 2 + 1; 158 int combirqno = i + 10; 159 SysBusDevice *s; 160 DeviceState *iotkitdev = DEVICE(&mms->iotkit); 161 DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); 162 163 sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]), 164 TYPE_CMSDK_APB_UART); 165 qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); 166 qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); 167 object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal); 168 s = SYS_BUS_DEVICE(uart); 169 sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, 170 "EXP_IRQ", txirqno)); 171 sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev, 172 "EXP_IRQ", rxirqno)); 173 sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); 174 sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); 175 sysbus_connect_irq(s, 4, qdev_get_gpio_in_named(iotkitdev, 176 "EXP_IRQ", combirqno)); 177 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); 178 } 179 180 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, 181 const char *name, hwaddr size) 182 { 183 MPS2SCC *scc = opaque; 184 DeviceState *sccdev; 185 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 186 187 object_initialize(scc, sizeof(mms->scc), TYPE_MPS2_SCC); 188 sccdev = DEVICE(scc); 189 qdev_set_parent_bus(sccdev, sysbus_get_default()); 190 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); 191 qdev_prop_set_uint32(sccdev, "scc-aid", 0x02000008); 192 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); 193 object_property_set_bool(OBJECT(scc), true, "realized", &error_fatal); 194 return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); 195 } 196 197 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, 198 const char *name, hwaddr size) 199 { 200 MPS2FPGAIO *fpgaio = opaque; 201 202 object_initialize(fpgaio, sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO); 203 qdev_set_parent_bus(DEVICE(fpgaio), sysbus_get_default()); 204 object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal); 205 return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); 206 } 207 208 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, 209 const char *name, hwaddr size) 210 { 211 SysBusDevice *s; 212 DeviceState *iotkitdev = DEVICE(&mms->iotkit); 213 NICInfo *nd = &nd_table[0]; 214 215 /* In hardware this is a LAN9220; the LAN9118 is software compatible 216 * except that it doesn't support the checksum-offload feature. 217 */ 218 qemu_check_nic_model(nd, "lan9118"); 219 mms->lan9118 = qdev_create(NULL, "lan9118"); 220 qdev_set_nic_properties(mms->lan9118, nd); 221 qdev_init_nofail(mms->lan9118); 222 223 s = SYS_BUS_DEVICE(mms->lan9118); 224 sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 16)); 225 return sysbus_mmio_get_region(s, 0); 226 } 227 228 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, 229 const char *name, hwaddr size) 230 { 231 TZMPC *mpc = opaque; 232 int i = mpc - &mms->ssram_mpc[0]; 233 MemoryRegion *ssram = &mms->ssram[i]; 234 MemoryRegion *upstream; 235 char *mpcname = g_strdup_printf("%s-mpc", name); 236 static uint32_t ramsize[] = { 0x00400000, 0x00200000, 0x00200000 }; 237 static uint32_t rambase[] = { 0x00000000, 0x28000000, 0x28200000 }; 238 239 memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal); 240 241 sysbus_init_child_obj(OBJECT(mms), mpcname, mpc, sizeof(mms->ssram_mpc[0]), 242 TYPE_TZ_MPC); 243 object_property_set_link(OBJECT(mpc), OBJECT(ssram), 244 "downstream", &error_fatal); 245 object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal); 246 /* Map the upstream end of the MPC into system memory */ 247 upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); 248 memory_region_add_subregion(get_system_memory(), rambase[i], upstream); 249 /* and connect its interrupt to the IoTKit */ 250 qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, 251 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 252 "mpcexp_status", i)); 253 254 /* The first SSRAM is a special case as it has an alias; accesses to 255 * the alias region at 0x00400000 must also go to the MPC upstream. 256 */ 257 if (i == 0) { 258 make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x00400000); 259 } 260 261 g_free(mpcname); 262 /* Return the register interface MR for our caller to map behind the PPC */ 263 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); 264 } 265 266 static void mps2tz_common_init(MachineState *machine) 267 { 268 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); 269 MachineClass *mc = MACHINE_GET_CLASS(machine); 270 MemoryRegion *system_memory = get_system_memory(); 271 DeviceState *iotkitdev; 272 DeviceState *dev_splitter; 273 int i; 274 275 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { 276 error_report("This board can only be used with CPU %s", 277 mc->default_cpu_type); 278 exit(1); 279 } 280 281 sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit, 282 sizeof(mms->iotkit), TYPE_IOTKIT); 283 iotkitdev = DEVICE(&mms->iotkit); 284 object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory), 285 "memory", &error_abort); 286 qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", 92); 287 qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); 288 object_property_set_bool(OBJECT(&mms->iotkit), true, "realized", 289 &error_fatal); 290 291 /* The sec_resp_cfg output from the IoTKit must be split into multiple 292 * lines, one for each of the PPCs we create here. 293 */ 294 object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter), 295 TYPE_SPLIT_IRQ); 296 object_property_add_child(OBJECT(machine), "sec-resp-splitter", 297 OBJECT(&mms->sec_resp_splitter), &error_abort); 298 object_property_set_int(OBJECT(&mms->sec_resp_splitter), 5, 299 "num-lines", &error_fatal); 300 object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true, 301 "realized", &error_fatal); 302 dev_splitter = DEVICE(&mms->sec_resp_splitter); 303 qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, 304 qdev_get_gpio_in(dev_splitter, 0)); 305 306 /* The IoTKit sets up much of the memory layout, including 307 * the aliases between secure and non-secure regions in the 308 * address space. The FPGA itself contains: 309 * 310 * 0x00000000..0x003fffff SSRAM1 311 * 0x00400000..0x007fffff alias of SSRAM1 312 * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3 313 * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices 314 * 0x80000000..0x80ffffff 16MB PSRAM 315 */ 316 317 /* The FPGA images have an odd combination of different RAMs, 318 * because in hardware they are different implementations and 319 * connected to different buses, giving varying performance/size 320 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily 321 * call the 16MB our "system memory", as it's the largest lump. 322 */ 323 memory_region_allocate_system_memory(&mms->psram, 324 NULL, "mps.ram", 0x01000000); 325 memory_region_add_subregion(system_memory, 0x80000000, &mms->psram); 326 327 /* The overflow IRQs for all UARTs are ORed together. 328 * Tx, Rx and "combined" IRQs are sent to the NVIC separately. 329 * Create the OR gate for this. 330 */ 331 object_initialize(&mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate), 332 TYPE_OR_IRQ); 333 object_property_add_child(OBJECT(mms), "uart-irq-orgate", 334 OBJECT(&mms->uart_irq_orgate), &error_abort); 335 object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines", 336 &error_fatal); 337 object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true, 338 "realized", &error_fatal); 339 qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, 340 qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 15)); 341 342 /* Most of the devices in the FPGA are behind Peripheral Protection 343 * Controllers. The required order for initializing things is: 344 * + initialize the PPC 345 * + initialize, configure and realize downstream devices 346 * + connect downstream device MemoryRegions to the PPC 347 * + realize the PPC 348 * + map the PPC's MemoryRegions to the places in the address map 349 * where the downstream devices should appear 350 * + wire up the PPC's control lines to the IoTKit object 351 */ 352 353 const PPCInfo ppcs[] = { { 354 .name = "apb_ppcexp0", 355 .ports = { 356 { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 }, 357 { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1000 }, 358 { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1000 }, 359 }, 360 }, { 361 .name = "apb_ppcexp1", 362 .ports = { 363 { "spi0", make_unimp_dev, &mms->spi[0], 0x40205000, 0x1000 }, 364 { "spi1", make_unimp_dev, &mms->spi[1], 0x40206000, 0x1000 }, 365 { "spi2", make_unimp_dev, &mms->spi[2], 0x40209000, 0x1000 }, 366 { "spi3", make_unimp_dev, &mms->spi[3], 0x4020a000, 0x1000 }, 367 { "spi4", make_unimp_dev, &mms->spi[4], 0x4020b000, 0x1000 }, 368 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 }, 369 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 }, 370 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 }, 371 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 }, 372 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 }, 373 { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40207000, 0x1000 }, 374 { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40208000, 0x1000 }, 375 { "i2c2", make_unimp_dev, &mms->i2c[2], 0x4020c000, 0x1000 }, 376 { "i2c3", make_unimp_dev, &mms->i2c[3], 0x4020d000, 0x1000 }, 377 }, 378 }, { 379 .name = "apb_ppcexp2", 380 .ports = { 381 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, 382 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 383 0x40301000, 0x1000 }, 384 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, 385 }, 386 }, { 387 .name = "ahb_ppcexp0", 388 .ports = { 389 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, 390 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, 391 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, 392 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, 393 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, 394 { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 }, 395 }, 396 }, { 397 .name = "ahb_ppcexp1", 398 .ports = { 399 { "dma0", make_unimp_dev, &mms->dma[0], 0x40110000, 0x1000 }, 400 { "dma1", make_unimp_dev, &mms->dma[1], 0x40111000, 0x1000 }, 401 { "dma2", make_unimp_dev, &mms->dma[2], 0x40112000, 0x1000 }, 402 { "dma3", make_unimp_dev, &mms->dma[3], 0x40113000, 0x1000 }, 403 }, 404 }, 405 }; 406 407 for (i = 0; i < ARRAY_SIZE(ppcs); i++) { 408 const PPCInfo *ppcinfo = &ppcs[i]; 409 TZPPC *ppc = &mms->ppc[i]; 410 DeviceState *ppcdev; 411 int port; 412 char *gpioname; 413 414 sysbus_init_child_obj(OBJECT(machine), ppcinfo->name, ppc, 415 sizeof(TZPPC), TYPE_TZ_PPC); 416 ppcdev = DEVICE(ppc); 417 418 for (port = 0; port < TZ_NUM_PORTS; port++) { 419 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 420 MemoryRegion *mr; 421 char *portname; 422 423 if (!pinfo->devfn) { 424 continue; 425 } 426 427 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); 428 portname = g_strdup_printf("port[%d]", port); 429 object_property_set_link(OBJECT(ppc), OBJECT(mr), 430 portname, &error_fatal); 431 g_free(portname); 432 } 433 434 object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal); 435 436 for (port = 0; port < TZ_NUM_PORTS; port++) { 437 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 438 439 if (!pinfo->devfn) { 440 continue; 441 } 442 sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); 443 444 gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); 445 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 446 qdev_get_gpio_in_named(ppcdev, 447 "cfg_nonsec", 448 port)); 449 g_free(gpioname); 450 gpioname = g_strdup_printf("%s_ap", ppcinfo->name); 451 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 452 qdev_get_gpio_in_named(ppcdev, 453 "cfg_ap", port)); 454 g_free(gpioname); 455 } 456 457 gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); 458 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 459 qdev_get_gpio_in_named(ppcdev, 460 "irq_enable", 0)); 461 g_free(gpioname); 462 gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); 463 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 464 qdev_get_gpio_in_named(ppcdev, 465 "irq_clear", 0)); 466 g_free(gpioname); 467 gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); 468 qdev_connect_gpio_out_named(ppcdev, "irq", 0, 469 qdev_get_gpio_in_named(iotkitdev, 470 gpioname, 0)); 471 g_free(gpioname); 472 473 qdev_connect_gpio_out(dev_splitter, i, 474 qdev_get_gpio_in_named(ppcdev, 475 "cfg_sec_resp", 0)); 476 } 477 478 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); 479 480 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); 481 } 482 483 static void mps2tz_class_init(ObjectClass *oc, void *data) 484 { 485 MachineClass *mc = MACHINE_CLASS(oc); 486 487 mc->init = mps2tz_common_init; 488 mc->max_cpus = 1; 489 } 490 491 static void mps2tz_an505_class_init(ObjectClass *oc, void *data) 492 { 493 MachineClass *mc = MACHINE_CLASS(oc); 494 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 495 496 mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; 497 mmc->fpga_type = FPGA_AN505; 498 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 499 mmc->scc_id = 0x41040000 | (505 << 4); 500 } 501 502 static const TypeInfo mps2tz_info = { 503 .name = TYPE_MPS2TZ_MACHINE, 504 .parent = TYPE_MACHINE, 505 .abstract = true, 506 .instance_size = sizeof(MPS2TZMachineState), 507 .class_size = sizeof(MPS2TZMachineClass), 508 .class_init = mps2tz_class_init, 509 }; 510 511 static const TypeInfo mps2tz_an505_info = { 512 .name = TYPE_MPS2TZ_AN505_MACHINE, 513 .parent = TYPE_MPS2TZ_MACHINE, 514 .class_init = mps2tz_an505_class_init, 515 }; 516 517 static void mps2tz_machine_init(void) 518 { 519 type_register_static(&mps2tz_info); 520 type_register_static(&mps2tz_an505_info); 521 } 522 523 type_init(mps2tz_machine_init); 524