1 /*
2 * ARM V2M MPS2 board emulation, trustzone aware FPGA images
3 *
4 * Copyright (c) 2017 Linaro Limited
5 * Written by Peter Maydell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
10 */
11
12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
13 * FPGA but is otherwise the same as the 2). Since the CPU itself
14 * and most of the devices are in the FPGA, the details of the board
15 * as seen by the guest depend significantly on the FPGA image.
16 * This source file covers the following FPGA images, for TrustZone cores:
17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505
18 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521
19 * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524
20 * "mps2-an547" -- Single Cortex-M55 as documented in Application Note AN547
21 *
22 * Links to the TRM for the board itself and to the various Application
23 * Notes which document the FPGA images can be found here:
24 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2
25 *
26 * Board TRM:
27 * https://developer.arm.com/documentation/100112/latest/
28 * Application Note AN505:
29 * https://developer.arm.com/documentation/dai0505/latest/
30 * Application Note AN521:
31 * https://developer.arm.com/documentation/dai0521/latest/
32 * Application Note AN524:
33 * https://developer.arm.com/documentation/dai0524/latest/
34 * Application Note AN547:
35 * https://developer.arm.com/documentation/dai0547/latest/
36 *
37 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
38 * (ARM ECM0601256) for the details of some of the device layout:
39 * https://developer.arm.com/documentation/ecm0601256/latest
40 * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines
41 * most of the device layout:
42 * https://developer.arm.com/documentation/101104/latest/
43 * and the AN547 uses the SSE-300, whose layout is in the SSE-300 TRM:
44 * https://developer.arm.com/documentation/101773/latest/
45 */
46
47 #include "qemu/osdep.h"
48 #include "qemu/units.h"
49 #include "qemu/cutils.h"
50 #include "qapi/error.h"
51 #include "qapi/qmp/qlist.h"
52 #include "qemu/error-report.h"
53 #include "hw/arm/boot.h"
54 #include "hw/arm/armv7m.h"
55 #include "hw/or-irq.h"
56 #include "hw/boards.h"
57 #include "exec/address-spaces.h"
58 #include "sysemu/sysemu.h"
59 #include "sysemu/reset.h"
60 #include "hw/misc/unimp.h"
61 #include "hw/char/cmsdk-apb-uart.h"
62 #include "hw/timer/cmsdk-apb-timer.h"
63 #include "hw/misc/mps2-scc.h"
64 #include "hw/misc/mps2-fpgaio.h"
65 #include "hw/misc/tz-mpc.h"
66 #include "hw/misc/tz-msc.h"
67 #include "hw/arm/armsse.h"
68 #include "hw/dma/pl080.h"
69 #include "hw/rtc/pl031.h"
70 #include "hw/ssi/pl022.h"
71 #include "hw/i2c/arm_sbcon_i2c.h"
72 #include "hw/net/lan9118.h"
73 #include "net/net.h"
74 #include "hw/core/split-irq.h"
75 #include "hw/qdev-clock.h"
76 #include "qom/object.h"
77 #include "hw/irq.h"
78
79 #define MPS2TZ_NUMIRQ_MAX 96
80 #define MPS2TZ_RAM_MAX 5
81
82 typedef enum MPS2TZFPGAType {
83 FPGA_AN505,
84 FPGA_AN521,
85 FPGA_AN524,
86 FPGA_AN547,
87 } MPS2TZFPGAType;
88
89 /*
90 * Define the layout of RAM in a board, including which parts are
91 * behind which MPCs.
92 * mrindex specifies the index into mms->ram[] to use for the backing RAM;
93 * -1 means "use the system RAM".
94 */
95 typedef struct RAMInfo {
96 const char *name;
97 uint32_t base;
98 uint32_t size;
99 int mpc; /* MPC number, -1 for "not behind an MPC" */
100 int mrindex;
101 int flags;
102 } RAMInfo;
103
104 /*
105 * Flag values:
106 * IS_ALIAS: this RAM area is an alias to the upstream end of the
107 * MPC specified by its .mpc value
108 * IS_ROM: this RAM area is read-only
109 */
110 #define IS_ALIAS 1
111 #define IS_ROM 2
112
113 struct MPS2TZMachineClass {
114 MachineClass parent;
115 MPS2TZFPGAType fpga_type;
116 uint32_t scc_id;
117 uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */
118 uint32_t apb_periph_frq; /* APB peripheral frequency in Hz */
119 uint32_t len_oscclk;
120 const uint32_t *oscclk;
121 uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */
122 bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */
123 bool fpgaio_has_dbgctrl; /* Does FPGAIO have DBGCTRL register? */
124 int numirq; /* Number of external interrupts */
125 int uart_overflow_irq; /* number of the combined UART overflow IRQ */
126 uint32_t init_svtor; /* init-svtor setting for SSE */
127 uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */
128 uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */
129 uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */
130 uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */
131 uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */
132 const RAMInfo *raminfo;
133 const char *armsse_type;
134 uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */
135 };
136
137 struct MPS2TZMachineState {
138 MachineState parent;
139
140 ARMSSE iotkit;
141 MemoryRegion ram[MPS2TZ_RAM_MAX];
142 MemoryRegion eth_usb_container;
143
144 MPS2SCC scc;
145 MPS2FPGAIO fpgaio;
146 TZPPC ppc[5];
147 TZMPC mpc[3];
148 PL022State spi[5];
149 ArmSbconI2CState i2c[5];
150 UnimplementedDeviceState i2s_audio;
151 UnimplementedDeviceState gpio[4];
152 UnimplementedDeviceState gfx;
153 UnimplementedDeviceState cldc;
154 UnimplementedDeviceState usb;
155 PL031State rtc;
156 PL080State dma[4];
157 TZMSC msc[4];
158 CMSDKAPBUART uart[6];
159 SplitIRQ sec_resp_splitter;
160 OrIRQState uart_irq_orgate;
161 DeviceState *lan9118;
162 SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX];
163 Clock *sysclk;
164 Clock *s32kclk;
165
166 bool remap;
167 qemu_irq remap_irq;
168 };
169
170 #define TYPE_MPS2TZ_MACHINE "mps2tz"
171 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505")
172 #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521")
173 #define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524")
174 #define TYPE_MPS3TZ_AN547_MACHINE MACHINE_TYPE_NAME("mps3-an547")
175
176 OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
177
178 /* Slow 32Khz S32KCLK frequency in Hz */
179 #define S32KCLK_FRQ (32 * 1000)
180
181 /*
182 * The MPS3 DDR is 2GiB, but on a 32-bit host QEMU doesn't permit
183 * emulation of that much guest RAM, so artificially make it smaller.
184 */
185 #if HOST_LONG_BITS == 32
186 #define MPS3_DDR_SIZE (1 * GiB)
187 #else
188 #define MPS3_DDR_SIZE (2 * GiB)
189 #endif
190
191 /* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */
192 #define MPU_REGION_DEFAULT UINT32_MAX
193
194 static const uint32_t an505_oscclk[] = {
195 40000000,
196 24580000,
197 25000000,
198 };
199
200 static const uint32_t an524_oscclk[] = {
201 24000000,
202 32000000,
203 50000000,
204 50000000,
205 24576000,
206 23750000,
207 };
208
209 static const RAMInfo an505_raminfo[] = { {
210 .name = "ssram-0",
211 .base = 0x00000000,
212 .size = 0x00400000,
213 .mpc = 0,
214 .mrindex = 0,
215 }, {
216 .name = "ssram-1",
217 .base = 0x28000000,
218 .size = 0x00200000,
219 .mpc = 1,
220 .mrindex = 1,
221 }, {
222 .name = "ssram-2",
223 .base = 0x28200000,
224 .size = 0x00200000,
225 .mpc = 2,
226 .mrindex = 2,
227 }, {
228 .name = "ssram-0-alias",
229 .base = 0x00400000,
230 .size = 0x00400000,
231 .mpc = 0,
232 .mrindex = 3,
233 .flags = IS_ALIAS,
234 }, {
235 /* Use the largest bit of contiguous RAM as our "system memory" */
236 .name = "mps.ram",
237 .base = 0x80000000,
238 .size = 16 * MiB,
239 .mpc = -1,
240 .mrindex = -1,
241 }, {
242 .name = NULL,
243 },
244 };
245
246 /*
247 * Note that the addresses and MPC numbering here should match up
248 * with those used in remap_memory(), which can swap the BRAM and QSPI.
249 */
250 static const RAMInfo an524_raminfo[] = { {
251 .name = "bram",
252 .base = 0x00000000,
253 .size = 512 * KiB,
254 .mpc = 0,
255 .mrindex = 0,
256 }, {
257 /* We don't model QSPI flash yet; for now expose it as simple ROM */
258 .name = "QSPI",
259 .base = 0x28000000,
260 .size = 8 * MiB,
261 .mpc = 1,
262 .mrindex = 1,
263 .flags = IS_ROM,
264 }, {
265 .name = "DDR",
266 .base = 0x60000000,
267 .size = MPS3_DDR_SIZE,
268 .mpc = 2,
269 .mrindex = -1,
270 }, {
271 .name = NULL,
272 },
273 };
274
275 static const RAMInfo an547_raminfo[] = { {
276 .name = "sram",
277 .base = 0x01000000,
278 .size = 2 * MiB,
279 .mpc = 0,
280 .mrindex = 1,
281 }, {
282 .name = "sram 2",
283 .base = 0x21000000,
284 .size = 4 * MiB,
285 .mpc = -1,
286 .mrindex = 3,
287 }, {
288 /* We don't model QSPI flash yet; for now expose it as simple ROM */
289 .name = "QSPI",
290 .base = 0x28000000,
291 .size = 8 * MiB,
292 .mpc = 1,
293 .mrindex = 4,
294 .flags = IS_ROM,
295 }, {
296 .name = "DDR",
297 .base = 0x60000000,
298 .size = MPS3_DDR_SIZE,
299 .mpc = 2,
300 .mrindex = -1,
301 }, {
302 .name = NULL,
303 },
304 };
305
find_raminfo_for_mpc(MPS2TZMachineState * mms,int mpc)306 static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc)
307 {
308 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
309 const RAMInfo *p;
310 const RAMInfo *found = NULL;
311
312 for (p = mmc->raminfo; p->name; p++) {
313 if (p->mpc == mpc && !(p->flags & IS_ALIAS)) {
314 /* There should only be one entry in the array for this MPC */
315 g_assert(!found);
316 found = p;
317 }
318 }
319 /* if raminfo array doesn't have an entry for each MPC this is a bug */
320 assert(found);
321 return found;
322 }
323
mr_for_raminfo(MPS2TZMachineState * mms,const RAMInfo * raminfo)324 static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms,
325 const RAMInfo *raminfo)
326 {
327 /* Return an initialized MemoryRegion for the RAMInfo. */
328 MemoryRegion *ram;
329
330 if (raminfo->mrindex < 0) {
331 /* Means this RAMInfo is for QEMU's "system memory" */
332 MachineState *machine = MACHINE(mms);
333 assert(!(raminfo->flags & IS_ROM));
334 return machine->ram;
335 }
336
337 assert(raminfo->mrindex < MPS2TZ_RAM_MAX);
338 ram = &mms->ram[raminfo->mrindex];
339
340 memory_region_init_ram(ram, NULL, raminfo->name,
341 raminfo->size, &error_fatal);
342 if (raminfo->flags & IS_ROM) {
343 memory_region_set_readonly(ram, true);
344 }
345 return ram;
346 }
347
348 /* Create an alias of an entire original MemoryRegion @orig
349 * located at @base in the memory map.
350 */
make_ram_alias(MemoryRegion * mr,const char * name,MemoryRegion * orig,hwaddr base)351 static void make_ram_alias(MemoryRegion *mr, const char *name,
352 MemoryRegion *orig, hwaddr base)
353 {
354 memory_region_init_alias(mr, NULL, name, orig, 0,
355 memory_region_size(orig));
356 memory_region_add_subregion(get_system_memory(), base, mr);
357 }
358
get_sse_irq_in(MPS2TZMachineState * mms,int irqno)359 static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno)
360 {
361 /*
362 * Return a qemu_irq which will signal IRQ n to all CPUs in the
363 * SSE. The irqno should be as the CPU sees it, so the first
364 * external-to-the-SSE interrupt is 32.
365 */
366 MachineClass *mc = MACHINE_GET_CLASS(mms);
367 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
368
369 assert(irqno >= 32 && irqno < (mmc->numirq + 32));
370
371 /*
372 * Convert from "CPU irq number" (as listed in the FPGA image
373 * documentation) to the SSE external-interrupt number.
374 */
375 irqno -= 32;
376
377 if (mc->max_cpus > 1) {
378 return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0);
379 } else {
380 return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno);
381 }
382 }
383
384 /* Union describing the device-specific extra data we pass to the devfn. */
385 typedef union PPCExtraData {
386 bool i2c_internal;
387 } PPCExtraData;
388
389 /* Most of the devices in the AN505 FPGA image sit behind
390 * Peripheral Protection Controllers. These data structures
391 * define the layout of which devices sit behind which PPCs.
392 * The devfn for each port is a function which creates, configures
393 * and initializes the device, returning the MemoryRegion which
394 * needs to be plugged into the downstream end of the PPC port.
395 */
396 typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque,
397 const char *name, hwaddr size,
398 const int *irqs,
399 const PPCExtraData *extradata);
400
401 typedef struct PPCPortInfo {
402 const char *name;
403 MakeDevFn *devfn;
404 void *opaque;
405 hwaddr addr;
406 hwaddr size;
407 int irqs[3]; /* currently no device needs more IRQ lines than this */
408 PPCExtraData extradata; /* to pass device-specific info to the devfn */
409 } PPCPortInfo;
410
411 typedef struct PPCInfo {
412 const char *name;
413 PPCPortInfo ports[TZ_NUM_PORTS];
414 } PPCInfo;
415
make_unimp_dev(MPS2TZMachineState * mms,void * opaque,const char * name,hwaddr size,const int * irqs,const PPCExtraData * extradata)416 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms,
417 void *opaque,
418 const char *name, hwaddr size,
419 const int *irqs,
420 const PPCExtraData *extradata)
421 {
422 /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE,
423 * and return a pointer to its MemoryRegion.
424 */
425 UnimplementedDeviceState *uds = opaque;
426
427 object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE);
428 qdev_prop_set_string(DEVICE(uds), "name", name);
429 qdev_prop_set_uint64(DEVICE(uds), "size", size);
430 sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal);
431 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);
432 }
433
make_uart(MPS2TZMachineState * mms,void * opaque,const char * name,hwaddr size,const int * irqs,const PPCExtraData * extradata)434 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
435 const char *name, hwaddr size,
436 const int *irqs, const PPCExtraData *extradata)
437 {
438 /* The irq[] array is rx, tx, combined, in that order */
439 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
440 CMSDKAPBUART *uart = opaque;
441 int i = uart - &mms->uart[0];
442 SysBusDevice *s;
443 DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate);
444
445 object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART);
446 qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));
447 qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->apb_periph_frq);
448 sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal);
449 s = SYS_BUS_DEVICE(uart);
450 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[1]));
451 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[0]));
452 sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2));
453 sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1));
454 sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2]));
455 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0);
456 }
457
make_scc(MPS2TZMachineState * mms,void * opaque,const char * name,hwaddr size,const int * irqs,const PPCExtraData * extradata)458 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque,
459 const char *name, hwaddr size,
460 const int *irqs, const PPCExtraData *extradata)
461 {
462 MPS2SCC *scc = opaque;
463 DeviceState *sccdev;
464 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
465 QList *oscclk;
466 uint32_t i;
467
468 object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC);
469 sccdev = DEVICE(scc);
470 qdev_prop_set_uint32(sccdev, "scc-cfg0", mms->remap ? 1 : 0);
471 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
472 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
473 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
474
475 oscclk = qlist_new();
476 for (i = 0; i < mmc->len_oscclk; i++) {
477 qlist_append_int(oscclk, mmc->oscclk[i]);
478 }
479 qdev_prop_set_array(sccdev, "oscclk", oscclk);
480
481 sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal);
482 return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0);
483 }
484
make_fpgaio(MPS2TZMachineState * mms,void * opaque,const char * name,hwaddr size,const int * irqs,const PPCExtraData * extradata)485 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque,
486 const char *name, hwaddr size,
487 const int *irqs, const PPCExtraData *extradata)
488 {
489 MPS2FPGAIO *fpgaio = opaque;
490 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
491
492 object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO);
493 qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds);
494 qdev_prop_set_bit(DEVICE(fpgaio), "has-switches", mmc->fpgaio_has_switches);
495 qdev_prop_set_bit(DEVICE(fpgaio), "has-dbgctrl", mmc->fpgaio_has_dbgctrl);
496 sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal);
497 return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0);
498 }
499
make_eth_dev(MPS2TZMachineState * mms,void * opaque,const char * name,hwaddr size,const int * irqs,const PPCExtraData * extradata)500 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque,
501 const char *name, hwaddr size,
502 const int *irqs,
503 const PPCExtraData *extradata)
504 {
505 SysBusDevice *s;
506
507 /* In hardware this is a LAN9220; the LAN9118 is software compatible
508 * except that it doesn't support the checksum-offload feature.
509 */
510 mms->lan9118 = qdev_new(TYPE_LAN9118);
511 qemu_configure_nic_device(mms->lan9118, true, NULL);
512
513 s = SYS_BUS_DEVICE(mms->lan9118);
514 sysbus_realize_and_unref(s, &error_fatal);
515 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0]));
516 return sysbus_mmio_get_region(s, 0);
517 }
518
make_eth_usb(MPS2TZMachineState * mms,void * opaque,const char * name,hwaddr size,const int * irqs,const PPCExtraData * extradata)519 static MemoryRegion *make_eth_usb(MPS2TZMachineState *mms, void *opaque,
520 const char *name, hwaddr size,
521 const int *irqs,
522 const PPCExtraData *extradata)
523 {
524 /*
525 * The AN524 makes the ethernet and USB share a PPC port.
526 * irqs[] is the ethernet IRQ.
527 */
528 SysBusDevice *s;
529
530 memory_region_init(&mms->eth_usb_container, OBJECT(mms),
531 "mps2-tz-eth-usb-container", 0x200000);
532
533 /*
534 * In hardware this is a LAN9220; the LAN9118 is software compatible
535 * except that it doesn't support the checksum-offload feature.
536 */
537 mms->lan9118 = qdev_new(TYPE_LAN9118);
538 qemu_configure_nic_device(mms->lan9118, true, NULL);
539
540 s = SYS_BUS_DEVICE(mms->lan9118);
541 sysbus_realize_and_unref(s, &error_fatal);
542 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0]));
543
544 memory_region_add_subregion(&mms->eth_usb_container,
545 0, sysbus_mmio_get_region(s, 0));
546
547 /* The USB OTG controller is an ISP1763; we don't have a model of it. */
548 object_initialize_child(OBJECT(mms), "usb-otg",
549 &mms->usb, TYPE_UNIMPLEMENTED_DEVICE);
550 qdev_prop_set_string(DEVICE(&mms->usb), "name", "usb-otg");
551 qdev_prop_set_uint64(DEVICE(&mms->usb), "size", 0x100000);
552 s = SYS_BUS_DEVICE(&mms->usb);
553 sysbus_realize(s, &error_fatal);
554
555 memory_region_add_subregion(&mms->eth_usb_container,
556 0x100000, sysbus_mmio_get_region(s, 0));
557
558 return &mms->eth_usb_container;
559 }
560
make_mpc(MPS2TZMachineState * mms,void * opaque,const char * name,hwaddr size,const int * irqs,const PPCExtraData * extradata)561 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque,
562 const char *name, hwaddr size,
563 const int *irqs, const PPCExtraData *extradata)
564 {
565 TZMPC *mpc = opaque;
566 int i = mpc - &mms->mpc[0];
567 MemoryRegion *upstream;
568 const RAMInfo *raminfo = find_raminfo_for_mpc(mms, i);
569 MemoryRegion *ram = mr_for_raminfo(mms, raminfo);
570
571 object_initialize_child(OBJECT(mms), name, mpc, TYPE_TZ_MPC);
572 object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ram),
573 &error_fatal);
574 sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal);
575 /* Map the upstream end of the MPC into system memory */
576 upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1);
577 memory_region_add_subregion(get_system_memory(), raminfo->base, upstream);
578 /* and connect its interrupt to the IoTKit */
579 qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0,
580 qdev_get_gpio_in_named(DEVICE(&mms->iotkit),
581 "mpcexp_status", i));
582
583 /* Return the register interface MR for our caller to map behind the PPC */
584 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0);
585 }
586
boot_mem_base(MPS2TZMachineState * mms)587 static hwaddr boot_mem_base(MPS2TZMachineState *mms)
588 {
589 /*
590 * Return the canonical address of the block which will be mapped
591 * at address 0x0 (i.e. where the vector table is).
592 * This is usually 0, but if the AN524 alternate memory map is
593 * enabled it will be the base address of the QSPI block.
594 */
595 return mms->remap ? 0x28000000 : 0;
596 }
597
remap_memory(MPS2TZMachineState * mms,int map)598 static void remap_memory(MPS2TZMachineState *mms, int map)
599 {
600 /*
601 * Remap the memory for the AN524. 'map' is the value of
602 * SCC CFG_REG0 bit 0, i.e. 0 for the default map and 1
603 * for the "option 1" mapping where QSPI is at address 0.
604 *
605 * Effectively we need to swap around the "upstream" ends of
606 * MPC 0 and MPC 1.
607 */
608 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
609 int i;
610
611 if (mmc->fpga_type != FPGA_AN524) {
612 return;
613 }
614
615 memory_region_transaction_begin();
616 for (i = 0; i < 2; i++) {
617 TZMPC *mpc = &mms->mpc[i];
618 MemoryRegion *upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1);
619 hwaddr addr = (i ^ map) ? 0x28000000 : 0;
620
621 memory_region_set_address(upstream, addr);
622 }
623 memory_region_transaction_commit();
624 }
625
remap_irq_fn(void * opaque,int n,int level)626 static void remap_irq_fn(void *opaque, int n, int level)
627 {
628 MPS2TZMachineState *mms = opaque;
629
630 remap_memory(mms, level);
631 }
632
make_dma(MPS2TZMachineState * mms,void * opaque,const char * name,hwaddr size,const int * irqs,const PPCExtraData * extradata)633 static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque,
634 const char *name, hwaddr size,
635 const int *irqs, const PPCExtraData *extradata)
636 {
637 /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */
638 PL080State *dma = opaque;
639 int i = dma - &mms->dma[0];
640 SysBusDevice *s;
641 char *mscname = g_strdup_printf("%s-msc", name);
642 TZMSC *msc = &mms->msc[i];
643 DeviceState *iotkitdev = DEVICE(&mms->iotkit);
644 MemoryRegion *msc_upstream;
645 MemoryRegion *msc_downstream;
646
647 /*
648 * Each DMA device is a PL081 whose transaction master interface
649 * is guarded by a Master Security Controller. The downstream end of
650 * the MSC connects to the IoTKit AHB Slave Expansion port, so the
651 * DMA devices can see all devices and memory that the CPU does.
652 */
653 object_initialize_child(OBJECT(mms), mscname, msc, TYPE_TZ_MSC);
654 msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0);
655 object_property_set_link(OBJECT(msc), "downstream",
656 OBJECT(msc_downstream), &error_fatal);
657 object_property_set_link(OBJECT(msc), "idau", OBJECT(mms), &error_fatal);
658 sysbus_realize(SYS_BUS_DEVICE(msc), &error_fatal);
659
660 qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0,
661 qdev_get_gpio_in_named(iotkitdev,
662 "mscexp_status", i));
663 qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i,
664 qdev_get_gpio_in_named(DEVICE(msc),
665 "irq_clear", 0));
666 qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i,
667 qdev_get_gpio_in_named(DEVICE(msc),
668 "cfg_nonsec", 0));
669 qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter),
670 ARRAY_SIZE(mms->ppc) + i,
671 qdev_get_gpio_in_named(DEVICE(msc),
672 "cfg_sec_resp", 0));
673 msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0);
674
675 object_initialize_child(OBJECT(mms), name, dma, TYPE_PL081);
676 object_property_set_link(OBJECT(dma), "downstream", OBJECT(msc_upstream),
677 &error_fatal);
678 sysbus_realize(SYS_BUS_DEVICE(dma), &error_fatal);
679
680 s = SYS_BUS_DEVICE(dma);
681 /* Wire up DMACINTR, DMACINTERR, DMACINTTC */
682 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0]));
683 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1]));
684 sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqs[2]));
685
686 g_free(mscname);
687 return sysbus_mmio_get_region(s, 0);
688 }
689
make_spi(MPS2TZMachineState * mms,void * opaque,const char * name,hwaddr size,const int * irqs,const PPCExtraData * extradata)690 static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque,
691 const char *name, hwaddr size,
692 const int *irqs, const PPCExtraData *extradata)
693 {
694 /*
695 * The AN505 has five PL022 SPI controllers.
696 * One of these should have the LCD controller behind it; the others
697 * are connected only to the FPGA's "general purpose SPI connector"
698 * or "shield" expansion connectors.
699 * Note that if we do implement devices behind SPI, the chip select
700 * lines are set via the "MISC" register in the MPS2 FPGAIO device.
701 */
702 PL022State *spi = opaque;
703 SysBusDevice *s;
704
705 object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022);
706 sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal);
707 s = SYS_BUS_DEVICE(spi);
708 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0]));
709 return sysbus_mmio_get_region(s, 0);
710 }
711
make_i2c(MPS2TZMachineState * mms,void * opaque,const char * name,hwaddr size,const int * irqs,const PPCExtraData * extradata)712 static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque,
713 const char *name, hwaddr size,
714 const int *irqs, const PPCExtraData *extradata)
715 {
716 ArmSbconI2CState *i2c = opaque;
717 SysBusDevice *s;
718
719 object_initialize_child(OBJECT(mms), name, i2c, TYPE_ARM_SBCON_I2C);
720 s = SYS_BUS_DEVICE(i2c);
721 sysbus_realize(s, &error_fatal);
722
723 /*
724 * If this is an internal-use-only i2c bus, mark it full
725 * so that user-created i2c devices are not plugged into it.
726 * If we implement models of any on-board i2c devices that
727 * plug in to one of the internal-use-only buses, then we will
728 * need to create and plugging those in here before we mark the
729 * bus as full.
730 */
731 if (extradata->i2c_internal) {
732 BusState *qbus = qdev_get_child_bus(DEVICE(i2c), "i2c");
733 qbus_mark_full(qbus);
734 }
735
736 return sysbus_mmio_get_region(s, 0);
737 }
738
make_rtc(MPS2TZMachineState * mms,void * opaque,const char * name,hwaddr size,const int * irqs,const PPCExtraData * extradata)739 static MemoryRegion *make_rtc(MPS2TZMachineState *mms, void *opaque,
740 const char *name, hwaddr size,
741 const int *irqs, const PPCExtraData *extradata)
742 {
743 PL031State *pl031 = opaque;
744 SysBusDevice *s;
745
746 object_initialize_child(OBJECT(mms), name, pl031, TYPE_PL031);
747 s = SYS_BUS_DEVICE(pl031);
748 sysbus_realize(s, &error_fatal);
749 /*
750 * The board docs don't give an IRQ number for the PL031, so
751 * presumably it is not connected.
752 */
753 return sysbus_mmio_get_region(s, 0);
754 }
755
create_non_mpc_ram(MPS2TZMachineState * mms)756 static void create_non_mpc_ram(MPS2TZMachineState *mms)
757 {
758 /*
759 * Handle the RAMs which are either not behind MPCs or which are
760 * aliases to another MPC.
761 */
762 const RAMInfo *p;
763 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
764
765 for (p = mmc->raminfo; p->name; p++) {
766 if (p->flags & IS_ALIAS) {
767 SysBusDevice *mpc_sbd = SYS_BUS_DEVICE(&mms->mpc[p->mpc]);
768 MemoryRegion *upstream = sysbus_mmio_get_region(mpc_sbd, 1);
769 make_ram_alias(&mms->ram[p->mrindex], p->name, upstream, p->base);
770 } else if (p->mpc == -1) {
771 /* RAM not behind an MPC */
772 MemoryRegion *mr = mr_for_raminfo(mms, p);
773 memory_region_add_subregion(get_system_memory(), p->base, mr);
774 }
775 }
776 }
777
boot_ram_size(MPS2TZMachineState * mms)778 static uint32_t boot_ram_size(MPS2TZMachineState *mms)
779 {
780 /* Return the size of the RAM block at guest address zero */
781 const RAMInfo *p;
782 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
783
784 /*
785 * Use a per-board specification (for when the boot RAM is in
786 * the SSE and so doesn't have a RAMInfo list entry)
787 */
788 if (mmc->boot_ram_size) {
789 return mmc->boot_ram_size;
790 }
791
792 for (p = mmc->raminfo; p->name; p++) {
793 if (p->base == boot_mem_base(mms)) {
794 return p->size;
795 }
796 }
797 g_assert_not_reached();
798 }
799
mps2tz_common_init(MachineState * machine)800 static void mps2tz_common_init(MachineState *machine)
801 {
802 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine);
803 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
804 MachineClass *mc = MACHINE_GET_CLASS(machine);
805 MemoryRegion *system_memory = get_system_memory();
806 DeviceState *iotkitdev;
807 DeviceState *dev_splitter;
808 const PPCInfo *ppcs;
809 int num_ppcs;
810 int i;
811
812 if (machine->ram_size != mc->default_ram_size) {
813 char *sz = size_to_str(mc->default_ram_size);
814 error_report("Invalid RAM size, should be %s", sz);
815 g_free(sz);
816 exit(EXIT_FAILURE);
817 }
818
819 /* These clocks don't need migration because they are fixed-frequency */
820 mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
821 clock_set_hz(mms->sysclk, mmc->sysclk_frq);
822 mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK");
823 clock_set_hz(mms->s32kclk, S32KCLK_FRQ);
824
825 object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit,
826 mmc->armsse_type);
827 iotkitdev = DEVICE(&mms->iotkit);
828 object_property_set_link(OBJECT(&mms->iotkit), "memory",
829 OBJECT(system_memory), &error_abort);
830 qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq);
831 qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor);
832 if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) {
833 qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns);
834 }
835 if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) {
836 qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s);
837 }
838 if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) {
839 if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) {
840 qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns);
841 }
842 if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) {
843 qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s);
844 }
845 }
846 qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
847 qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
848 qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
849 sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
850
851 /*
852 * If this board has more than one CPU, then we need to create splitters
853 * to feed the IRQ inputs for each CPU in the SSE from each device in the
854 * board. If there is only one CPU, we can just wire the device IRQ
855 * directly to the SSE's IRQ input.
856 */
857 assert(mmc->numirq <= MPS2TZ_NUMIRQ_MAX);
858 if (mc->max_cpus > 1) {
859 for (i = 0; i < mmc->numirq; i++) {
860 char *name = g_strdup_printf("mps2-irq-splitter%d", i);
861 SplitIRQ *splitter = &mms->cpu_irq_splitter[i];
862
863 object_initialize_child_with_props(OBJECT(machine), name,
864 splitter, sizeof(*splitter),
865 TYPE_SPLIT_IRQ, &error_fatal,
866 NULL);
867 g_free(name);
868
869 object_property_set_int(OBJECT(splitter), "num-lines", 2,
870 &error_fatal);
871 qdev_realize(DEVICE(splitter), NULL, &error_fatal);
872 qdev_connect_gpio_out(DEVICE(splitter), 0,
873 qdev_get_gpio_in_named(DEVICE(&mms->iotkit),
874 "EXP_IRQ", i));
875 qdev_connect_gpio_out(DEVICE(splitter), 1,
876 qdev_get_gpio_in_named(DEVICE(&mms->iotkit),
877 "EXP_CPU1_IRQ", i));
878 }
879 }
880
881 /* The sec_resp_cfg output from the IoTKit must be split into multiple
882 * lines, one for each of the PPCs we create here, plus one per MSC.
883 */
884 object_initialize_child(OBJECT(machine), "sec-resp-splitter",
885 &mms->sec_resp_splitter, TYPE_SPLIT_IRQ);
886 object_property_set_int(OBJECT(&mms->sec_resp_splitter), "num-lines",
887 ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc),
888 &error_fatal);
889 qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal);
890 dev_splitter = DEVICE(&mms->sec_resp_splitter);
891 qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0,
892 qdev_get_gpio_in(dev_splitter, 0));
893
894 /*
895 * The IoTKit sets up much of the memory layout, including
896 * the aliases between secure and non-secure regions in the
897 * address space, and also most of the devices in the system.
898 * The FPGA itself contains various RAMs and some additional devices.
899 * The FPGA images have an odd combination of different RAMs,
900 * because in hardware they are different implementations and
901 * connected to different buses, giving varying performance/size
902 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
903 * call the largest lump our "system memory".
904 */
905
906 /*
907 * The overflow IRQs for all UARTs are ORed together.
908 * Tx, Rx and "combined" IRQs are sent to the NVIC separately.
909 * Create the OR gate for this: it has one input for the TX overflow
910 * and one for the RX overflow for each UART we might have.
911 * (If the board has fewer than the maximum possible number of UARTs
912 * those inputs are never wired up and are treated as always-zero.)
913 */
914 object_initialize_child(OBJECT(mms), "uart-irq-orgate",
915 &mms->uart_irq_orgate, TYPE_OR_IRQ);
916 object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines",
917 2 * ARRAY_SIZE(mms->uart),
918 &error_fatal);
919 qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal);
920 qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0,
921 get_sse_irq_in(mms, mmc->uart_overflow_irq));
922
923 /* Most of the devices in the FPGA are behind Peripheral Protection
924 * Controllers. The required order for initializing things is:
925 * + initialize the PPC
926 * + initialize, configure and realize downstream devices
927 * + connect downstream device MemoryRegions to the PPC
928 * + realize the PPC
929 * + map the PPC's MemoryRegions to the places in the address map
930 * where the downstream devices should appear
931 * + wire up the PPC's control lines to the IoTKit object
932 */
933
934 const PPCInfo an505_ppcs[] = { {
935 .name = "apb_ppcexp0",
936 .ports = {
937 { "ssram-0-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 },
938 { "ssram-1-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 },
939 { "ssram-2-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 },
940 },
941 }, {
942 .name = "apb_ppcexp1",
943 .ports = {
944 { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000, { 51 } },
945 { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000, { 52 } },
946 { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000, { 53 } },
947 { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000, { 54 } },
948 { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000, { 55 } },
949 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000, { 32, 33, 42 } },
950 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000, { 34, 35, 43 } },
951 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000, { 36, 37, 44 } },
952 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000, { 38, 39, 45 } },
953 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000, { 40, 41, 46 } },
954 { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000, {},
955 { .i2c_internal = true /* touchscreen */ } },
956 { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000, {},
957 { .i2c_internal = true /* audio conf */ } },
958 { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000, {},
959 { .i2c_internal = false /* shield 0 */ } },
960 { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000, {},
961 { .i2c_internal = false /* shield 1 */ } },
962 },
963 }, {
964 .name = "apb_ppcexp2",
965 .ports = {
966 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 },
967 { "i2s-audio", make_unimp_dev, &mms->i2s_audio,
968 0x40301000, 0x1000 },
969 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 },
970 },
971 }, {
972 .name = "ahb_ppcexp0",
973 .ports = {
974 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 },
975 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 },
976 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 },
977 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 },
978 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 },
979 { "eth", make_eth_dev, NULL, 0x42000000, 0x100000, { 48 } },
980 },
981 }, {
982 .name = "ahb_ppcexp1",
983 .ports = {
984 { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000, { 58, 56, 57 } },
985 { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000, { 61, 59, 60 } },
986 { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000, { 64, 62, 63 } },
987 { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000, { 67, 65, 66 } },
988 },
989 },
990 };
991
992 const PPCInfo an524_ppcs[] = { {
993 .name = "apb_ppcexp0",
994 .ports = {
995 { "bram-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 },
996 { "qspi-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 },
997 { "ddr-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 },
998 },
999 }, {
1000 .name = "apb_ppcexp1",
1001 .ports = {
1002 { "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000, {},
1003 { .i2c_internal = true /* touchscreen */ } },
1004 { "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000, {},
1005 { .i2c_internal = true /* audio conf */ } },
1006 { "spi0", make_spi, &mms->spi[0], 0x41202000, 0x1000, { 52 } },
1007 { "spi1", make_spi, &mms->spi[1], 0x41203000, 0x1000, { 53 } },
1008 { "spi2", make_spi, &mms->spi[2], 0x41204000, 0x1000, { 54 } },
1009 { "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000, {},
1010 { .i2c_internal = false /* shield 0 */ } },
1011 { "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000, {},
1012 { .i2c_internal = false /* shield 1 */ } },
1013 { /* port 7 reserved */ },
1014 { "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000, {},
1015 { .i2c_internal = true /* DDR4 EEPROM */ } },
1016 },
1017 }, {
1018 .name = "apb_ppcexp2",
1019 .ports = {
1020 { "scc", make_scc, &mms->scc, 0x41300000, 0x1000 },
1021 { "i2s-audio", make_unimp_dev, &mms->i2s_audio,
1022 0x41301000, 0x1000 },
1023 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x41302000, 0x1000 },
1024 { "uart0", make_uart, &mms->uart[0], 0x41303000, 0x1000, { 32, 33, 42 } },
1025 { "uart1", make_uart, &mms->uart[1], 0x41304000, 0x1000, { 34, 35, 43 } },
1026 { "uart2", make_uart, &mms->uart[2], 0x41305000, 0x1000, { 36, 37, 44 } },
1027 { "uart3", make_uart, &mms->uart[3], 0x41306000, 0x1000, { 38, 39, 45 } },
1028 { "uart4", make_uart, &mms->uart[4], 0x41307000, 0x1000, { 40, 41, 46 } },
1029 { "uart5", make_uart, &mms->uart[5], 0x41308000, 0x1000, { 124, 125, 126 } },
1030
1031 { /* port 9 reserved */ },
1032 { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 },
1033 { "rtc", make_rtc, &mms->rtc, 0x4130b000, 0x1000 },
1034 },
1035 }, {
1036 .name = "ahb_ppcexp0",
1037 .ports = {
1038 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 },
1039 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 },
1040 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 },
1041 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 },
1042 { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 48 } },
1043 },
1044 },
1045 };
1046
1047 const PPCInfo an547_ppcs[] = { {
1048 .name = "apb_ppcexp0",
1049 .ports = {
1050 { "ssram-mpc", make_mpc, &mms->mpc[0], 0x57000000, 0x1000 },
1051 { "qspi-mpc", make_mpc, &mms->mpc[1], 0x57001000, 0x1000 },
1052 { "ddr-mpc", make_mpc, &mms->mpc[2], 0x57002000, 0x1000 },
1053 },
1054 }, {
1055 .name = "apb_ppcexp1",
1056 .ports = {
1057 { "i2c0", make_i2c, &mms->i2c[0], 0x49200000, 0x1000, {},
1058 { .i2c_internal = true /* touchscreen */ } },
1059 { "i2c1", make_i2c, &mms->i2c[1], 0x49201000, 0x1000, {},
1060 { .i2c_internal = true /* audio conf */ } },
1061 { "spi0", make_spi, &mms->spi[0], 0x49202000, 0x1000, { 53 } },
1062 { "spi1", make_spi, &mms->spi[1], 0x49203000, 0x1000, { 54 } },
1063 { "spi2", make_spi, &mms->spi[2], 0x49204000, 0x1000, { 55 } },
1064 { "i2c2", make_i2c, &mms->i2c[2], 0x49205000, 0x1000, {},
1065 { .i2c_internal = false /* shield 0 */ } },
1066 { "i2c3", make_i2c, &mms->i2c[3], 0x49206000, 0x1000, {},
1067 { .i2c_internal = false /* shield 1 */ } },
1068 { /* port 7 reserved */ },
1069 { "i2c4", make_i2c, &mms->i2c[4], 0x49208000, 0x1000, {},
1070 { .i2c_internal = true /* DDR4 EEPROM */ } },
1071 },
1072 }, {
1073 .name = "apb_ppcexp2",
1074 .ports = {
1075 { "scc", make_scc, &mms->scc, 0x49300000, 0x1000 },
1076 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 0x49301000, 0x1000 },
1077 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x49302000, 0x1000 },
1078 { "uart0", make_uart, &mms->uart[0], 0x49303000, 0x1000, { 33, 34, 43 } },
1079 { "uart1", make_uart, &mms->uart[1], 0x49304000, 0x1000, { 35, 36, 44 } },
1080 { "uart2", make_uart, &mms->uart[2], 0x49305000, 0x1000, { 37, 38, 45 } },
1081 { "uart3", make_uart, &mms->uart[3], 0x49306000, 0x1000, { 39, 40, 46 } },
1082 { "uart4", make_uart, &mms->uart[4], 0x49307000, 0x1000, { 41, 42, 47 } },
1083 { "uart5", make_uart, &mms->uart[5], 0x49308000, 0x1000, { 125, 126, 127 } },
1084
1085 { /* port 9 reserved */ },
1086 { "clcd", make_unimp_dev, &mms->cldc, 0x4930a000, 0x1000 },
1087 { "rtc", make_rtc, &mms->rtc, 0x4930b000, 0x1000 },
1088 },
1089 }, {
1090 .name = "ahb_ppcexp0",
1091 .ports = {
1092 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 },
1093 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 },
1094 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 },
1095 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 },
1096 { /* port 4 USER AHB interface 0 */ },
1097 { /* port 5 USER AHB interface 1 */ },
1098 { /* port 6 USER AHB interface 2 */ },
1099 { /* port 7 USER AHB interface 3 */ },
1100 { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 49 } },
1101 },
1102 },
1103 };
1104
1105 switch (mmc->fpga_type) {
1106 case FPGA_AN505:
1107 case FPGA_AN521:
1108 ppcs = an505_ppcs;
1109 num_ppcs = ARRAY_SIZE(an505_ppcs);
1110 break;
1111 case FPGA_AN524:
1112 ppcs = an524_ppcs;
1113 num_ppcs = ARRAY_SIZE(an524_ppcs);
1114 break;
1115 case FPGA_AN547:
1116 ppcs = an547_ppcs;
1117 num_ppcs = ARRAY_SIZE(an547_ppcs);
1118 break;
1119 default:
1120 g_assert_not_reached();
1121 }
1122
1123 for (i = 0; i < num_ppcs; i++) {
1124 const PPCInfo *ppcinfo = &ppcs[i];
1125 TZPPC *ppc = &mms->ppc[i];
1126 DeviceState *ppcdev;
1127 int port;
1128 char *gpioname;
1129
1130 object_initialize_child(OBJECT(machine), ppcinfo->name, ppc,
1131 TYPE_TZ_PPC);
1132 ppcdev = DEVICE(ppc);
1133
1134 for (port = 0; port < TZ_NUM_PORTS; port++) {
1135 const PPCPortInfo *pinfo = &ppcinfo->ports[port];
1136 MemoryRegion *mr;
1137 char *portname;
1138
1139 if (!pinfo->devfn) {
1140 continue;
1141 }
1142
1143 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size,
1144 pinfo->irqs, &pinfo->extradata);
1145 portname = g_strdup_printf("port[%d]", port);
1146 object_property_set_link(OBJECT(ppc), portname, OBJECT(mr),
1147 &error_fatal);
1148 g_free(portname);
1149 }
1150
1151 sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal);
1152
1153 for (port = 0; port < TZ_NUM_PORTS; port++) {
1154 const PPCPortInfo *pinfo = &ppcinfo->ports[port];
1155
1156 if (!pinfo->devfn) {
1157 continue;
1158 }
1159 sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr);
1160
1161 gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name);
1162 qdev_connect_gpio_out_named(iotkitdev, gpioname, port,
1163 qdev_get_gpio_in_named(ppcdev,
1164 "cfg_nonsec",
1165 port));
1166 g_free(gpioname);
1167 gpioname = g_strdup_printf("%s_ap", ppcinfo->name);
1168 qdev_connect_gpio_out_named(iotkitdev, gpioname, port,
1169 qdev_get_gpio_in_named(ppcdev,
1170 "cfg_ap", port));
1171 g_free(gpioname);
1172 }
1173
1174 gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name);
1175 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0,
1176 qdev_get_gpio_in_named(ppcdev,
1177 "irq_enable", 0));
1178 g_free(gpioname);
1179 gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name);
1180 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0,
1181 qdev_get_gpio_in_named(ppcdev,
1182 "irq_clear", 0));
1183 g_free(gpioname);
1184 gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name);
1185 qdev_connect_gpio_out_named(ppcdev, "irq", 0,
1186 qdev_get_gpio_in_named(iotkitdev,
1187 gpioname, 0));
1188 g_free(gpioname);
1189
1190 qdev_connect_gpio_out(dev_splitter, i,
1191 qdev_get_gpio_in_named(ppcdev,
1192 "cfg_sec_resp", 0));
1193 }
1194
1195 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000);
1196
1197 if (mmc->fpga_type == FPGA_AN547) {
1198 create_unimplemented_device("U55 timing adapter 0", 0x48102000, 0x1000);
1199 create_unimplemented_device("U55 timing adapter 1", 0x48103000, 0x1000);
1200 }
1201
1202 create_non_mpc_ram(mms);
1203
1204 if (mmc->fpga_type == FPGA_AN524) {
1205 /*
1206 * Connect the line from the SCC so that we can remap when the
1207 * guest updates that register.
1208 */
1209 mms->remap_irq = qemu_allocate_irq(remap_irq_fn, mms, 0);
1210 qdev_connect_gpio_out_named(DEVICE(&mms->scc), "remap", 0,
1211 mms->remap_irq);
1212 }
1213
1214 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
1215 0, boot_ram_size(mms));
1216 }
1217
mps2_tz_idau_check(IDAUInterface * ii,uint32_t address,int * iregion,bool * exempt,bool * ns,bool * nsc)1218 static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address,
1219 int *iregion, bool *exempt, bool *ns, bool *nsc)
1220 {
1221 /*
1222 * The MPS2 TZ FPGA images have IDAUs in them which are connected to
1223 * the Master Security Controllers. These have the same logic as
1224 * is used by the IoTKit for the IDAU connected to the CPU, except
1225 * that MSCs don't care about the NSC attribute.
1226 */
1227 int region = extract32(address, 28, 4);
1228
1229 *ns = !(region & 1);
1230 *nsc = false;
1231 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */
1232 *exempt = (address & 0xeff00000) == 0xe0000000;
1233 *iregion = region;
1234 }
1235
mps2_get_remap(Object * obj,Error ** errp)1236 static char *mps2_get_remap(Object *obj, Error **errp)
1237 {
1238 MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj);
1239 const char *val = mms->remap ? "QSPI" : "BRAM";
1240 return g_strdup(val);
1241 }
1242
mps2_set_remap(Object * obj,const char * value,Error ** errp)1243 static void mps2_set_remap(Object *obj, const char *value, Error **errp)
1244 {
1245 MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj);
1246
1247 if (!strcmp(value, "BRAM")) {
1248 mms->remap = false;
1249 } else if (!strcmp(value, "QSPI")) {
1250 mms->remap = true;
1251 } else {
1252 error_setg(errp, "Invalid remap value");
1253 error_append_hint(errp, "Valid values are BRAM and QSPI.\n");
1254 }
1255 }
1256
mps2_machine_reset(MachineState * machine,ShutdownCause reason)1257 static void mps2_machine_reset(MachineState *machine, ShutdownCause reason)
1258 {
1259 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine);
1260
1261 /*
1262 * Set the initial memory mapping before triggering the reset of
1263 * the rest of the system, so that the guest image loader and CPU
1264 * reset see the correct mapping.
1265 */
1266 remap_memory(mms, mms->remap);
1267 qemu_devices_reset(reason);
1268 }
1269
mps2tz_class_init(ObjectClass * oc,void * data)1270 static void mps2tz_class_init(ObjectClass *oc, void *data)
1271 {
1272 MachineClass *mc = MACHINE_CLASS(oc);
1273 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc);
1274 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
1275
1276 mc->init = mps2tz_common_init;
1277 mc->reset = mps2_machine_reset;
1278 iic->check = mps2_tz_idau_check;
1279
1280 /* Most machines leave these at the SSE defaults */
1281 mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT;
1282 mmc->cpu0_mpu_s = MPU_REGION_DEFAULT;
1283 mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT;
1284 mmc->cpu1_mpu_s = MPU_REGION_DEFAULT;
1285 }
1286
mps2tz_set_default_ram_info(MPS2TZMachineClass * mmc)1287 static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc)
1288 {
1289 /*
1290 * Set mc->default_ram_size and default_ram_id from the
1291 * information in mmc->raminfo.
1292 */
1293 MachineClass *mc = MACHINE_CLASS(mmc);
1294 const RAMInfo *p;
1295
1296 for (p = mmc->raminfo; p->name; p++) {
1297 if (p->mrindex < 0) {
1298 /* Found the entry for "system memory" */
1299 mc->default_ram_size = p->size;
1300 mc->default_ram_id = p->name;
1301 return;
1302 }
1303 }
1304 g_assert_not_reached();
1305 }
1306
mps2tz_an505_class_init(ObjectClass * oc,void * data)1307 static void mps2tz_an505_class_init(ObjectClass *oc, void *data)
1308 {
1309 MachineClass *mc = MACHINE_CLASS(oc);
1310 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
1311 static const char * const valid_cpu_types[] = {
1312 ARM_CPU_TYPE_NAME("cortex-m33"),
1313 NULL
1314 };
1315
1316 mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33";
1317 mc->default_cpus = 1;
1318 mc->min_cpus = mc->default_cpus;
1319 mc->max_cpus = mc->default_cpus;
1320 mmc->fpga_type = FPGA_AN505;
1321 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
1322 mc->valid_cpu_types = valid_cpu_types;
1323 mmc->scc_id = 0x41045050;
1324 mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */
1325 mmc->apb_periph_frq = mmc->sysclk_frq;
1326 mmc->oscclk = an505_oscclk;
1327 mmc->len_oscclk = ARRAY_SIZE(an505_oscclk);
1328 mmc->fpgaio_num_leds = 2;
1329 mmc->fpgaio_has_switches = false;
1330 mmc->fpgaio_has_dbgctrl = false;
1331 mmc->numirq = 92;
1332 mmc->uart_overflow_irq = 47;
1333 mmc->init_svtor = 0x10000000;
1334 mmc->sram_addr_width = 15;
1335 mmc->raminfo = an505_raminfo;
1336 mmc->armsse_type = TYPE_IOTKIT;
1337 mmc->boot_ram_size = 0;
1338 mps2tz_set_default_ram_info(mmc);
1339 }
1340
mps2tz_an521_class_init(ObjectClass * oc,void * data)1341 static void mps2tz_an521_class_init(ObjectClass *oc, void *data)
1342 {
1343 MachineClass *mc = MACHINE_CLASS(oc);
1344 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
1345 static const char * const valid_cpu_types[] = {
1346 ARM_CPU_TYPE_NAME("cortex-m33"),
1347 NULL
1348 };
1349
1350 mc->desc = "ARM MPS2 with AN521 FPGA image for dual Cortex-M33";
1351 mc->default_cpus = 2;
1352 mc->min_cpus = mc->default_cpus;
1353 mc->max_cpus = mc->default_cpus;
1354 mmc->fpga_type = FPGA_AN521;
1355 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
1356 mc->valid_cpu_types = valid_cpu_types;
1357 mmc->scc_id = 0x41045210;
1358 mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */
1359 mmc->apb_periph_frq = mmc->sysclk_frq;
1360 mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */
1361 mmc->len_oscclk = ARRAY_SIZE(an505_oscclk);
1362 mmc->fpgaio_num_leds = 2;
1363 mmc->fpgaio_has_switches = false;
1364 mmc->fpgaio_has_dbgctrl = false;
1365 mmc->numirq = 92;
1366 mmc->uart_overflow_irq = 47;
1367 mmc->init_svtor = 0x10000000;
1368 mmc->sram_addr_width = 15;
1369 mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */
1370 mmc->armsse_type = TYPE_SSE200;
1371 mmc->boot_ram_size = 0;
1372 mps2tz_set_default_ram_info(mmc);
1373 }
1374
mps3tz_an524_class_init(ObjectClass * oc,void * data)1375 static void mps3tz_an524_class_init(ObjectClass *oc, void *data)
1376 {
1377 MachineClass *mc = MACHINE_CLASS(oc);
1378 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
1379 static const char * const valid_cpu_types[] = {
1380 ARM_CPU_TYPE_NAME("cortex-m33"),
1381 NULL
1382 };
1383
1384 mc->desc = "ARM MPS3 with AN524 FPGA image for dual Cortex-M33";
1385 mc->default_cpus = 2;
1386 mc->min_cpus = mc->default_cpus;
1387 mc->max_cpus = mc->default_cpus;
1388 mmc->fpga_type = FPGA_AN524;
1389 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
1390 mc->valid_cpu_types = valid_cpu_types;
1391 mmc->scc_id = 0x41045240;
1392 mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */
1393 mmc->apb_periph_frq = mmc->sysclk_frq;
1394 mmc->oscclk = an524_oscclk;
1395 mmc->len_oscclk = ARRAY_SIZE(an524_oscclk);
1396 mmc->fpgaio_num_leds = 10;
1397 mmc->fpgaio_has_switches = true;
1398 mmc->fpgaio_has_dbgctrl = false;
1399 mmc->numirq = 95;
1400 mmc->uart_overflow_irq = 47;
1401 mmc->init_svtor = 0x10000000;
1402 mmc->sram_addr_width = 15;
1403 mmc->raminfo = an524_raminfo;
1404 mmc->armsse_type = TYPE_SSE200;
1405 mmc->boot_ram_size = 0;
1406 mps2tz_set_default_ram_info(mmc);
1407
1408 object_class_property_add_str(oc, "remap", mps2_get_remap, mps2_set_remap);
1409 object_class_property_set_description(oc, "remap",
1410 "Set memory mapping. Valid values "
1411 "are BRAM (default) and QSPI.");
1412 }
1413
mps3tz_an547_class_init(ObjectClass * oc,void * data)1414 static void mps3tz_an547_class_init(ObjectClass *oc, void *data)
1415 {
1416 MachineClass *mc = MACHINE_CLASS(oc);
1417 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
1418 static const char * const valid_cpu_types[] = {
1419 ARM_CPU_TYPE_NAME("cortex-m55"),
1420 NULL
1421 };
1422
1423 mc->desc = "ARM MPS3 with AN547 FPGA image for Cortex-M55";
1424 mc->default_cpus = 1;
1425 mc->min_cpus = mc->default_cpus;
1426 mc->max_cpus = mc->default_cpus;
1427 mmc->fpga_type = FPGA_AN547;
1428 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m55");
1429 mc->valid_cpu_types = valid_cpu_types;
1430 mmc->scc_id = 0x41055470;
1431 mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */
1432 mmc->apb_periph_frq = 25 * 1000 * 1000; /* 25MHz */
1433 mmc->oscclk = an524_oscclk; /* same as AN524 */
1434 mmc->len_oscclk = ARRAY_SIZE(an524_oscclk);
1435 mmc->fpgaio_num_leds = 10;
1436 mmc->fpgaio_has_switches = true;
1437 mmc->fpgaio_has_dbgctrl = true;
1438 mmc->numirq = 96;
1439 mmc->uart_overflow_irq = 48;
1440 mmc->init_svtor = 0x00000000;
1441 mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16;
1442 mmc->sram_addr_width = 21;
1443 mmc->raminfo = an547_raminfo;
1444 mmc->armsse_type = TYPE_SSE300;
1445 mmc->boot_ram_size = 512 * KiB;
1446 mps2tz_set_default_ram_info(mmc);
1447 }
1448
1449 static const TypeInfo mps2tz_info = {
1450 .name = TYPE_MPS2TZ_MACHINE,
1451 .parent = TYPE_MACHINE,
1452 .abstract = true,
1453 .instance_size = sizeof(MPS2TZMachineState),
1454 .class_size = sizeof(MPS2TZMachineClass),
1455 .class_init = mps2tz_class_init,
1456 .interfaces = (InterfaceInfo[]) {
1457 { TYPE_IDAU_INTERFACE },
1458 { }
1459 },
1460 };
1461
1462 static const TypeInfo mps2tz_an505_info = {
1463 .name = TYPE_MPS2TZ_AN505_MACHINE,
1464 .parent = TYPE_MPS2TZ_MACHINE,
1465 .class_init = mps2tz_an505_class_init,
1466 };
1467
1468 static const TypeInfo mps2tz_an521_info = {
1469 .name = TYPE_MPS2TZ_AN521_MACHINE,
1470 .parent = TYPE_MPS2TZ_MACHINE,
1471 .class_init = mps2tz_an521_class_init,
1472 };
1473
1474 static const TypeInfo mps3tz_an524_info = {
1475 .name = TYPE_MPS3TZ_AN524_MACHINE,
1476 .parent = TYPE_MPS2TZ_MACHINE,
1477 .class_init = mps3tz_an524_class_init,
1478 };
1479
1480 static const TypeInfo mps3tz_an547_info = {
1481 .name = TYPE_MPS3TZ_AN547_MACHINE,
1482 .parent = TYPE_MPS2TZ_MACHINE,
1483 .class_init = mps3tz_an547_class_init,
1484 };
1485
mps2tz_machine_init(void)1486 static void mps2tz_machine_init(void)
1487 {
1488 type_register_static(&mps2tz_info);
1489 type_register_static(&mps2tz_an505_info);
1490 type_register_static(&mps2tz_an521_info);
1491 type_register_static(&mps3tz_an524_info);
1492 type_register_static(&mps3tz_an547_info);
1493 }
1494
1495 type_init(mps2tz_machine_init);
1496