1 /* 2 * MAX78000 SOC 3 * 4 * Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 * 8 * Implementation based on stm32f205 and Max78000 user guide at 9 * https://www.analog.com/media/en/technical-documentation/user-guides/max78000-user-guide.pdf 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "system/address-spaces.h" 15 #include "system/system.h" 16 #include "hw/arm/max78000_soc.h" 17 #include "hw/qdev-clock.h" 18 #include "hw/misc/unimp.h" 19 20 static const uint32_t max78000_icc_addr[] = {0x4002a000, 0x4002a800}; 21 static const uint32_t max78000_uart_addr[] = {0x40042000, 0x40043000, 22 0x40044000}; 23 24 static const int max78000_uart_irq[] = {14, 15, 34}; 25 26 static void max78000_soc_initfn(Object *obj) 27 { 28 MAX78000State *s = MAX78000_SOC(obj); 29 int i; 30 31 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); 32 33 for (i = 0; i < MAX78000_NUM_ICC; i++) { 34 g_autofree char *name = g_strdup_printf("icc%d", i); 35 object_initialize_child(obj, name, &s->icc[i], TYPE_MAX78000_ICC); 36 } 37 38 for (i = 0; i < MAX78000_NUM_UART; i++) { 39 g_autofree char *name = g_strdup_printf("uart%d", i); 40 object_initialize_child(obj, name, &s->uart[i], 41 TYPE_MAX78000_UART); 42 } 43 44 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); 45 } 46 47 static void max78000_soc_realize(DeviceState *dev_soc, Error **errp) 48 { 49 MAX78000State *s = MAX78000_SOC(dev_soc); 50 MemoryRegion *system_memory = get_system_memory(); 51 DeviceState *dev, *armv7m; 52 SysBusDevice *busdev; 53 Error *err = NULL; 54 int i; 55 56 if (!clock_has_source(s->sysclk)) { 57 error_setg(errp, "sysclk clock must be wired up by the board code"); 58 return; 59 } 60 61 memory_region_init_rom(&s->flash, OBJECT(dev_soc), "MAX78000.flash", 62 FLASH_SIZE, &err); 63 if (err != NULL) { 64 error_propagate(errp, err); 65 return; 66 } 67 68 memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash); 69 70 memory_region_init_ram(&s->sram, NULL, "MAX78000.sram", SRAM_SIZE, 71 &err); 72 if (err != NULL) { 73 error_propagate(errp, err); 74 return; 75 } 76 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram); 77 78 armv7m = DEVICE(&s->armv7m); 79 80 /* 81 * The MAX78000 user guide's Interrupt Vector Table section 82 * suggests that there are 120 IRQs in the text, while only listing 83 * 104 in table 5-1. Implement the more generous of the two. 84 * This has not been tested in hardware. 85 */ 86 qdev_prop_set_uint32(armv7m, "num-irq", 120); 87 qdev_prop_set_uint8(armv7m, "num-prio-bits", 3); 88 qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); 89 qdev_prop_set_bit(armv7m, "enable-bitband", true); 90 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); 91 object_property_set_link(OBJECT(&s->armv7m), "memory", 92 OBJECT(system_memory), &error_abort); 93 if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { 94 return; 95 } 96 97 for (i = 0; i < MAX78000_NUM_ICC; i++) { 98 dev = DEVICE(&(s->icc[i])); 99 sysbus_realize(SYS_BUS_DEVICE(dev), errp); 100 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, max78000_icc_addr[i]); 101 } 102 103 for (i = 0; i < MAX78000_NUM_UART; i++) { 104 dev = DEVICE(&(s->uart[i])); 105 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 106 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { 107 return; 108 } 109 110 busdev = SYS_BUS_DEVICE(dev); 111 sysbus_mmio_map(busdev, 0, max78000_uart_addr[i]); 112 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 113 max78000_uart_irq[i])); 114 } 115 116 create_unimplemented_device("globalControl", 0x40000000, 0x400); 117 create_unimplemented_device("systemInterface", 0x40000400, 0x400); 118 create_unimplemented_device("functionControl", 0x40000800, 0x400); 119 create_unimplemented_device("watchdogTimer0", 0x40003000, 0x400); 120 create_unimplemented_device("dynamicVoltScale", 0x40003c00, 0x40); 121 create_unimplemented_device("SIMO", 0x40004400, 0x400); 122 create_unimplemented_device("trimSystemInit", 0x40005400, 0x400); 123 create_unimplemented_device("generalCtrlFunc", 0x40005800, 0x400); 124 create_unimplemented_device("wakeupTimer", 0x40006400, 0x400); 125 create_unimplemented_device("powerSequencer", 0x40006800, 0x400); 126 create_unimplemented_device("miscControl", 0x40006c00, 0x400); 127 128 create_unimplemented_device("aes", 0x40007400, 0x400); 129 create_unimplemented_device("aesKey", 0x40007800, 0x400); 130 131 create_unimplemented_device("gpio0", 0x40008000, 0x1000); 132 create_unimplemented_device("gpio1", 0x40009000, 0x1000); 133 134 create_unimplemented_device("parallelCamInterface", 0x4000e000, 0x1000); 135 create_unimplemented_device("CRC", 0x4000f000, 0x1000); 136 137 create_unimplemented_device("timer0", 0x40010000, 0x1000); 138 create_unimplemented_device("timer1", 0x40011000, 0x1000); 139 create_unimplemented_device("timer2", 0x40012000, 0x1000); 140 create_unimplemented_device("timer3", 0x40013000, 0x1000); 141 142 create_unimplemented_device("i2c0", 0x4001d000, 0x1000); 143 create_unimplemented_device("i2c1", 0x4001e000, 0x1000); 144 create_unimplemented_device("i2c2", 0x4001f000, 0x1000); 145 146 create_unimplemented_device("standardDMA", 0x40028000, 0x1000); 147 create_unimplemented_device("flashController0", 0x40029000, 0x400); 148 149 create_unimplemented_device("adc", 0x40034000, 0x1000); 150 create_unimplemented_device("pulseTrainEngine", 0x4003c000, 0xa0); 151 create_unimplemented_device("oneWireMaster", 0x4003d000, 0x1000); 152 create_unimplemented_device("semaphore", 0x4003e000, 0x1000); 153 154 create_unimplemented_device("spi1", 0x40046000, 0x2000); 155 create_unimplemented_device("trng", 0x4004d000, 0x1000); 156 create_unimplemented_device("i2s", 0x40060000, 0x1000); 157 create_unimplemented_device("lowPowerControl", 0x40080000, 0x400); 158 create_unimplemented_device("gpio2", 0x40080400, 0x200); 159 create_unimplemented_device("lowPowerWatchdogTimer", 0x40080800, 0x400); 160 create_unimplemented_device("lowPowerTimer4", 0x40080c00, 0x400); 161 162 create_unimplemented_device("lowPowerTimer5", 0x40081000, 0x400); 163 create_unimplemented_device("lowPowerUART0", 0x40081400, 0x400); 164 create_unimplemented_device("lowPowerComparator", 0x40088000, 0x400); 165 166 create_unimplemented_device("spi0", 0x400be000, 0x400); 167 168 /* 169 * The MAX78000 user guide's base address map lists the CNN TX FIFO as 170 * beginning at 0x400c0400 and ending at 0x400c0400. Given that CNN_FIFO 171 * is listed as having data accessible up to offset 0x1000, the user 172 * guide is likely incorrect. 173 */ 174 create_unimplemented_device("cnnTxFIFO", 0x400c0400, 0x2000); 175 176 create_unimplemented_device("cnnGlobalControl", 0x50000000, 0x10000); 177 create_unimplemented_device("cnnx16quad0", 0x50100000, 0x40000); 178 create_unimplemented_device("cnnx16quad1", 0x50500000, 0x40000); 179 create_unimplemented_device("cnnx16quad2", 0x50900000, 0x40000); 180 create_unimplemented_device("cnnx16quad3", 0x50d00000, 0x40000); 181 182 } 183 184 static void max78000_soc_class_init(ObjectClass *klass, const void *data) 185 { 186 DeviceClass *dc = DEVICE_CLASS(klass); 187 188 dc->realize = max78000_soc_realize; 189 } 190 191 static const TypeInfo max78000_soc_info = { 192 .name = TYPE_MAX78000_SOC, 193 .parent = TYPE_SYS_BUS_DEVICE, 194 .instance_size = sizeof(MAX78000State), 195 .instance_init = max78000_soc_initfn, 196 .class_init = max78000_soc_class_init, 197 }; 198 199 static void max78000_soc_types(void) 200 { 201 type_register_static(&max78000_soc_info); 202 } 203 204 type_init(max78000_soc_types) 205