1 /* 2 * MAX78000 SOC 3 * 4 * Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 * 8 * Implementation based on stm32f205 and Max78000 user guide at 9 * https://www.analog.com/media/en/technical-documentation/user-guides/max78000-user-guide.pdf 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "system/address-spaces.h" 15 #include "system/system.h" 16 #include "hw/arm/max78000_soc.h" 17 #include "hw/qdev-clock.h" 18 #include "hw/misc/unimp.h" 19 20 static const uint32_t max78000_icc_addr[] = {0x4002a000, 0x4002a800}; 21 static const uint32_t max78000_uart_addr[] = {0x40042000, 0x40043000, 22 0x40044000}; 23 24 static const int max78000_uart_irq[] = {14, 15, 34}; 25 26 static void max78000_soc_initfn(Object *obj) 27 { 28 MAX78000State *s = MAX78000_SOC(obj); 29 int i; 30 31 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); 32 33 object_initialize_child(obj, "gcr", &s->gcr, TYPE_MAX78000_GCR); 34 35 for (i = 0; i < MAX78000_NUM_ICC; i++) { 36 g_autofree char *name = g_strdup_printf("icc%d", i); 37 object_initialize_child(obj, name, &s->icc[i], TYPE_MAX78000_ICC); 38 } 39 40 for (i = 0; i < MAX78000_NUM_UART; i++) { 41 g_autofree char *name = g_strdup_printf("uart%d", i); 42 object_initialize_child(obj, name, &s->uart[i], 43 TYPE_MAX78000_UART); 44 } 45 46 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); 47 } 48 49 static void max78000_soc_realize(DeviceState *dev_soc, Error **errp) 50 { 51 MAX78000State *s = MAX78000_SOC(dev_soc); 52 MemoryRegion *system_memory = get_system_memory(); 53 DeviceState *dev, *gcrdev, *armv7m; 54 SysBusDevice *busdev; 55 Error *err = NULL; 56 int i; 57 58 if (!clock_has_source(s->sysclk)) { 59 error_setg(errp, "sysclk clock must be wired up by the board code"); 60 return; 61 } 62 63 memory_region_init_rom(&s->flash, OBJECT(dev_soc), "MAX78000.flash", 64 FLASH_SIZE, &err); 65 if (err != NULL) { 66 error_propagate(errp, err); 67 return; 68 } 69 70 memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash); 71 72 memory_region_init_ram(&s->sram, NULL, "MAX78000.sram", SRAM_SIZE, 73 &err); 74 75 gcrdev = DEVICE(&s->gcr); 76 object_property_set_link(OBJECT(gcrdev), "sram", OBJECT(&s->sram), 77 &err); 78 79 if (err != NULL) { 80 error_propagate(errp, err); 81 return; 82 } 83 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram); 84 85 armv7m = DEVICE(&s->armv7m); 86 87 /* 88 * The MAX78000 user guide's Interrupt Vector Table section 89 * suggests that there are 120 IRQs in the text, while only listing 90 * 104 in table 5-1. Implement the more generous of the two. 91 * This has not been tested in hardware. 92 */ 93 qdev_prop_set_uint32(armv7m, "num-irq", 120); 94 qdev_prop_set_uint8(armv7m, "num-prio-bits", 3); 95 qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); 96 qdev_prop_set_bit(armv7m, "enable-bitband", true); 97 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); 98 object_property_set_link(OBJECT(&s->armv7m), "memory", 99 OBJECT(system_memory), &error_abort); 100 if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { 101 return; 102 } 103 104 for (i = 0; i < MAX78000_NUM_ICC; i++) { 105 dev = DEVICE(&(s->icc[i])); 106 sysbus_realize(SYS_BUS_DEVICE(dev), errp); 107 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, max78000_icc_addr[i]); 108 } 109 110 for (i = 0; i < MAX78000_NUM_UART; i++) { 111 g_autofree char *link = g_strdup_printf("uart%d", i); 112 dev = DEVICE(&(s->uart[i])); 113 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 114 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { 115 return; 116 } 117 118 object_property_set_link(OBJECT(gcrdev), link, OBJECT(dev), 119 &err); 120 121 busdev = SYS_BUS_DEVICE(dev); 122 sysbus_mmio_map(busdev, 0, max78000_uart_addr[i]); 123 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 124 max78000_uart_irq[i])); 125 } 126 127 dev = DEVICE(&s->gcr); 128 sysbus_realize(SYS_BUS_DEVICE(dev), errp); 129 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x40000000); 130 131 create_unimplemented_device("systemInterface", 0x40000400, 0x400); 132 create_unimplemented_device("functionControl", 0x40000800, 0x400); 133 create_unimplemented_device("watchdogTimer0", 0x40003000, 0x400); 134 create_unimplemented_device("dynamicVoltScale", 0x40003c00, 0x40); 135 create_unimplemented_device("SIMO", 0x40004400, 0x400); 136 create_unimplemented_device("trimSystemInit", 0x40005400, 0x400); 137 create_unimplemented_device("generalCtrlFunc", 0x40005800, 0x400); 138 create_unimplemented_device("wakeupTimer", 0x40006400, 0x400); 139 create_unimplemented_device("powerSequencer", 0x40006800, 0x400); 140 create_unimplemented_device("miscControl", 0x40006c00, 0x400); 141 142 create_unimplemented_device("aes", 0x40007400, 0x400); 143 create_unimplemented_device("aesKey", 0x40007800, 0x400); 144 145 create_unimplemented_device("gpio0", 0x40008000, 0x1000); 146 create_unimplemented_device("gpio1", 0x40009000, 0x1000); 147 148 create_unimplemented_device("parallelCamInterface", 0x4000e000, 0x1000); 149 create_unimplemented_device("CRC", 0x4000f000, 0x1000); 150 151 create_unimplemented_device("timer0", 0x40010000, 0x1000); 152 create_unimplemented_device("timer1", 0x40011000, 0x1000); 153 create_unimplemented_device("timer2", 0x40012000, 0x1000); 154 create_unimplemented_device("timer3", 0x40013000, 0x1000); 155 156 create_unimplemented_device("i2c0", 0x4001d000, 0x1000); 157 create_unimplemented_device("i2c1", 0x4001e000, 0x1000); 158 create_unimplemented_device("i2c2", 0x4001f000, 0x1000); 159 160 create_unimplemented_device("standardDMA", 0x40028000, 0x1000); 161 create_unimplemented_device("flashController0", 0x40029000, 0x400); 162 163 create_unimplemented_device("adc", 0x40034000, 0x1000); 164 create_unimplemented_device("pulseTrainEngine", 0x4003c000, 0xa0); 165 create_unimplemented_device("oneWireMaster", 0x4003d000, 0x1000); 166 create_unimplemented_device("semaphore", 0x4003e000, 0x1000); 167 168 create_unimplemented_device("spi1", 0x40046000, 0x2000); 169 create_unimplemented_device("trng", 0x4004d000, 0x1000); 170 create_unimplemented_device("i2s", 0x40060000, 0x1000); 171 create_unimplemented_device("lowPowerControl", 0x40080000, 0x400); 172 create_unimplemented_device("gpio2", 0x40080400, 0x200); 173 create_unimplemented_device("lowPowerWatchdogTimer", 0x40080800, 0x400); 174 create_unimplemented_device("lowPowerTimer4", 0x40080c00, 0x400); 175 176 create_unimplemented_device("lowPowerTimer5", 0x40081000, 0x400); 177 create_unimplemented_device("lowPowerUART0", 0x40081400, 0x400); 178 create_unimplemented_device("lowPowerComparator", 0x40088000, 0x400); 179 180 create_unimplemented_device("spi0", 0x400be000, 0x400); 181 182 /* 183 * The MAX78000 user guide's base address map lists the CNN TX FIFO as 184 * beginning at 0x400c0400 and ending at 0x400c0400. Given that CNN_FIFO 185 * is listed as having data accessible up to offset 0x1000, the user 186 * guide is likely incorrect. 187 */ 188 create_unimplemented_device("cnnTxFIFO", 0x400c0400, 0x2000); 189 190 create_unimplemented_device("cnnGlobalControl", 0x50000000, 0x10000); 191 create_unimplemented_device("cnnx16quad0", 0x50100000, 0x40000); 192 create_unimplemented_device("cnnx16quad1", 0x50500000, 0x40000); 193 create_unimplemented_device("cnnx16quad2", 0x50900000, 0x40000); 194 create_unimplemented_device("cnnx16quad3", 0x50d00000, 0x40000); 195 196 } 197 198 static void max78000_soc_class_init(ObjectClass *klass, const void *data) 199 { 200 DeviceClass *dc = DEVICE_CLASS(klass); 201 202 dc->realize = max78000_soc_realize; 203 } 204 205 static const TypeInfo max78000_soc_info = { 206 .name = TYPE_MAX78000_SOC, 207 .parent = TYPE_SYS_BUS_DEVICE, 208 .instance_size = sizeof(MAX78000State), 209 .instance_init = max78000_soc_initfn, 210 .class_init = max78000_soc_class_init, 211 }; 212 213 static void max78000_soc_types(void) 214 { 215 type_register_static(&max78000_soc_info); 216 } 217 218 type_init(max78000_soc_types) 219