1 /* 2 * PXA270-based Intel Mainstone platforms. 3 * 4 * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or 5 * <akuster@mvista.com> 6 * 7 * Code based on spitz platform by Andrzej Zaborowski <balrog@zabor.org> 8 * 9 * This code is licensed under the GNU GPL v2. 10 * 11 * Contributions after 2012-01-13 are licensed under the terms of the 12 * GNU GPL, version 2 or (at your option) any later version. 13 */ 14 #include "hw/hw.h" 15 #include "hw/arm/pxa.h" 16 #include "hw/arm/arm.h" 17 #include "net/net.h" 18 #include "hw/devices.h" 19 #include "hw/boards.h" 20 #include "hw/block/flash.h" 21 #include "sysemu/blockdev.h" 22 #include "hw/sysbus.h" 23 #include "exec/address-spaces.h" 24 25 /* Device addresses */ 26 #define MST_FPGA_PHYS 0x08000000 27 #define MST_ETH_PHYS 0x10000300 28 #define MST_FLASH_0 0x00000000 29 #define MST_FLASH_1 0x04000000 30 31 /* IRQ definitions */ 32 #define MMC_IRQ 0 33 #define USIM_IRQ 1 34 #define USBC_IRQ 2 35 #define ETHERNET_IRQ 3 36 #define AC97_IRQ 4 37 #define PEN_IRQ 5 38 #define MSINS_IRQ 6 39 #define EXBRD_IRQ 7 40 #define S0_CD_IRQ 9 41 #define S0_STSCHG_IRQ 10 42 #define S0_IRQ 11 43 #define S1_CD_IRQ 13 44 #define S1_STSCHG_IRQ 14 45 #define S1_IRQ 15 46 47 static struct keymap map[0xE0] = { 48 [0 ... 0xDF] = { -1, -1 }, 49 [0x1e] = {0,0}, /* a */ 50 [0x30] = {0,1}, /* b */ 51 [0x2e] = {0,2}, /* c */ 52 [0x20] = {0,3}, /* d */ 53 [0x12] = {0,4}, /* e */ 54 [0x21] = {0,5}, /* f */ 55 [0x22] = {1,0}, /* g */ 56 [0x23] = {1,1}, /* h */ 57 [0x17] = {1,2}, /* i */ 58 [0x24] = {1,3}, /* j */ 59 [0x25] = {1,4}, /* k */ 60 [0x26] = {1,5}, /* l */ 61 [0x32] = {2,0}, /* m */ 62 [0x31] = {2,1}, /* n */ 63 [0x18] = {2,2}, /* o */ 64 [0x19] = {2,3}, /* p */ 65 [0x10] = {2,4}, /* q */ 66 [0x13] = {2,5}, /* r */ 67 [0x1f] = {3,0}, /* s */ 68 [0x14] = {3,1}, /* t */ 69 [0x16] = {3,2}, /* u */ 70 [0x2f] = {3,3}, /* v */ 71 [0x11] = {3,4}, /* w */ 72 [0x2d] = {3,5}, /* x */ 73 [0x15] = {4,2}, /* y */ 74 [0x2c] = {4,3}, /* z */ 75 [0xc7] = {5,0}, /* Home */ 76 [0x2a] = {5,1}, /* shift */ 77 [0x39] = {5,2}, /* space */ 78 [0x39] = {5,3}, /* space */ 79 [0x1c] = {5,5}, /* enter */ 80 [0xc8] = {6,0}, /* up */ 81 [0xd0] = {6,1}, /* down */ 82 [0xcb] = {6,2}, /* left */ 83 [0xcd] = {6,3}, /* right */ 84 }; 85 86 enum mainstone_model_e { mainstone }; 87 88 #define MAINSTONE_RAM 0x04000000 89 #define MAINSTONE_ROM 0x00800000 90 #define MAINSTONE_FLASH 0x02000000 91 92 static struct arm_boot_info mainstone_binfo = { 93 .loader_start = PXA2XX_SDRAM_BASE, 94 .ram_size = 0x04000000, 95 }; 96 97 static void mainstone_common_init(MemoryRegion *address_space_mem, 98 QEMUMachineInitArgs *args, 99 enum mainstone_model_e model, int arm_id) 100 { 101 uint32_t sector_len = 256 * 1024; 102 hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 }; 103 PXA2xxState *mpu; 104 DeviceState *mst_irq; 105 DriveInfo *dinfo; 106 int i; 107 int be; 108 MemoryRegion *rom = g_new(MemoryRegion, 1); 109 const char *cpu_model = args->cpu_model; 110 111 if (!cpu_model) 112 cpu_model = "pxa270-c5"; 113 114 /* Setup CPU & memory */ 115 mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, cpu_model); 116 memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM); 117 vmstate_register_ram_global(rom); 118 memory_region_set_readonly(rom, true); 119 memory_region_add_subregion(address_space_mem, 0, rom); 120 121 #ifdef TARGET_WORDS_BIGENDIAN 122 be = 1; 123 #else 124 be = 0; 125 #endif 126 /* There are two 32MiB flash devices on the board */ 127 for (i = 0; i < 2; i ++) { 128 dinfo = drive_get(IF_PFLASH, 0, i); 129 if (!dinfo) { 130 fprintf(stderr, "Two flash images must be given with the " 131 "'pflash' parameter\n"); 132 exit(1); 133 } 134 135 if (!pflash_cfi01_register(mainstone_flash_base[i], NULL, 136 i ? "mainstone.flash1" : "mainstone.flash0", 137 MAINSTONE_FLASH, 138 dinfo->bdrv, sector_len, 139 MAINSTONE_FLASH / sector_len, 4, 0, 0, 0, 0, 140 be)) { 141 fprintf(stderr, "qemu: Error registering flash memory.\n"); 142 exit(1); 143 } 144 } 145 146 mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS, 147 qdev_get_gpio_in(mpu->gpio, 0)); 148 149 /* setup keypad */ 150 printf("map addr %p\n", &map); 151 pxa27x_register_keypad(mpu->kp, map, 0xe0); 152 153 /* MMC/SD host */ 154 pxa2xx_mmci_handlers(mpu->mmc, NULL, qdev_get_gpio_in(mst_irq, MMC_IRQ)); 155 156 pxa2xx_pcmcia_set_irq_cb(mpu->pcmcia[0], 157 qdev_get_gpio_in(mst_irq, S0_IRQ), 158 qdev_get_gpio_in(mst_irq, S0_CD_IRQ)); 159 pxa2xx_pcmcia_set_irq_cb(mpu->pcmcia[1], 160 qdev_get_gpio_in(mst_irq, S1_IRQ), 161 qdev_get_gpio_in(mst_irq, S1_CD_IRQ)); 162 163 smc91c111_init(&nd_table[0], MST_ETH_PHYS, 164 qdev_get_gpio_in(mst_irq, ETHERNET_IRQ)); 165 166 mainstone_binfo.kernel_filename = args->kernel_filename; 167 mainstone_binfo.kernel_cmdline = args->kernel_cmdline; 168 mainstone_binfo.initrd_filename = args->initrd_filename; 169 mainstone_binfo.board_id = arm_id; 170 arm_load_kernel(mpu->cpu, &mainstone_binfo); 171 } 172 173 static void mainstone_init(QEMUMachineInitArgs *args) 174 { 175 mainstone_common_init(get_system_memory(), args, mainstone, 0x196); 176 } 177 178 static QEMUMachine mainstone2_machine = { 179 .name = "mainstone", 180 .desc = "Mainstone II (PXA27x)", 181 .init = mainstone_init, 182 DEFAULT_MACHINE_OPTIONS, 183 }; 184 185 static void mainstone_machine_init(void) 186 { 187 qemu_register_machine(&mainstone2_machine); 188 } 189 190 machine_init(mainstone_machine_init); 191