1 /* 2 * ARM Integrator CP System emulation. 3 * 4 * Copyright (c) 2005-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "cpu.h" 13 #include "hw/sysbus.h" 14 #include "migration/vmstate.h" 15 #include "hw/boards.h" 16 #include "hw/arm/boot.h" 17 #include "hw/misc/arm_integrator_debug.h" 18 #include "hw/net/smc91c111.h" 19 #include "net/net.h" 20 #include "exec/address-spaces.h" 21 #include "sysemu/runstate.h" 22 #include "sysemu/sysemu.h" 23 #include "qemu/log.h" 24 #include "qemu/error-report.h" 25 #include "hw/char/pl011.h" 26 #include "hw/hw.h" 27 #include "hw/irq.h" 28 #include "hw/sd/sd.h" 29 #include "qom/object.h" 30 #include "audio/audio.h" 31 #include "target/arm/cpu-qom.h" 32 33 #define TYPE_INTEGRATOR_CM "integrator_core" 34 OBJECT_DECLARE_SIMPLE_TYPE(IntegratorCMState, INTEGRATOR_CM) 35 36 struct IntegratorCMState { 37 /*< private >*/ 38 SysBusDevice parent_obj; 39 /*< public >*/ 40 41 MemoryRegion iomem; 42 uint32_t memsz; 43 MemoryRegion flash; 44 uint32_t cm_osc; 45 uint32_t cm_ctrl; 46 uint32_t cm_lock; 47 uint32_t cm_auxosc; 48 uint32_t cm_sdram; 49 uint32_t cm_init; 50 uint32_t cm_flags; 51 uint32_t cm_nvflags; 52 uint32_t cm_refcnt_offset; 53 uint32_t int_level; 54 uint32_t irq_enabled; 55 uint32_t fiq_enabled; 56 }; 57 58 static uint8_t integrator_spd[128] = { 59 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1, 60 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 61 }; 62 63 static const VMStateDescription vmstate_integratorcm = { 64 .name = "integratorcm", 65 .version_id = 1, 66 .minimum_version_id = 1, 67 .fields = (const VMStateField[]) { 68 VMSTATE_UINT32(cm_osc, IntegratorCMState), 69 VMSTATE_UINT32(cm_ctrl, IntegratorCMState), 70 VMSTATE_UINT32(cm_lock, IntegratorCMState), 71 VMSTATE_UINT32(cm_auxosc, IntegratorCMState), 72 VMSTATE_UINT32(cm_sdram, IntegratorCMState), 73 VMSTATE_UINT32(cm_init, IntegratorCMState), 74 VMSTATE_UINT32(cm_flags, IntegratorCMState), 75 VMSTATE_UINT32(cm_nvflags, IntegratorCMState), 76 VMSTATE_UINT32(int_level, IntegratorCMState), 77 VMSTATE_UINT32(irq_enabled, IntegratorCMState), 78 VMSTATE_UINT32(fiq_enabled, IntegratorCMState), 79 VMSTATE_END_OF_LIST() 80 } 81 }; 82 83 static uint64_t integratorcm_read(void *opaque, hwaddr offset, 84 unsigned size) 85 { 86 IntegratorCMState *s = opaque; 87 if (offset >= 0x100 && offset < 0x200) { 88 /* CM_SPD */ 89 if (offset >= 0x180) 90 return 0; 91 return integrator_spd[offset >> 2]; 92 } 93 switch (offset >> 2) { 94 case 0: /* CM_ID */ 95 return 0x411a3001; 96 case 1: /* CM_PROC */ 97 return 0; 98 case 2: /* CM_OSC */ 99 return s->cm_osc; 100 case 3: /* CM_CTRL */ 101 return s->cm_ctrl; 102 case 4: /* CM_STAT */ 103 return 0x00100000; 104 case 5: /* CM_LOCK */ 105 if (s->cm_lock == 0xa05f) { 106 return 0x1a05f; 107 } else { 108 return s->cm_lock; 109 } 110 case 6: /* CM_LMBUSCNT */ 111 /* ??? High frequency timer. */ 112 hw_error("integratorcm_read: CM_LMBUSCNT"); 113 case 7: /* CM_AUXOSC */ 114 return s->cm_auxosc; 115 case 8: /* CM_SDRAM */ 116 return s->cm_sdram; 117 case 9: /* CM_INIT */ 118 return s->cm_init; 119 case 10: /* CM_REFCNT */ 120 /* This register, CM_REFCNT, provides a 32-bit count value. 121 * The count increments at the fixed reference clock frequency of 24MHz 122 * and can be used as a real-time counter. 123 */ 124 return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 125 1000) - s->cm_refcnt_offset; 126 case 12: /* CM_FLAGS */ 127 return s->cm_flags; 128 case 14: /* CM_NVFLAGS */ 129 return s->cm_nvflags; 130 case 16: /* CM_IRQ_STAT */ 131 return s->int_level & s->irq_enabled; 132 case 17: /* CM_IRQ_RSTAT */ 133 return s->int_level; 134 case 18: /* CM_IRQ_ENSET */ 135 return s->irq_enabled; 136 case 20: /* CM_SOFT_INTSET */ 137 return s->int_level & 1; 138 case 24: /* CM_FIQ_STAT */ 139 return s->int_level & s->fiq_enabled; 140 case 25: /* CM_FIQ_RSTAT */ 141 return s->int_level; 142 case 26: /* CM_FIQ_ENSET */ 143 return s->fiq_enabled; 144 case 32: /* CM_VOLTAGE_CTL0 */ 145 case 33: /* CM_VOLTAGE_CTL1 */ 146 case 34: /* CM_VOLTAGE_CTL2 */ 147 case 35: /* CM_VOLTAGE_CTL3 */ 148 /* ??? Voltage control unimplemented. */ 149 return 0; 150 default: 151 qemu_log_mask(LOG_UNIMP, 152 "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n", 153 __func__, offset); 154 return 0; 155 } 156 } 157 158 static void integratorcm_do_remap(IntegratorCMState *s) 159 { 160 /* Sync memory region state with CM_CTRL REMAP bit: 161 * bit 0 => flash at address 0; bit 1 => RAM 162 */ 163 memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4)); 164 } 165 166 static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value) 167 { 168 if (value & 8) { 169 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 170 } 171 if ((s->cm_ctrl ^ value) & 1) { 172 /* (value & 1) != 0 means the green "MISC LED" is lit. 173 * We don't have any nice place to display LEDs. printf is a bad 174 * idea because Linux uses the LED as a heartbeat and the output 175 * will swamp anything else on the terminal. 176 */ 177 } 178 /* Note that the RESET bit [3] always reads as zero */ 179 s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5); 180 integratorcm_do_remap(s); 181 } 182 183 static void integratorcm_update(IntegratorCMState *s) 184 { 185 /* ??? The CPU irq/fiq is raised when either the core module or base PIC 186 are active. */ 187 if (s->int_level & (s->irq_enabled | s->fiq_enabled)) 188 hw_error("Core module interrupt\n"); 189 } 190 191 static void integratorcm_write(void *opaque, hwaddr offset, 192 uint64_t value, unsigned size) 193 { 194 IntegratorCMState *s = opaque; 195 switch (offset >> 2) { 196 case 2: /* CM_OSC */ 197 if (s->cm_lock == 0xa05f) 198 s->cm_osc = value; 199 break; 200 case 3: /* CM_CTRL */ 201 integratorcm_set_ctrl(s, value); 202 break; 203 case 5: /* CM_LOCK */ 204 s->cm_lock = value & 0xffff; 205 break; 206 case 7: /* CM_AUXOSC */ 207 if (s->cm_lock == 0xa05f) 208 s->cm_auxosc = value; 209 break; 210 case 8: /* CM_SDRAM */ 211 s->cm_sdram = value; 212 break; 213 case 9: /* CM_INIT */ 214 /* ??? This can change the memory bus frequency. */ 215 s->cm_init = value; 216 break; 217 case 12: /* CM_FLAGSS */ 218 s->cm_flags |= value; 219 break; 220 case 13: /* CM_FLAGSC */ 221 s->cm_flags &= ~value; 222 break; 223 case 14: /* CM_NVFLAGSS */ 224 s->cm_nvflags |= value; 225 break; 226 case 15: /* CM_NVFLAGSS */ 227 s->cm_nvflags &= ~value; 228 break; 229 case 18: /* CM_IRQ_ENSET */ 230 s->irq_enabled |= value; 231 integratorcm_update(s); 232 break; 233 case 19: /* CM_IRQ_ENCLR */ 234 s->irq_enabled &= ~value; 235 integratorcm_update(s); 236 break; 237 case 20: /* CM_SOFT_INTSET */ 238 s->int_level |= (value & 1); 239 integratorcm_update(s); 240 break; 241 case 21: /* CM_SOFT_INTCLR */ 242 s->int_level &= ~(value & 1); 243 integratorcm_update(s); 244 break; 245 case 26: /* CM_FIQ_ENSET */ 246 s->fiq_enabled |= value; 247 integratorcm_update(s); 248 break; 249 case 27: /* CM_FIQ_ENCLR */ 250 s->fiq_enabled &= ~value; 251 integratorcm_update(s); 252 break; 253 case 32: /* CM_VOLTAGE_CTL0 */ 254 case 33: /* CM_VOLTAGE_CTL1 */ 255 case 34: /* CM_VOLTAGE_CTL2 */ 256 case 35: /* CM_VOLTAGE_CTL3 */ 257 /* ??? Voltage control unimplemented. */ 258 break; 259 default: 260 qemu_log_mask(LOG_UNIMP, 261 "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n", 262 __func__, offset); 263 break; 264 } 265 } 266 267 /* Integrator/CM control registers. */ 268 269 static const MemoryRegionOps integratorcm_ops = { 270 .read = integratorcm_read, 271 .write = integratorcm_write, 272 .endianness = DEVICE_NATIVE_ENDIAN, 273 }; 274 275 static void integratorcm_init(Object *obj) 276 { 277 IntegratorCMState *s = INTEGRATOR_CM(obj); 278 279 s->cm_osc = 0x01000048; 280 /* ??? What should the high bits of this value be? */ 281 s->cm_auxosc = 0x0007feff; 282 s->cm_sdram = 0x00011122; 283 memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); 284 s->cm_init = 0x00000112; 285 s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 286 1000); 287 288 /* ??? Save/restore. */ 289 } 290 291 static void integratorcm_realize(DeviceState *d, Error **errp) 292 { 293 IntegratorCMState *s = INTEGRATOR_CM(d); 294 SysBusDevice *dev = SYS_BUS_DEVICE(d); 295 296 if (!memory_region_init_ram(&s->flash, OBJECT(d), "integrator.flash", 297 0x100000, errp)) { 298 return; 299 } 300 301 memory_region_init_io(&s->iomem, OBJECT(d), &integratorcm_ops, s, 302 "integratorcm", 0x00800000); 303 sysbus_init_mmio(dev, &s->iomem); 304 305 integratorcm_do_remap(s); 306 307 if (s->memsz >= 256) { 308 integrator_spd[31] = 64; 309 s->cm_sdram |= 0x10; 310 } else if (s->memsz >= 128) { 311 integrator_spd[31] = 32; 312 s->cm_sdram |= 0x0c; 313 } else if (s->memsz >= 64) { 314 integrator_spd[31] = 16; 315 s->cm_sdram |= 0x08; 316 } else if (s->memsz >= 32) { 317 integrator_spd[31] = 4; 318 s->cm_sdram |= 0x04; 319 } else { 320 integrator_spd[31] = 2; 321 } 322 } 323 324 /* Integrator/CP hardware emulation. */ 325 /* Primary interrupt controller. */ 326 327 #define TYPE_INTEGRATOR_PIC "integrator_pic" 328 OBJECT_DECLARE_SIMPLE_TYPE(icp_pic_state, INTEGRATOR_PIC) 329 330 struct icp_pic_state { 331 /*< private >*/ 332 SysBusDevice parent_obj; 333 /*< public >*/ 334 335 MemoryRegion iomem; 336 uint32_t level; 337 uint32_t irq_enabled; 338 uint32_t fiq_enabled; 339 qemu_irq parent_irq; 340 qemu_irq parent_fiq; 341 }; 342 343 static const VMStateDescription vmstate_icp_pic = { 344 .name = "icp_pic", 345 .version_id = 1, 346 .minimum_version_id = 1, 347 .fields = (const VMStateField[]) { 348 VMSTATE_UINT32(level, icp_pic_state), 349 VMSTATE_UINT32(irq_enabled, icp_pic_state), 350 VMSTATE_UINT32(fiq_enabled, icp_pic_state), 351 VMSTATE_END_OF_LIST() 352 } 353 }; 354 355 static void icp_pic_update(icp_pic_state *s) 356 { 357 uint32_t flags; 358 359 flags = (s->level & s->irq_enabled); 360 qemu_set_irq(s->parent_irq, flags != 0); 361 flags = (s->level & s->fiq_enabled); 362 qemu_set_irq(s->parent_fiq, flags != 0); 363 } 364 365 static void icp_pic_set_irq(void *opaque, int irq, int level) 366 { 367 icp_pic_state *s = (icp_pic_state *)opaque; 368 if (level) 369 s->level |= 1 << irq; 370 else 371 s->level &= ~(1 << irq); 372 icp_pic_update(s); 373 } 374 375 static uint64_t icp_pic_read(void *opaque, hwaddr offset, 376 unsigned size) 377 { 378 icp_pic_state *s = (icp_pic_state *)opaque; 379 380 switch (offset >> 2) { 381 case 0: /* IRQ_STATUS */ 382 return s->level & s->irq_enabled; 383 case 1: /* IRQ_RAWSTAT */ 384 return s->level; 385 case 2: /* IRQ_ENABLESET */ 386 return s->irq_enabled; 387 case 4: /* INT_SOFTSET */ 388 return s->level & 1; 389 case 8: /* FRQ_STATUS */ 390 return s->level & s->fiq_enabled; 391 case 9: /* FRQ_RAWSTAT */ 392 return s->level; 393 case 10: /* FRQ_ENABLESET */ 394 return s->fiq_enabled; 395 case 3: /* IRQ_ENABLECLR */ 396 case 5: /* INT_SOFTCLR */ 397 case 11: /* FRQ_ENABLECLR */ 398 default: 399 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 400 __func__, offset); 401 return 0; 402 } 403 } 404 405 static void icp_pic_write(void *opaque, hwaddr offset, 406 uint64_t value, unsigned size) 407 { 408 icp_pic_state *s = (icp_pic_state *)opaque; 409 410 switch (offset >> 2) { 411 case 2: /* IRQ_ENABLESET */ 412 s->irq_enabled |= value; 413 break; 414 case 3: /* IRQ_ENABLECLR */ 415 s->irq_enabled &= ~value; 416 break; 417 case 4: /* INT_SOFTSET */ 418 if (value & 1) 419 icp_pic_set_irq(s, 0, 1); 420 break; 421 case 5: /* INT_SOFTCLR */ 422 if (value & 1) 423 icp_pic_set_irq(s, 0, 0); 424 break; 425 case 10: /* FRQ_ENABLESET */ 426 s->fiq_enabled |= value; 427 break; 428 case 11: /* FRQ_ENABLECLR */ 429 s->fiq_enabled &= ~value; 430 break; 431 case 0: /* IRQ_STATUS */ 432 case 1: /* IRQ_RAWSTAT */ 433 case 8: /* FRQ_STATUS */ 434 case 9: /* FRQ_RAWSTAT */ 435 default: 436 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 437 __func__, offset); 438 return; 439 } 440 icp_pic_update(s); 441 } 442 443 static const MemoryRegionOps icp_pic_ops = { 444 .read = icp_pic_read, 445 .write = icp_pic_write, 446 .endianness = DEVICE_NATIVE_ENDIAN, 447 }; 448 449 static void icp_pic_init(Object *obj) 450 { 451 DeviceState *dev = DEVICE(obj); 452 icp_pic_state *s = INTEGRATOR_PIC(obj); 453 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 454 455 qdev_init_gpio_in(dev, icp_pic_set_irq, 32); 456 sysbus_init_irq(sbd, &s->parent_irq); 457 sysbus_init_irq(sbd, &s->parent_fiq); 458 memory_region_init_io(&s->iomem, obj, &icp_pic_ops, s, 459 "icp-pic", 0x00800000); 460 sysbus_init_mmio(sbd, &s->iomem); 461 } 462 463 /* CP control registers. */ 464 465 #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs" 466 OBJECT_DECLARE_SIMPLE_TYPE(ICPCtrlRegsState, ICP_CONTROL_REGS) 467 468 struct ICPCtrlRegsState { 469 /*< private >*/ 470 SysBusDevice parent_obj; 471 /*< public >*/ 472 473 MemoryRegion iomem; 474 475 qemu_irq mmc_irq; 476 uint32_t intreg_state; 477 }; 478 479 #define ICP_GPIO_MMC_WPROT "mmc-wprot" 480 #define ICP_GPIO_MMC_CARDIN "mmc-cardin" 481 482 #define ICP_INTREG_WPROT (1 << 0) 483 #define ICP_INTREG_CARDIN (1 << 3) 484 485 static const VMStateDescription vmstate_icp_control = { 486 .name = "icp_control", 487 .version_id = 1, 488 .minimum_version_id = 1, 489 .fields = (const VMStateField[]) { 490 VMSTATE_UINT32(intreg_state, ICPCtrlRegsState), 491 VMSTATE_END_OF_LIST() 492 } 493 }; 494 495 static uint64_t icp_control_read(void *opaque, hwaddr offset, 496 unsigned size) 497 { 498 ICPCtrlRegsState *s = opaque; 499 500 switch (offset >> 2) { 501 case 0: /* CP_IDFIELD */ 502 return 0x41034003; 503 case 1: /* CP_FLASHPROG */ 504 return 0; 505 case 2: /* CP_INTREG */ 506 return s->intreg_state; 507 case 3: /* CP_DECODE */ 508 return 0x11; 509 default: 510 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 511 __func__, offset); 512 return 0; 513 } 514 } 515 516 static void icp_control_write(void *opaque, hwaddr offset, 517 uint64_t value, unsigned size) 518 { 519 ICPCtrlRegsState *s = opaque; 520 521 switch (offset >> 2) { 522 case 2: /* CP_INTREG */ 523 s->intreg_state &= ~(value & ICP_INTREG_CARDIN); 524 qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN)); 525 break; 526 case 1: /* CP_FLASHPROG */ 527 case 3: /* CP_DECODE */ 528 /* Nothing interesting implemented yet. */ 529 break; 530 default: 531 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 532 __func__, offset); 533 } 534 } 535 536 static const MemoryRegionOps icp_control_ops = { 537 .read = icp_control_read, 538 .write = icp_control_write, 539 .endianness = DEVICE_NATIVE_ENDIAN, 540 }; 541 542 static void icp_control_mmc_wprot(void *opaque, int line, int level) 543 { 544 ICPCtrlRegsState *s = opaque; 545 546 s->intreg_state &= ~ICP_INTREG_WPROT; 547 if (level) { 548 s->intreg_state |= ICP_INTREG_WPROT; 549 } 550 } 551 552 static void icp_control_mmc_cardin(void *opaque, int line, int level) 553 { 554 ICPCtrlRegsState *s = opaque; 555 556 /* line is released by writing to CP_INTREG */ 557 if (level) { 558 s->intreg_state |= ICP_INTREG_CARDIN; 559 qemu_set_irq(s->mmc_irq, 1); 560 } 561 } 562 563 static void icp_control_init(Object *obj) 564 { 565 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 566 ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj); 567 DeviceState *dev = DEVICE(obj); 568 569 memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s, 570 "icp_ctrl_regs", 0x00800000); 571 sysbus_init_mmio(sbd, &s->iomem); 572 573 qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1); 574 qdev_init_gpio_in_named(dev, icp_control_mmc_cardin, 575 ICP_GPIO_MMC_CARDIN, 1); 576 sysbus_init_irq(sbd, &s->mmc_irq); 577 } 578 579 580 /* Board init. */ 581 582 static struct arm_boot_info integrator_binfo = { 583 .loader_start = 0x0, 584 .board_id = 0x113, 585 }; 586 587 static void integratorcp_init(MachineState *machine) 588 { 589 ram_addr_t ram_size = machine->ram_size; 590 Object *cpuobj; 591 ARMCPU *cpu; 592 MemoryRegion *address_space_mem = get_system_memory(); 593 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 594 qemu_irq pic[32]; 595 DeviceState *dev, *sic, *icp; 596 DriveInfo *dinfo; 597 int i; 598 599 cpuobj = object_new(machine->cpu_type); 600 601 /* By default ARM1176 CPUs have EL3 enabled. This board does not 602 * currently support EL3 so the CPU EL3 property is disabled before 603 * realization. 604 */ 605 if (object_property_find(cpuobj, "has_el3")) { 606 object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); 607 } 608 609 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 610 611 cpu = ARM_CPU(cpuobj); 612 613 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ 614 /* ??? RAM should repeat to fill physical memory space. */ 615 /* SDRAM at address zero*/ 616 memory_region_add_subregion(address_space_mem, 0, machine->ram); 617 /* And again at address 0x80000000 */ 618 memory_region_init_alias(ram_alias, NULL, "ram.alias", machine->ram, 619 0, ram_size); 620 memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias); 621 622 dev = qdev_new(TYPE_INTEGRATOR_CM); 623 qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); 624 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 625 sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); 626 627 dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000, 628 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), 629 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), 630 NULL); 631 for (i = 0; i < 32; i++) { 632 pic[i] = qdev_get_gpio_in(dev, i); 633 } 634 sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]); 635 sysbus_create_varargs("integrator_pit", 0x13000000, 636 pic[5], pic[6], pic[7], NULL); 637 sysbus_create_simple("pl031", 0x15000000, pic[8]); 638 pl011_create(0x16000000, pic[1], serial_hd(0)); 639 pl011_create(0x17000000, pic[2], serial_hd(1)); 640 icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000, 641 qdev_get_gpio_in(sic, 3)); 642 sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]); 643 sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]); 644 sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0); 645 646 dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL); 647 qdev_connect_gpio_out_named(dev, "card-read-only", 0, 648 qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0)); 649 qdev_connect_gpio_out_named(dev, "card-inserted", 0, 650 qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0)); 651 dinfo = drive_get(IF_SD, 0, 0); 652 if (dinfo) { 653 DeviceState *card; 654 655 card = qdev_new(TYPE_SD_CARD); 656 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 657 &error_fatal); 658 qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"), 659 &error_fatal); 660 } 661 662 dev = qdev_new("pl041"); 663 if (machine->audiodev) { 664 qdev_prop_set_string(dev, "audiodev", machine->audiodev); 665 } 666 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 667 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x1d000000); 668 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[25]); 669 670 if (nd_table[0].used) 671 smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); 672 673 sysbus_create_simple("pl110", 0xc0000000, pic[22]); 674 675 integrator_binfo.ram_size = ram_size; 676 arm_load_kernel(cpu, machine, &integrator_binfo); 677 } 678 679 static void integratorcp_machine_init(MachineClass *mc) 680 { 681 mc->desc = "ARM Integrator/CP (ARM926EJ-S)"; 682 mc->init = integratorcp_init; 683 mc->ignore_memory_transaction_failures = true; 684 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 685 mc->default_ram_id = "integrator.ram"; 686 687 machine_add_audiodev_property(mc); 688 } 689 690 DEFINE_MACHINE("integratorcp", integratorcp_machine_init) 691 692 static Property core_properties[] = { 693 DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0), 694 DEFINE_PROP_END_OF_LIST(), 695 }; 696 697 static void core_class_init(ObjectClass *klass, void *data) 698 { 699 DeviceClass *dc = DEVICE_CLASS(klass); 700 701 device_class_set_props(dc, core_properties); 702 dc->realize = integratorcm_realize; 703 dc->vmsd = &vmstate_integratorcm; 704 } 705 706 static void icp_pic_class_init(ObjectClass *klass, void *data) 707 { 708 DeviceClass *dc = DEVICE_CLASS(klass); 709 710 dc->vmsd = &vmstate_icp_pic; 711 } 712 713 static void icp_control_class_init(ObjectClass *klass, void *data) 714 { 715 DeviceClass *dc = DEVICE_CLASS(klass); 716 717 dc->vmsd = &vmstate_icp_control; 718 } 719 720 static const TypeInfo core_info = { 721 .name = TYPE_INTEGRATOR_CM, 722 .parent = TYPE_SYS_BUS_DEVICE, 723 .instance_size = sizeof(IntegratorCMState), 724 .instance_init = integratorcm_init, 725 .class_init = core_class_init, 726 }; 727 728 static const TypeInfo icp_pic_info = { 729 .name = TYPE_INTEGRATOR_PIC, 730 .parent = TYPE_SYS_BUS_DEVICE, 731 .instance_size = sizeof(icp_pic_state), 732 .instance_init = icp_pic_init, 733 .class_init = icp_pic_class_init, 734 }; 735 736 static const TypeInfo icp_ctrl_regs_info = { 737 .name = TYPE_ICP_CONTROL_REGS, 738 .parent = TYPE_SYS_BUS_DEVICE, 739 .instance_size = sizeof(ICPCtrlRegsState), 740 .instance_init = icp_control_init, 741 .class_init = icp_control_class_init, 742 }; 743 744 static void integratorcp_register_types(void) 745 { 746 type_register_static(&icp_pic_info); 747 type_register_static(&core_info); 748 type_register_static(&icp_ctrl_regs_info); 749 } 750 751 type_init(integratorcp_register_types) 752