1 /* 2 * ARM Integrator CP System emulation. 3 * 4 * Copyright (c) 2005-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL 8 */ 9 10 #include "hw/sysbus.h" 11 #include "hw/devices.h" 12 #include "hw/boards.h" 13 #include "hw/arm/arm.h" 14 #include "hw/misc/arm_integrator_debug.h" 15 #include "net/net.h" 16 #include "exec/address-spaces.h" 17 #include "sysemu/sysemu.h" 18 19 #define TYPE_INTEGRATOR_CM "integrator_core" 20 #define INTEGRATOR_CM(obj) \ 21 OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM) 22 23 typedef struct IntegratorCMState { 24 /*< private >*/ 25 SysBusDevice parent_obj; 26 /*< public >*/ 27 28 MemoryRegion iomem; 29 uint32_t memsz; 30 MemoryRegion flash; 31 uint32_t cm_osc; 32 uint32_t cm_ctrl; 33 uint32_t cm_lock; 34 uint32_t cm_auxosc; 35 uint32_t cm_sdram; 36 uint32_t cm_init; 37 uint32_t cm_flags; 38 uint32_t cm_nvflags; 39 uint32_t cm_refcnt_offset; 40 uint32_t int_level; 41 uint32_t irq_enabled; 42 uint32_t fiq_enabled; 43 } IntegratorCMState; 44 45 static uint8_t integrator_spd[128] = { 46 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1, 47 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 48 }; 49 50 static uint64_t integratorcm_read(void *opaque, hwaddr offset, 51 unsigned size) 52 { 53 IntegratorCMState *s = opaque; 54 if (offset >= 0x100 && offset < 0x200) { 55 /* CM_SPD */ 56 if (offset >= 0x180) 57 return 0; 58 return integrator_spd[offset >> 2]; 59 } 60 switch (offset >> 2) { 61 case 0: /* CM_ID */ 62 return 0x411a3001; 63 case 1: /* CM_PROC */ 64 return 0; 65 case 2: /* CM_OSC */ 66 return s->cm_osc; 67 case 3: /* CM_CTRL */ 68 return s->cm_ctrl; 69 case 4: /* CM_STAT */ 70 return 0x00100000; 71 case 5: /* CM_LOCK */ 72 if (s->cm_lock == 0xa05f) { 73 return 0x1a05f; 74 } else { 75 return s->cm_lock; 76 } 77 case 6: /* CM_LMBUSCNT */ 78 /* ??? High frequency timer. */ 79 hw_error("integratorcm_read: CM_LMBUSCNT"); 80 case 7: /* CM_AUXOSC */ 81 return s->cm_auxosc; 82 case 8: /* CM_SDRAM */ 83 return s->cm_sdram; 84 case 9: /* CM_INIT */ 85 return s->cm_init; 86 case 10: /* CM_REFCNT */ 87 /* This register, CM_REFCNT, provides a 32-bit count value. 88 * The count increments at the fixed reference clock frequency of 24MHz 89 * and can be used as a real-time counter. 90 */ 91 return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 92 1000) - s->cm_refcnt_offset; 93 case 12: /* CM_FLAGS */ 94 return s->cm_flags; 95 case 14: /* CM_NVFLAGS */ 96 return s->cm_nvflags; 97 case 16: /* CM_IRQ_STAT */ 98 return s->int_level & s->irq_enabled; 99 case 17: /* CM_IRQ_RSTAT */ 100 return s->int_level; 101 case 18: /* CM_IRQ_ENSET */ 102 return s->irq_enabled; 103 case 20: /* CM_SOFT_INTSET */ 104 return s->int_level & 1; 105 case 24: /* CM_FIQ_STAT */ 106 return s->int_level & s->fiq_enabled; 107 case 25: /* CM_FIQ_RSTAT */ 108 return s->int_level; 109 case 26: /* CM_FIQ_ENSET */ 110 return s->fiq_enabled; 111 case 32: /* CM_VOLTAGE_CTL0 */ 112 case 33: /* CM_VOLTAGE_CTL1 */ 113 case 34: /* CM_VOLTAGE_CTL2 */ 114 case 35: /* CM_VOLTAGE_CTL3 */ 115 /* ??? Voltage control unimplemented. */ 116 return 0; 117 default: 118 hw_error("integratorcm_read: Unimplemented offset 0x%x\n", 119 (int)offset); 120 return 0; 121 } 122 } 123 124 static void integratorcm_do_remap(IntegratorCMState *s) 125 { 126 /* Sync memory region state with CM_CTRL REMAP bit: 127 * bit 0 => flash at address 0; bit 1 => RAM 128 */ 129 memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4)); 130 } 131 132 static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value) 133 { 134 if (value & 8) { 135 qemu_system_reset_request(); 136 } 137 if ((s->cm_ctrl ^ value) & 1) { 138 /* (value & 1) != 0 means the green "MISC LED" is lit. 139 * We don't have any nice place to display LEDs. printf is a bad 140 * idea because Linux uses the LED as a heartbeat and the output 141 * will swamp anything else on the terminal. 142 */ 143 } 144 /* Note that the RESET bit [3] always reads as zero */ 145 s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5); 146 integratorcm_do_remap(s); 147 } 148 149 static void integratorcm_update(IntegratorCMState *s) 150 { 151 /* ??? The CPU irq/fiq is raised when either the core module or base PIC 152 are active. */ 153 if (s->int_level & (s->irq_enabled | s->fiq_enabled)) 154 hw_error("Core module interrupt\n"); 155 } 156 157 static void integratorcm_write(void *opaque, hwaddr offset, 158 uint64_t value, unsigned size) 159 { 160 IntegratorCMState *s = opaque; 161 switch (offset >> 2) { 162 case 2: /* CM_OSC */ 163 if (s->cm_lock == 0xa05f) 164 s->cm_osc = value; 165 break; 166 case 3: /* CM_CTRL */ 167 integratorcm_set_ctrl(s, value); 168 break; 169 case 5: /* CM_LOCK */ 170 s->cm_lock = value & 0xffff; 171 break; 172 case 7: /* CM_AUXOSC */ 173 if (s->cm_lock == 0xa05f) 174 s->cm_auxosc = value; 175 break; 176 case 8: /* CM_SDRAM */ 177 s->cm_sdram = value; 178 break; 179 case 9: /* CM_INIT */ 180 /* ??? This can change the memory bus frequency. */ 181 s->cm_init = value; 182 break; 183 case 12: /* CM_FLAGSS */ 184 s->cm_flags |= value; 185 break; 186 case 13: /* CM_FLAGSC */ 187 s->cm_flags &= ~value; 188 break; 189 case 14: /* CM_NVFLAGSS */ 190 s->cm_nvflags |= value; 191 break; 192 case 15: /* CM_NVFLAGSS */ 193 s->cm_nvflags &= ~value; 194 break; 195 case 18: /* CM_IRQ_ENSET */ 196 s->irq_enabled |= value; 197 integratorcm_update(s); 198 break; 199 case 19: /* CM_IRQ_ENCLR */ 200 s->irq_enabled &= ~value; 201 integratorcm_update(s); 202 break; 203 case 20: /* CM_SOFT_INTSET */ 204 s->int_level |= (value & 1); 205 integratorcm_update(s); 206 break; 207 case 21: /* CM_SOFT_INTCLR */ 208 s->int_level &= ~(value & 1); 209 integratorcm_update(s); 210 break; 211 case 26: /* CM_FIQ_ENSET */ 212 s->fiq_enabled |= value; 213 integratorcm_update(s); 214 break; 215 case 27: /* CM_FIQ_ENCLR */ 216 s->fiq_enabled &= ~value; 217 integratorcm_update(s); 218 break; 219 case 32: /* CM_VOLTAGE_CTL0 */ 220 case 33: /* CM_VOLTAGE_CTL1 */ 221 case 34: /* CM_VOLTAGE_CTL2 */ 222 case 35: /* CM_VOLTAGE_CTL3 */ 223 /* ??? Voltage control unimplemented. */ 224 break; 225 default: 226 hw_error("integratorcm_write: Unimplemented offset 0x%x\n", 227 (int)offset); 228 break; 229 } 230 } 231 232 /* Integrator/CM control registers. */ 233 234 static const MemoryRegionOps integratorcm_ops = { 235 .read = integratorcm_read, 236 .write = integratorcm_write, 237 .endianness = DEVICE_NATIVE_ENDIAN, 238 }; 239 240 static int integratorcm_init(SysBusDevice *dev) 241 { 242 IntegratorCMState *s = INTEGRATOR_CM(dev); 243 244 s->cm_osc = 0x01000048; 245 /* ??? What should the high bits of this value be? */ 246 s->cm_auxosc = 0x0007feff; 247 s->cm_sdram = 0x00011122; 248 if (s->memsz >= 256) { 249 integrator_spd[31] = 64; 250 s->cm_sdram |= 0x10; 251 } else if (s->memsz >= 128) { 252 integrator_spd[31] = 32; 253 s->cm_sdram |= 0x0c; 254 } else if (s->memsz >= 64) { 255 integrator_spd[31] = 16; 256 s->cm_sdram |= 0x08; 257 } else if (s->memsz >= 32) { 258 integrator_spd[31] = 4; 259 s->cm_sdram |= 0x04; 260 } else { 261 integrator_spd[31] = 2; 262 } 263 memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); 264 s->cm_init = 0x00000112; 265 s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 266 1000); 267 memory_region_init_ram(&s->flash, OBJECT(s), "integrator.flash", 0x100000); 268 vmstate_register_ram_global(&s->flash); 269 270 memory_region_init_io(&s->iomem, OBJECT(s), &integratorcm_ops, s, 271 "integratorcm", 0x00800000); 272 sysbus_init_mmio(dev, &s->iomem); 273 274 integratorcm_do_remap(s); 275 /* ??? Save/restore. */ 276 return 0; 277 } 278 279 /* Integrator/CP hardware emulation. */ 280 /* Primary interrupt controller. */ 281 282 #define TYPE_INTEGRATOR_PIC "integrator_pic" 283 #define INTEGRATOR_PIC(obj) \ 284 OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC) 285 286 typedef struct icp_pic_state { 287 /*< private >*/ 288 SysBusDevice parent_obj; 289 /*< public >*/ 290 291 MemoryRegion iomem; 292 uint32_t level; 293 uint32_t irq_enabled; 294 uint32_t fiq_enabled; 295 qemu_irq parent_irq; 296 qemu_irq parent_fiq; 297 } icp_pic_state; 298 299 static void icp_pic_update(icp_pic_state *s) 300 { 301 uint32_t flags; 302 303 flags = (s->level & s->irq_enabled); 304 qemu_set_irq(s->parent_irq, flags != 0); 305 flags = (s->level & s->fiq_enabled); 306 qemu_set_irq(s->parent_fiq, flags != 0); 307 } 308 309 static void icp_pic_set_irq(void *opaque, int irq, int level) 310 { 311 icp_pic_state *s = (icp_pic_state *)opaque; 312 if (level) 313 s->level |= 1 << irq; 314 else 315 s->level &= ~(1 << irq); 316 icp_pic_update(s); 317 } 318 319 static uint64_t icp_pic_read(void *opaque, hwaddr offset, 320 unsigned size) 321 { 322 icp_pic_state *s = (icp_pic_state *)opaque; 323 324 switch (offset >> 2) { 325 case 0: /* IRQ_STATUS */ 326 return s->level & s->irq_enabled; 327 case 1: /* IRQ_RAWSTAT */ 328 return s->level; 329 case 2: /* IRQ_ENABLESET */ 330 return s->irq_enabled; 331 case 4: /* INT_SOFTSET */ 332 return s->level & 1; 333 case 8: /* FRQ_STATUS */ 334 return s->level & s->fiq_enabled; 335 case 9: /* FRQ_RAWSTAT */ 336 return s->level; 337 case 10: /* FRQ_ENABLESET */ 338 return s->fiq_enabled; 339 case 3: /* IRQ_ENABLECLR */ 340 case 5: /* INT_SOFTCLR */ 341 case 11: /* FRQ_ENABLECLR */ 342 default: 343 printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset); 344 return 0; 345 } 346 } 347 348 static void icp_pic_write(void *opaque, hwaddr offset, 349 uint64_t value, unsigned size) 350 { 351 icp_pic_state *s = (icp_pic_state *)opaque; 352 353 switch (offset >> 2) { 354 case 2: /* IRQ_ENABLESET */ 355 s->irq_enabled |= value; 356 break; 357 case 3: /* IRQ_ENABLECLR */ 358 s->irq_enabled &= ~value; 359 break; 360 case 4: /* INT_SOFTSET */ 361 if (value & 1) 362 icp_pic_set_irq(s, 0, 1); 363 break; 364 case 5: /* INT_SOFTCLR */ 365 if (value & 1) 366 icp_pic_set_irq(s, 0, 0); 367 break; 368 case 10: /* FRQ_ENABLESET */ 369 s->fiq_enabled |= value; 370 break; 371 case 11: /* FRQ_ENABLECLR */ 372 s->fiq_enabled &= ~value; 373 break; 374 case 0: /* IRQ_STATUS */ 375 case 1: /* IRQ_RAWSTAT */ 376 case 8: /* FRQ_STATUS */ 377 case 9: /* FRQ_RAWSTAT */ 378 default: 379 printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset); 380 return; 381 } 382 icp_pic_update(s); 383 } 384 385 static const MemoryRegionOps icp_pic_ops = { 386 .read = icp_pic_read, 387 .write = icp_pic_write, 388 .endianness = DEVICE_NATIVE_ENDIAN, 389 }; 390 391 static int icp_pic_init(SysBusDevice *sbd) 392 { 393 DeviceState *dev = DEVICE(sbd); 394 icp_pic_state *s = INTEGRATOR_PIC(dev); 395 396 qdev_init_gpio_in(dev, icp_pic_set_irq, 32); 397 sysbus_init_irq(sbd, &s->parent_irq); 398 sysbus_init_irq(sbd, &s->parent_fiq); 399 memory_region_init_io(&s->iomem, OBJECT(s), &icp_pic_ops, s, 400 "icp-pic", 0x00800000); 401 sysbus_init_mmio(sbd, &s->iomem); 402 return 0; 403 } 404 405 /* CP control registers. */ 406 407 static uint64_t icp_control_read(void *opaque, hwaddr offset, 408 unsigned size) 409 { 410 switch (offset >> 2) { 411 case 0: /* CP_IDFIELD */ 412 return 0x41034003; 413 case 1: /* CP_FLASHPROG */ 414 return 0; 415 case 2: /* CP_INTREG */ 416 return 0; 417 case 3: /* CP_DECODE */ 418 return 0x11; 419 default: 420 hw_error("icp_control_read: Bad offset %x\n", (int)offset); 421 return 0; 422 } 423 } 424 425 static void icp_control_write(void *opaque, hwaddr offset, 426 uint64_t value, unsigned size) 427 { 428 switch (offset >> 2) { 429 case 1: /* CP_FLASHPROG */ 430 case 2: /* CP_INTREG */ 431 case 3: /* CP_DECODE */ 432 /* Nothing interesting implemented yet. */ 433 break; 434 default: 435 hw_error("icp_control_write: Bad offset %x\n", (int)offset); 436 } 437 } 438 439 static const MemoryRegionOps icp_control_ops = { 440 .read = icp_control_read, 441 .write = icp_control_write, 442 .endianness = DEVICE_NATIVE_ENDIAN, 443 }; 444 445 static void icp_control_init(hwaddr base) 446 { 447 MemoryRegion *io; 448 449 io = (MemoryRegion *)g_malloc0(sizeof(MemoryRegion)); 450 memory_region_init_io(io, NULL, &icp_control_ops, NULL, 451 "control", 0x00800000); 452 memory_region_add_subregion(get_system_memory(), base, io); 453 /* ??? Save/restore. */ 454 } 455 456 457 /* Board init. */ 458 459 static struct arm_boot_info integrator_binfo = { 460 .loader_start = 0x0, 461 .board_id = 0x113, 462 }; 463 464 static void integratorcp_init(QEMUMachineInitArgs *args) 465 { 466 ram_addr_t ram_size = args->ram_size; 467 const char *cpu_model = args->cpu_model; 468 const char *kernel_filename = args->kernel_filename; 469 const char *kernel_cmdline = args->kernel_cmdline; 470 const char *initrd_filename = args->initrd_filename; 471 ARMCPU *cpu; 472 MemoryRegion *address_space_mem = get_system_memory(); 473 MemoryRegion *ram = g_new(MemoryRegion, 1); 474 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 475 qemu_irq pic[32]; 476 DeviceState *dev; 477 int i; 478 479 if (!cpu_model) { 480 cpu_model = "arm926"; 481 } 482 cpu = cpu_arm_init(cpu_model); 483 if (!cpu) { 484 fprintf(stderr, "Unable to find CPU definition\n"); 485 exit(1); 486 } 487 488 memory_region_init_ram(ram, NULL, "integrator.ram", ram_size); 489 vmstate_register_ram_global(ram); 490 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ 491 /* ??? RAM should repeat to fill physical memory space. */ 492 /* SDRAM at address zero*/ 493 memory_region_add_subregion(address_space_mem, 0, ram); 494 /* And again at address 0x80000000 */ 495 memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size); 496 memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias); 497 498 dev = qdev_create(NULL, TYPE_INTEGRATOR_CM); 499 qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); 500 qdev_init_nofail(dev); 501 sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); 502 503 dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000, 504 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), 505 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), 506 NULL); 507 for (i = 0; i < 32; i++) { 508 pic[i] = qdev_get_gpio_in(dev, i); 509 } 510 sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]); 511 sysbus_create_varargs("integrator_pit", 0x13000000, 512 pic[5], pic[6], pic[7], NULL); 513 sysbus_create_simple("pl031", 0x15000000, pic[8]); 514 sysbus_create_simple("pl011", 0x16000000, pic[1]); 515 sysbus_create_simple("pl011", 0x17000000, pic[2]); 516 icp_control_init(0xcb000000); 517 sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]); 518 sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]); 519 sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0); 520 sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL); 521 if (nd_table[0].used) 522 smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); 523 524 sysbus_create_simple("pl110", 0xc0000000, pic[22]); 525 526 integrator_binfo.ram_size = ram_size; 527 integrator_binfo.kernel_filename = kernel_filename; 528 integrator_binfo.kernel_cmdline = kernel_cmdline; 529 integrator_binfo.initrd_filename = initrd_filename; 530 arm_load_kernel(cpu, &integrator_binfo); 531 } 532 533 static QEMUMachine integratorcp_machine = { 534 .name = "integratorcp", 535 .desc = "ARM Integrator/CP (ARM926EJ-S)", 536 .init = integratorcp_init, 537 .is_default = 1, 538 }; 539 540 static void integratorcp_machine_init(void) 541 { 542 qemu_register_machine(&integratorcp_machine); 543 } 544 545 machine_init(integratorcp_machine_init); 546 547 static Property core_properties[] = { 548 DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0), 549 DEFINE_PROP_END_OF_LIST(), 550 }; 551 552 static void core_class_init(ObjectClass *klass, void *data) 553 { 554 DeviceClass *dc = DEVICE_CLASS(klass); 555 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 556 557 k->init = integratorcm_init; 558 dc->props = core_properties; 559 } 560 561 static const TypeInfo core_info = { 562 .name = TYPE_INTEGRATOR_CM, 563 .parent = TYPE_SYS_BUS_DEVICE, 564 .instance_size = sizeof(IntegratorCMState), 565 .class_init = core_class_init, 566 }; 567 568 static void icp_pic_class_init(ObjectClass *klass, void *data) 569 { 570 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 571 572 sdc->init = icp_pic_init; 573 } 574 575 static const TypeInfo icp_pic_info = { 576 .name = TYPE_INTEGRATOR_PIC, 577 .parent = TYPE_SYS_BUS_DEVICE, 578 .instance_size = sizeof(icp_pic_state), 579 .class_init = icp_pic_class_init, 580 }; 581 582 static void integratorcp_register_types(void) 583 { 584 type_register_static(&icp_pic_info); 585 type_register_static(&core_info); 586 } 587 588 type_init(integratorcp_register_types) 589