1 /* 2 * ARM Integrator CP System emulation. 3 * 4 * Copyright (c) 2005-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "qemu-common.h" 13 #include "cpu.h" 14 #include "hw/sysbus.h" 15 #include "hw/devices.h" 16 #include "hw/boards.h" 17 #include "hw/arm/arm.h" 18 #include "hw/misc/arm_integrator_debug.h" 19 #include "net/net.h" 20 #include "exec/address-spaces.h" 21 #include "sysemu/sysemu.h" 22 #include "qemu/error-report.h" 23 #include "hw/char/pl011.h" 24 25 #define TYPE_INTEGRATOR_CM "integrator_core" 26 #define INTEGRATOR_CM(obj) \ 27 OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM) 28 29 typedef struct IntegratorCMState { 30 /*< private >*/ 31 SysBusDevice parent_obj; 32 /*< public >*/ 33 34 MemoryRegion iomem; 35 uint32_t memsz; 36 MemoryRegion flash; 37 uint32_t cm_osc; 38 uint32_t cm_ctrl; 39 uint32_t cm_lock; 40 uint32_t cm_auxosc; 41 uint32_t cm_sdram; 42 uint32_t cm_init; 43 uint32_t cm_flags; 44 uint32_t cm_nvflags; 45 uint32_t cm_refcnt_offset; 46 uint32_t int_level; 47 uint32_t irq_enabled; 48 uint32_t fiq_enabled; 49 } IntegratorCMState; 50 51 static uint8_t integrator_spd[128] = { 52 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1, 53 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 54 }; 55 56 static const VMStateDescription vmstate_integratorcm = { 57 .name = "integratorcm", 58 .version_id = 1, 59 .minimum_version_id = 1, 60 .fields = (VMStateField[]) { 61 VMSTATE_UINT32(cm_osc, IntegratorCMState), 62 VMSTATE_UINT32(cm_ctrl, IntegratorCMState), 63 VMSTATE_UINT32(cm_lock, IntegratorCMState), 64 VMSTATE_UINT32(cm_auxosc, IntegratorCMState), 65 VMSTATE_UINT32(cm_sdram, IntegratorCMState), 66 VMSTATE_UINT32(cm_init, IntegratorCMState), 67 VMSTATE_UINT32(cm_flags, IntegratorCMState), 68 VMSTATE_UINT32(cm_nvflags, IntegratorCMState), 69 VMSTATE_UINT32(int_level, IntegratorCMState), 70 VMSTATE_UINT32(irq_enabled, IntegratorCMState), 71 VMSTATE_UINT32(fiq_enabled, IntegratorCMState), 72 VMSTATE_END_OF_LIST() 73 } 74 }; 75 76 static uint64_t integratorcm_read(void *opaque, hwaddr offset, 77 unsigned size) 78 { 79 IntegratorCMState *s = opaque; 80 if (offset >= 0x100 && offset < 0x200) { 81 /* CM_SPD */ 82 if (offset >= 0x180) 83 return 0; 84 return integrator_spd[offset >> 2]; 85 } 86 switch (offset >> 2) { 87 case 0: /* CM_ID */ 88 return 0x411a3001; 89 case 1: /* CM_PROC */ 90 return 0; 91 case 2: /* CM_OSC */ 92 return s->cm_osc; 93 case 3: /* CM_CTRL */ 94 return s->cm_ctrl; 95 case 4: /* CM_STAT */ 96 return 0x00100000; 97 case 5: /* CM_LOCK */ 98 if (s->cm_lock == 0xa05f) { 99 return 0x1a05f; 100 } else { 101 return s->cm_lock; 102 } 103 case 6: /* CM_LMBUSCNT */ 104 /* ??? High frequency timer. */ 105 hw_error("integratorcm_read: CM_LMBUSCNT"); 106 case 7: /* CM_AUXOSC */ 107 return s->cm_auxosc; 108 case 8: /* CM_SDRAM */ 109 return s->cm_sdram; 110 case 9: /* CM_INIT */ 111 return s->cm_init; 112 case 10: /* CM_REFCNT */ 113 /* This register, CM_REFCNT, provides a 32-bit count value. 114 * The count increments at the fixed reference clock frequency of 24MHz 115 * and can be used as a real-time counter. 116 */ 117 return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 118 1000) - s->cm_refcnt_offset; 119 case 12: /* CM_FLAGS */ 120 return s->cm_flags; 121 case 14: /* CM_NVFLAGS */ 122 return s->cm_nvflags; 123 case 16: /* CM_IRQ_STAT */ 124 return s->int_level & s->irq_enabled; 125 case 17: /* CM_IRQ_RSTAT */ 126 return s->int_level; 127 case 18: /* CM_IRQ_ENSET */ 128 return s->irq_enabled; 129 case 20: /* CM_SOFT_INTSET */ 130 return s->int_level & 1; 131 case 24: /* CM_FIQ_STAT */ 132 return s->int_level & s->fiq_enabled; 133 case 25: /* CM_FIQ_RSTAT */ 134 return s->int_level; 135 case 26: /* CM_FIQ_ENSET */ 136 return s->fiq_enabled; 137 case 32: /* CM_VOLTAGE_CTL0 */ 138 case 33: /* CM_VOLTAGE_CTL1 */ 139 case 34: /* CM_VOLTAGE_CTL2 */ 140 case 35: /* CM_VOLTAGE_CTL3 */ 141 /* ??? Voltage control unimplemented. */ 142 return 0; 143 default: 144 hw_error("integratorcm_read: Unimplemented offset 0x%x\n", 145 (int)offset); 146 return 0; 147 } 148 } 149 150 static void integratorcm_do_remap(IntegratorCMState *s) 151 { 152 /* Sync memory region state with CM_CTRL REMAP bit: 153 * bit 0 => flash at address 0; bit 1 => RAM 154 */ 155 memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4)); 156 } 157 158 static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value) 159 { 160 if (value & 8) { 161 qemu_system_reset_request(); 162 } 163 if ((s->cm_ctrl ^ value) & 1) { 164 /* (value & 1) != 0 means the green "MISC LED" is lit. 165 * We don't have any nice place to display LEDs. printf is a bad 166 * idea because Linux uses the LED as a heartbeat and the output 167 * will swamp anything else on the terminal. 168 */ 169 } 170 /* Note that the RESET bit [3] always reads as zero */ 171 s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5); 172 integratorcm_do_remap(s); 173 } 174 175 static void integratorcm_update(IntegratorCMState *s) 176 { 177 /* ??? The CPU irq/fiq is raised when either the core module or base PIC 178 are active. */ 179 if (s->int_level & (s->irq_enabled | s->fiq_enabled)) 180 hw_error("Core module interrupt\n"); 181 } 182 183 static void integratorcm_write(void *opaque, hwaddr offset, 184 uint64_t value, unsigned size) 185 { 186 IntegratorCMState *s = opaque; 187 switch (offset >> 2) { 188 case 2: /* CM_OSC */ 189 if (s->cm_lock == 0xa05f) 190 s->cm_osc = value; 191 break; 192 case 3: /* CM_CTRL */ 193 integratorcm_set_ctrl(s, value); 194 break; 195 case 5: /* CM_LOCK */ 196 s->cm_lock = value & 0xffff; 197 break; 198 case 7: /* CM_AUXOSC */ 199 if (s->cm_lock == 0xa05f) 200 s->cm_auxosc = value; 201 break; 202 case 8: /* CM_SDRAM */ 203 s->cm_sdram = value; 204 break; 205 case 9: /* CM_INIT */ 206 /* ??? This can change the memory bus frequency. */ 207 s->cm_init = value; 208 break; 209 case 12: /* CM_FLAGSS */ 210 s->cm_flags |= value; 211 break; 212 case 13: /* CM_FLAGSC */ 213 s->cm_flags &= ~value; 214 break; 215 case 14: /* CM_NVFLAGSS */ 216 s->cm_nvflags |= value; 217 break; 218 case 15: /* CM_NVFLAGSS */ 219 s->cm_nvflags &= ~value; 220 break; 221 case 18: /* CM_IRQ_ENSET */ 222 s->irq_enabled |= value; 223 integratorcm_update(s); 224 break; 225 case 19: /* CM_IRQ_ENCLR */ 226 s->irq_enabled &= ~value; 227 integratorcm_update(s); 228 break; 229 case 20: /* CM_SOFT_INTSET */ 230 s->int_level |= (value & 1); 231 integratorcm_update(s); 232 break; 233 case 21: /* CM_SOFT_INTCLR */ 234 s->int_level &= ~(value & 1); 235 integratorcm_update(s); 236 break; 237 case 26: /* CM_FIQ_ENSET */ 238 s->fiq_enabled |= value; 239 integratorcm_update(s); 240 break; 241 case 27: /* CM_FIQ_ENCLR */ 242 s->fiq_enabled &= ~value; 243 integratorcm_update(s); 244 break; 245 case 32: /* CM_VOLTAGE_CTL0 */ 246 case 33: /* CM_VOLTAGE_CTL1 */ 247 case 34: /* CM_VOLTAGE_CTL2 */ 248 case 35: /* CM_VOLTAGE_CTL3 */ 249 /* ??? Voltage control unimplemented. */ 250 break; 251 default: 252 hw_error("integratorcm_write: Unimplemented offset 0x%x\n", 253 (int)offset); 254 break; 255 } 256 } 257 258 /* Integrator/CM control registers. */ 259 260 static const MemoryRegionOps integratorcm_ops = { 261 .read = integratorcm_read, 262 .write = integratorcm_write, 263 .endianness = DEVICE_NATIVE_ENDIAN, 264 }; 265 266 static void integratorcm_init(Object *obj) 267 { 268 IntegratorCMState *s = INTEGRATOR_CM(obj); 269 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 270 271 s->cm_osc = 0x01000048; 272 /* ??? What should the high bits of this value be? */ 273 s->cm_auxosc = 0x0007feff; 274 s->cm_sdram = 0x00011122; 275 memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); 276 s->cm_init = 0x00000112; 277 s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 278 1000); 279 memory_region_init_ram(&s->flash, obj, "integrator.flash", 0x100000, 280 &error_fatal); 281 vmstate_register_ram_global(&s->flash); 282 283 memory_region_init_io(&s->iomem, obj, &integratorcm_ops, s, 284 "integratorcm", 0x00800000); 285 sysbus_init_mmio(dev, &s->iomem); 286 287 integratorcm_do_remap(s); 288 /* ??? Save/restore. */ 289 } 290 291 static void integratorcm_realize(DeviceState *d, Error **errp) 292 { 293 IntegratorCMState *s = INTEGRATOR_CM(d); 294 295 if (s->memsz >= 256) { 296 integrator_spd[31] = 64; 297 s->cm_sdram |= 0x10; 298 } else if (s->memsz >= 128) { 299 integrator_spd[31] = 32; 300 s->cm_sdram |= 0x0c; 301 } else if (s->memsz >= 64) { 302 integrator_spd[31] = 16; 303 s->cm_sdram |= 0x08; 304 } else if (s->memsz >= 32) { 305 integrator_spd[31] = 4; 306 s->cm_sdram |= 0x04; 307 } else { 308 integrator_spd[31] = 2; 309 } 310 } 311 312 /* Integrator/CP hardware emulation. */ 313 /* Primary interrupt controller. */ 314 315 #define TYPE_INTEGRATOR_PIC "integrator_pic" 316 #define INTEGRATOR_PIC(obj) \ 317 OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC) 318 319 typedef struct icp_pic_state { 320 /*< private >*/ 321 SysBusDevice parent_obj; 322 /*< public >*/ 323 324 MemoryRegion iomem; 325 uint32_t level; 326 uint32_t irq_enabled; 327 uint32_t fiq_enabled; 328 qemu_irq parent_irq; 329 qemu_irq parent_fiq; 330 } icp_pic_state; 331 332 static const VMStateDescription vmstate_icp_pic = { 333 .name = "icp_pic", 334 .version_id = 1, 335 .minimum_version_id = 1, 336 .fields = (VMStateField[]) { 337 VMSTATE_UINT32(level, icp_pic_state), 338 VMSTATE_UINT32(irq_enabled, icp_pic_state), 339 VMSTATE_UINT32(fiq_enabled, icp_pic_state), 340 VMSTATE_END_OF_LIST() 341 } 342 }; 343 344 static void icp_pic_update(icp_pic_state *s) 345 { 346 uint32_t flags; 347 348 flags = (s->level & s->irq_enabled); 349 qemu_set_irq(s->parent_irq, flags != 0); 350 flags = (s->level & s->fiq_enabled); 351 qemu_set_irq(s->parent_fiq, flags != 0); 352 } 353 354 static void icp_pic_set_irq(void *opaque, int irq, int level) 355 { 356 icp_pic_state *s = (icp_pic_state *)opaque; 357 if (level) 358 s->level |= 1 << irq; 359 else 360 s->level &= ~(1 << irq); 361 icp_pic_update(s); 362 } 363 364 static uint64_t icp_pic_read(void *opaque, hwaddr offset, 365 unsigned size) 366 { 367 icp_pic_state *s = (icp_pic_state *)opaque; 368 369 switch (offset >> 2) { 370 case 0: /* IRQ_STATUS */ 371 return s->level & s->irq_enabled; 372 case 1: /* IRQ_RAWSTAT */ 373 return s->level; 374 case 2: /* IRQ_ENABLESET */ 375 return s->irq_enabled; 376 case 4: /* INT_SOFTSET */ 377 return s->level & 1; 378 case 8: /* FRQ_STATUS */ 379 return s->level & s->fiq_enabled; 380 case 9: /* FRQ_RAWSTAT */ 381 return s->level; 382 case 10: /* FRQ_ENABLESET */ 383 return s->fiq_enabled; 384 case 3: /* IRQ_ENABLECLR */ 385 case 5: /* INT_SOFTCLR */ 386 case 11: /* FRQ_ENABLECLR */ 387 default: 388 printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset); 389 return 0; 390 } 391 } 392 393 static void icp_pic_write(void *opaque, hwaddr offset, 394 uint64_t value, unsigned size) 395 { 396 icp_pic_state *s = (icp_pic_state *)opaque; 397 398 switch (offset >> 2) { 399 case 2: /* IRQ_ENABLESET */ 400 s->irq_enabled |= value; 401 break; 402 case 3: /* IRQ_ENABLECLR */ 403 s->irq_enabled &= ~value; 404 break; 405 case 4: /* INT_SOFTSET */ 406 if (value & 1) 407 icp_pic_set_irq(s, 0, 1); 408 break; 409 case 5: /* INT_SOFTCLR */ 410 if (value & 1) 411 icp_pic_set_irq(s, 0, 0); 412 break; 413 case 10: /* FRQ_ENABLESET */ 414 s->fiq_enabled |= value; 415 break; 416 case 11: /* FRQ_ENABLECLR */ 417 s->fiq_enabled &= ~value; 418 break; 419 case 0: /* IRQ_STATUS */ 420 case 1: /* IRQ_RAWSTAT */ 421 case 8: /* FRQ_STATUS */ 422 case 9: /* FRQ_RAWSTAT */ 423 default: 424 printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset); 425 return; 426 } 427 icp_pic_update(s); 428 } 429 430 static const MemoryRegionOps icp_pic_ops = { 431 .read = icp_pic_read, 432 .write = icp_pic_write, 433 .endianness = DEVICE_NATIVE_ENDIAN, 434 }; 435 436 static void icp_pic_init(Object *obj) 437 { 438 DeviceState *dev = DEVICE(obj); 439 icp_pic_state *s = INTEGRATOR_PIC(obj); 440 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 441 442 qdev_init_gpio_in(dev, icp_pic_set_irq, 32); 443 sysbus_init_irq(sbd, &s->parent_irq); 444 sysbus_init_irq(sbd, &s->parent_fiq); 445 memory_region_init_io(&s->iomem, obj, &icp_pic_ops, s, 446 "icp-pic", 0x00800000); 447 sysbus_init_mmio(sbd, &s->iomem); 448 } 449 450 /* CP control registers. */ 451 452 #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs" 453 #define ICP_CONTROL_REGS(obj) \ 454 OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS) 455 456 typedef struct ICPCtrlRegsState { 457 /*< private >*/ 458 SysBusDevice parent_obj; 459 /*< public >*/ 460 461 MemoryRegion iomem; 462 463 qemu_irq mmc_irq; 464 uint32_t intreg_state; 465 } ICPCtrlRegsState; 466 467 #define ICP_GPIO_MMC_WPROT "mmc-wprot" 468 #define ICP_GPIO_MMC_CARDIN "mmc-cardin" 469 470 #define ICP_INTREG_WPROT (1 << 0) 471 #define ICP_INTREG_CARDIN (1 << 3) 472 473 static const VMStateDescription vmstate_icp_control = { 474 .name = "icp_control", 475 .version_id = 1, 476 .minimum_version_id = 1, 477 .fields = (VMStateField[]) { 478 VMSTATE_UINT32(intreg_state, ICPCtrlRegsState), 479 VMSTATE_END_OF_LIST() 480 } 481 }; 482 483 static uint64_t icp_control_read(void *opaque, hwaddr offset, 484 unsigned size) 485 { 486 ICPCtrlRegsState *s = opaque; 487 488 switch (offset >> 2) { 489 case 0: /* CP_IDFIELD */ 490 return 0x41034003; 491 case 1: /* CP_FLASHPROG */ 492 return 0; 493 case 2: /* CP_INTREG */ 494 return s->intreg_state; 495 case 3: /* CP_DECODE */ 496 return 0x11; 497 default: 498 hw_error("icp_control_read: Bad offset %x\n", (int)offset); 499 return 0; 500 } 501 } 502 503 static void icp_control_write(void *opaque, hwaddr offset, 504 uint64_t value, unsigned size) 505 { 506 ICPCtrlRegsState *s = opaque; 507 508 switch (offset >> 2) { 509 case 2: /* CP_INTREG */ 510 s->intreg_state &= ~(value & ICP_INTREG_CARDIN); 511 qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN)); 512 break; 513 case 1: /* CP_FLASHPROG */ 514 case 3: /* CP_DECODE */ 515 /* Nothing interesting implemented yet. */ 516 break; 517 default: 518 hw_error("icp_control_write: Bad offset %x\n", (int)offset); 519 } 520 } 521 522 static const MemoryRegionOps icp_control_ops = { 523 .read = icp_control_read, 524 .write = icp_control_write, 525 .endianness = DEVICE_NATIVE_ENDIAN, 526 }; 527 528 static void icp_control_mmc_wprot(void *opaque, int line, int level) 529 { 530 ICPCtrlRegsState *s = opaque; 531 532 s->intreg_state &= ~ICP_INTREG_WPROT; 533 if (level) { 534 s->intreg_state |= ICP_INTREG_WPROT; 535 } 536 } 537 538 static void icp_control_mmc_cardin(void *opaque, int line, int level) 539 { 540 ICPCtrlRegsState *s = opaque; 541 542 /* line is released by writing to CP_INTREG */ 543 if (level) { 544 s->intreg_state |= ICP_INTREG_CARDIN; 545 qemu_set_irq(s->mmc_irq, 1); 546 } 547 } 548 549 static void icp_control_init(Object *obj) 550 { 551 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 552 ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj); 553 DeviceState *dev = DEVICE(obj); 554 555 memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s, 556 "icp_ctrl_regs", 0x00800000); 557 sysbus_init_mmio(sbd, &s->iomem); 558 559 qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1); 560 qdev_init_gpio_in_named(dev, icp_control_mmc_cardin, 561 ICP_GPIO_MMC_CARDIN, 1); 562 sysbus_init_irq(sbd, &s->mmc_irq); 563 } 564 565 566 /* Board init. */ 567 568 static struct arm_boot_info integrator_binfo = { 569 .loader_start = 0x0, 570 .board_id = 0x113, 571 }; 572 573 static void integratorcp_init(MachineState *machine) 574 { 575 ram_addr_t ram_size = machine->ram_size; 576 const char *cpu_model = machine->cpu_model; 577 const char *kernel_filename = machine->kernel_filename; 578 const char *kernel_cmdline = machine->kernel_cmdline; 579 const char *initrd_filename = machine->initrd_filename; 580 char **cpustr; 581 ObjectClass *cpu_oc; 582 CPUClass *cc; 583 Object *cpuobj; 584 ARMCPU *cpu; 585 const char *typename; 586 MemoryRegion *address_space_mem = get_system_memory(); 587 MemoryRegion *ram = g_new(MemoryRegion, 1); 588 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 589 qemu_irq pic[32]; 590 DeviceState *dev, *sic, *icp; 591 int i; 592 Error *err = NULL; 593 594 if (!cpu_model) { 595 cpu_model = "arm926"; 596 } 597 598 cpustr = g_strsplit(cpu_model, ",", 2); 599 600 cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); 601 if (!cpu_oc) { 602 fprintf(stderr, "Unable to find CPU definition\n"); 603 exit(1); 604 } 605 typename = object_class_get_name(cpu_oc); 606 607 cc = CPU_CLASS(cpu_oc); 608 cc->parse_features(typename, cpustr[1], &err); 609 g_strfreev(cpustr); 610 if (err) { 611 error_report_err(err); 612 exit(1); 613 } 614 615 cpuobj = object_new(typename); 616 617 /* By default ARM1176 CPUs have EL3 enabled. This board does not 618 * currently support EL3 so the CPU EL3 property is disabled before 619 * realization. 620 */ 621 if (object_property_find(cpuobj, "has_el3", NULL)) { 622 object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 623 } 624 625 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 626 627 cpu = ARM_CPU(cpuobj); 628 629 memory_region_allocate_system_memory(ram, NULL, "integrator.ram", 630 ram_size); 631 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ 632 /* ??? RAM should repeat to fill physical memory space. */ 633 /* SDRAM at address zero*/ 634 memory_region_add_subregion(address_space_mem, 0, ram); 635 /* And again at address 0x80000000 */ 636 memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size); 637 memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias); 638 639 dev = qdev_create(NULL, TYPE_INTEGRATOR_CM); 640 qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); 641 qdev_init_nofail(dev); 642 sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); 643 644 dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000, 645 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), 646 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), 647 NULL); 648 for (i = 0; i < 32; i++) { 649 pic[i] = qdev_get_gpio_in(dev, i); 650 } 651 sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]); 652 sysbus_create_varargs("integrator_pit", 0x13000000, 653 pic[5], pic[6], pic[7], NULL); 654 sysbus_create_simple("pl031", 0x15000000, pic[8]); 655 pl011_create(0x16000000, pic[1], serial_hds[0]); 656 pl011_create(0x17000000, pic[2], serial_hds[1]); 657 icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000, 658 qdev_get_gpio_in(sic, 3)); 659 sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]); 660 sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]); 661 sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0); 662 663 dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL); 664 qdev_connect_gpio_out(dev, 0, 665 qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0)); 666 qdev_connect_gpio_out(dev, 1, 667 qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0)); 668 669 if (nd_table[0].used) 670 smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); 671 672 sysbus_create_simple("pl110", 0xc0000000, pic[22]); 673 674 integrator_binfo.ram_size = ram_size; 675 integrator_binfo.kernel_filename = kernel_filename; 676 integrator_binfo.kernel_cmdline = kernel_cmdline; 677 integrator_binfo.initrd_filename = initrd_filename; 678 arm_load_kernel(cpu, &integrator_binfo); 679 } 680 681 static void integratorcp_machine_init(MachineClass *mc) 682 { 683 mc->desc = "ARM Integrator/CP (ARM926EJ-S)"; 684 mc->init = integratorcp_init; 685 } 686 687 DEFINE_MACHINE("integratorcp", integratorcp_machine_init) 688 689 static Property core_properties[] = { 690 DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0), 691 DEFINE_PROP_END_OF_LIST(), 692 }; 693 694 static void core_class_init(ObjectClass *klass, void *data) 695 { 696 DeviceClass *dc = DEVICE_CLASS(klass); 697 698 dc->props = core_properties; 699 dc->realize = integratorcm_realize; 700 dc->vmsd = &vmstate_integratorcm; 701 } 702 703 static void icp_pic_class_init(ObjectClass *klass, void *data) 704 { 705 DeviceClass *dc = DEVICE_CLASS(klass); 706 707 dc->vmsd = &vmstate_icp_pic; 708 } 709 710 static void icp_control_class_init(ObjectClass *klass, void *data) 711 { 712 DeviceClass *dc = DEVICE_CLASS(klass); 713 714 dc->vmsd = &vmstate_icp_control; 715 } 716 717 static const TypeInfo core_info = { 718 .name = TYPE_INTEGRATOR_CM, 719 .parent = TYPE_SYS_BUS_DEVICE, 720 .instance_size = sizeof(IntegratorCMState), 721 .instance_init = integratorcm_init, 722 .class_init = core_class_init, 723 }; 724 725 static const TypeInfo icp_pic_info = { 726 .name = TYPE_INTEGRATOR_PIC, 727 .parent = TYPE_SYS_BUS_DEVICE, 728 .instance_size = sizeof(icp_pic_state), 729 .instance_init = icp_pic_init, 730 .class_init = icp_pic_class_init, 731 }; 732 733 static const TypeInfo icp_ctrl_regs_info = { 734 .name = TYPE_ICP_CONTROL_REGS, 735 .parent = TYPE_SYS_BUS_DEVICE, 736 .instance_size = sizeof(ICPCtrlRegsState), 737 .instance_init = icp_control_init, 738 .class_init = icp_control_class_init, 739 }; 740 741 static void integratorcp_register_types(void) 742 { 743 type_register_static(&icp_pic_info); 744 type_register_static(&core_info); 745 type_register_static(&icp_ctrl_regs_info); 746 } 747 748 type_init(integratorcp_register_types) 749