1 /* 2 * ARM Integrator CP System emulation. 3 * 4 * Copyright (c) 2005-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL 8 */ 9 10 #include "hw/sysbus.h" 11 #include "hw/devices.h" 12 #include "hw/boards.h" 13 #include "hw/arm/arm.h" 14 #include "hw/misc/arm_integrator_debug.h" 15 #include "net/net.h" 16 #include "exec/address-spaces.h" 17 #include "sysemu/sysemu.h" 18 #include "qemu/error-report.h" 19 20 #define TYPE_INTEGRATOR_CM "integrator_core" 21 #define INTEGRATOR_CM(obj) \ 22 OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM) 23 24 typedef struct IntegratorCMState { 25 /*< private >*/ 26 SysBusDevice parent_obj; 27 /*< public >*/ 28 29 MemoryRegion iomem; 30 uint32_t memsz; 31 MemoryRegion flash; 32 uint32_t cm_osc; 33 uint32_t cm_ctrl; 34 uint32_t cm_lock; 35 uint32_t cm_auxosc; 36 uint32_t cm_sdram; 37 uint32_t cm_init; 38 uint32_t cm_flags; 39 uint32_t cm_nvflags; 40 uint32_t cm_refcnt_offset; 41 uint32_t int_level; 42 uint32_t irq_enabled; 43 uint32_t fiq_enabled; 44 } IntegratorCMState; 45 46 static uint8_t integrator_spd[128] = { 47 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1, 48 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 49 }; 50 51 static uint64_t integratorcm_read(void *opaque, hwaddr offset, 52 unsigned size) 53 { 54 IntegratorCMState *s = opaque; 55 if (offset >= 0x100 && offset < 0x200) { 56 /* CM_SPD */ 57 if (offset >= 0x180) 58 return 0; 59 return integrator_spd[offset >> 2]; 60 } 61 switch (offset >> 2) { 62 case 0: /* CM_ID */ 63 return 0x411a3001; 64 case 1: /* CM_PROC */ 65 return 0; 66 case 2: /* CM_OSC */ 67 return s->cm_osc; 68 case 3: /* CM_CTRL */ 69 return s->cm_ctrl; 70 case 4: /* CM_STAT */ 71 return 0x00100000; 72 case 5: /* CM_LOCK */ 73 if (s->cm_lock == 0xa05f) { 74 return 0x1a05f; 75 } else { 76 return s->cm_lock; 77 } 78 case 6: /* CM_LMBUSCNT */ 79 /* ??? High frequency timer. */ 80 hw_error("integratorcm_read: CM_LMBUSCNT"); 81 case 7: /* CM_AUXOSC */ 82 return s->cm_auxosc; 83 case 8: /* CM_SDRAM */ 84 return s->cm_sdram; 85 case 9: /* CM_INIT */ 86 return s->cm_init; 87 case 10: /* CM_REFCNT */ 88 /* This register, CM_REFCNT, provides a 32-bit count value. 89 * The count increments at the fixed reference clock frequency of 24MHz 90 * and can be used as a real-time counter. 91 */ 92 return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 93 1000) - s->cm_refcnt_offset; 94 case 12: /* CM_FLAGS */ 95 return s->cm_flags; 96 case 14: /* CM_NVFLAGS */ 97 return s->cm_nvflags; 98 case 16: /* CM_IRQ_STAT */ 99 return s->int_level & s->irq_enabled; 100 case 17: /* CM_IRQ_RSTAT */ 101 return s->int_level; 102 case 18: /* CM_IRQ_ENSET */ 103 return s->irq_enabled; 104 case 20: /* CM_SOFT_INTSET */ 105 return s->int_level & 1; 106 case 24: /* CM_FIQ_STAT */ 107 return s->int_level & s->fiq_enabled; 108 case 25: /* CM_FIQ_RSTAT */ 109 return s->int_level; 110 case 26: /* CM_FIQ_ENSET */ 111 return s->fiq_enabled; 112 case 32: /* CM_VOLTAGE_CTL0 */ 113 case 33: /* CM_VOLTAGE_CTL1 */ 114 case 34: /* CM_VOLTAGE_CTL2 */ 115 case 35: /* CM_VOLTAGE_CTL3 */ 116 /* ??? Voltage control unimplemented. */ 117 return 0; 118 default: 119 hw_error("integratorcm_read: Unimplemented offset 0x%x\n", 120 (int)offset); 121 return 0; 122 } 123 } 124 125 static void integratorcm_do_remap(IntegratorCMState *s) 126 { 127 /* Sync memory region state with CM_CTRL REMAP bit: 128 * bit 0 => flash at address 0; bit 1 => RAM 129 */ 130 memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4)); 131 } 132 133 static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value) 134 { 135 if (value & 8) { 136 qemu_system_reset_request(); 137 } 138 if ((s->cm_ctrl ^ value) & 1) { 139 /* (value & 1) != 0 means the green "MISC LED" is lit. 140 * We don't have any nice place to display LEDs. printf is a bad 141 * idea because Linux uses the LED as a heartbeat and the output 142 * will swamp anything else on the terminal. 143 */ 144 } 145 /* Note that the RESET bit [3] always reads as zero */ 146 s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5); 147 integratorcm_do_remap(s); 148 } 149 150 static void integratorcm_update(IntegratorCMState *s) 151 { 152 /* ??? The CPU irq/fiq is raised when either the core module or base PIC 153 are active. */ 154 if (s->int_level & (s->irq_enabled | s->fiq_enabled)) 155 hw_error("Core module interrupt\n"); 156 } 157 158 static void integratorcm_write(void *opaque, hwaddr offset, 159 uint64_t value, unsigned size) 160 { 161 IntegratorCMState *s = opaque; 162 switch (offset >> 2) { 163 case 2: /* CM_OSC */ 164 if (s->cm_lock == 0xa05f) 165 s->cm_osc = value; 166 break; 167 case 3: /* CM_CTRL */ 168 integratorcm_set_ctrl(s, value); 169 break; 170 case 5: /* CM_LOCK */ 171 s->cm_lock = value & 0xffff; 172 break; 173 case 7: /* CM_AUXOSC */ 174 if (s->cm_lock == 0xa05f) 175 s->cm_auxosc = value; 176 break; 177 case 8: /* CM_SDRAM */ 178 s->cm_sdram = value; 179 break; 180 case 9: /* CM_INIT */ 181 /* ??? This can change the memory bus frequency. */ 182 s->cm_init = value; 183 break; 184 case 12: /* CM_FLAGSS */ 185 s->cm_flags |= value; 186 break; 187 case 13: /* CM_FLAGSC */ 188 s->cm_flags &= ~value; 189 break; 190 case 14: /* CM_NVFLAGSS */ 191 s->cm_nvflags |= value; 192 break; 193 case 15: /* CM_NVFLAGSS */ 194 s->cm_nvflags &= ~value; 195 break; 196 case 18: /* CM_IRQ_ENSET */ 197 s->irq_enabled |= value; 198 integratorcm_update(s); 199 break; 200 case 19: /* CM_IRQ_ENCLR */ 201 s->irq_enabled &= ~value; 202 integratorcm_update(s); 203 break; 204 case 20: /* CM_SOFT_INTSET */ 205 s->int_level |= (value & 1); 206 integratorcm_update(s); 207 break; 208 case 21: /* CM_SOFT_INTCLR */ 209 s->int_level &= ~(value & 1); 210 integratorcm_update(s); 211 break; 212 case 26: /* CM_FIQ_ENSET */ 213 s->fiq_enabled |= value; 214 integratorcm_update(s); 215 break; 216 case 27: /* CM_FIQ_ENCLR */ 217 s->fiq_enabled &= ~value; 218 integratorcm_update(s); 219 break; 220 case 32: /* CM_VOLTAGE_CTL0 */ 221 case 33: /* CM_VOLTAGE_CTL1 */ 222 case 34: /* CM_VOLTAGE_CTL2 */ 223 case 35: /* CM_VOLTAGE_CTL3 */ 224 /* ??? Voltage control unimplemented. */ 225 break; 226 default: 227 hw_error("integratorcm_write: Unimplemented offset 0x%x\n", 228 (int)offset); 229 break; 230 } 231 } 232 233 /* Integrator/CM control registers. */ 234 235 static const MemoryRegionOps integratorcm_ops = { 236 .read = integratorcm_read, 237 .write = integratorcm_write, 238 .endianness = DEVICE_NATIVE_ENDIAN, 239 }; 240 241 static int integratorcm_init(SysBusDevice *dev) 242 { 243 IntegratorCMState *s = INTEGRATOR_CM(dev); 244 245 s->cm_osc = 0x01000048; 246 /* ??? What should the high bits of this value be? */ 247 s->cm_auxosc = 0x0007feff; 248 s->cm_sdram = 0x00011122; 249 if (s->memsz >= 256) { 250 integrator_spd[31] = 64; 251 s->cm_sdram |= 0x10; 252 } else if (s->memsz >= 128) { 253 integrator_spd[31] = 32; 254 s->cm_sdram |= 0x0c; 255 } else if (s->memsz >= 64) { 256 integrator_spd[31] = 16; 257 s->cm_sdram |= 0x08; 258 } else if (s->memsz >= 32) { 259 integrator_spd[31] = 4; 260 s->cm_sdram |= 0x04; 261 } else { 262 integrator_spd[31] = 2; 263 } 264 memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); 265 s->cm_init = 0x00000112; 266 s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 267 1000); 268 memory_region_init_ram(&s->flash, OBJECT(s), "integrator.flash", 0x100000, 269 &error_fatal); 270 vmstate_register_ram_global(&s->flash); 271 272 memory_region_init_io(&s->iomem, OBJECT(s), &integratorcm_ops, s, 273 "integratorcm", 0x00800000); 274 sysbus_init_mmio(dev, &s->iomem); 275 276 integratorcm_do_remap(s); 277 /* ??? Save/restore. */ 278 return 0; 279 } 280 281 /* Integrator/CP hardware emulation. */ 282 /* Primary interrupt controller. */ 283 284 #define TYPE_INTEGRATOR_PIC "integrator_pic" 285 #define INTEGRATOR_PIC(obj) \ 286 OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC) 287 288 typedef struct icp_pic_state { 289 /*< private >*/ 290 SysBusDevice parent_obj; 291 /*< public >*/ 292 293 MemoryRegion iomem; 294 uint32_t level; 295 uint32_t irq_enabled; 296 uint32_t fiq_enabled; 297 qemu_irq parent_irq; 298 qemu_irq parent_fiq; 299 } icp_pic_state; 300 301 static void icp_pic_update(icp_pic_state *s) 302 { 303 uint32_t flags; 304 305 flags = (s->level & s->irq_enabled); 306 qemu_set_irq(s->parent_irq, flags != 0); 307 flags = (s->level & s->fiq_enabled); 308 qemu_set_irq(s->parent_fiq, flags != 0); 309 } 310 311 static void icp_pic_set_irq(void *opaque, int irq, int level) 312 { 313 icp_pic_state *s = (icp_pic_state *)opaque; 314 if (level) 315 s->level |= 1 << irq; 316 else 317 s->level &= ~(1 << irq); 318 icp_pic_update(s); 319 } 320 321 static uint64_t icp_pic_read(void *opaque, hwaddr offset, 322 unsigned size) 323 { 324 icp_pic_state *s = (icp_pic_state *)opaque; 325 326 switch (offset >> 2) { 327 case 0: /* IRQ_STATUS */ 328 return s->level & s->irq_enabled; 329 case 1: /* IRQ_RAWSTAT */ 330 return s->level; 331 case 2: /* IRQ_ENABLESET */ 332 return s->irq_enabled; 333 case 4: /* INT_SOFTSET */ 334 return s->level & 1; 335 case 8: /* FRQ_STATUS */ 336 return s->level & s->fiq_enabled; 337 case 9: /* FRQ_RAWSTAT */ 338 return s->level; 339 case 10: /* FRQ_ENABLESET */ 340 return s->fiq_enabled; 341 case 3: /* IRQ_ENABLECLR */ 342 case 5: /* INT_SOFTCLR */ 343 case 11: /* FRQ_ENABLECLR */ 344 default: 345 printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset); 346 return 0; 347 } 348 } 349 350 static void icp_pic_write(void *opaque, hwaddr offset, 351 uint64_t value, unsigned size) 352 { 353 icp_pic_state *s = (icp_pic_state *)opaque; 354 355 switch (offset >> 2) { 356 case 2: /* IRQ_ENABLESET */ 357 s->irq_enabled |= value; 358 break; 359 case 3: /* IRQ_ENABLECLR */ 360 s->irq_enabled &= ~value; 361 break; 362 case 4: /* INT_SOFTSET */ 363 if (value & 1) 364 icp_pic_set_irq(s, 0, 1); 365 break; 366 case 5: /* INT_SOFTCLR */ 367 if (value & 1) 368 icp_pic_set_irq(s, 0, 0); 369 break; 370 case 10: /* FRQ_ENABLESET */ 371 s->fiq_enabled |= value; 372 break; 373 case 11: /* FRQ_ENABLECLR */ 374 s->fiq_enabled &= ~value; 375 break; 376 case 0: /* IRQ_STATUS */ 377 case 1: /* IRQ_RAWSTAT */ 378 case 8: /* FRQ_STATUS */ 379 case 9: /* FRQ_RAWSTAT */ 380 default: 381 printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset); 382 return; 383 } 384 icp_pic_update(s); 385 } 386 387 static const MemoryRegionOps icp_pic_ops = { 388 .read = icp_pic_read, 389 .write = icp_pic_write, 390 .endianness = DEVICE_NATIVE_ENDIAN, 391 }; 392 393 static int icp_pic_init(SysBusDevice *sbd) 394 { 395 DeviceState *dev = DEVICE(sbd); 396 icp_pic_state *s = INTEGRATOR_PIC(dev); 397 398 qdev_init_gpio_in(dev, icp_pic_set_irq, 32); 399 sysbus_init_irq(sbd, &s->parent_irq); 400 sysbus_init_irq(sbd, &s->parent_fiq); 401 memory_region_init_io(&s->iomem, OBJECT(s), &icp_pic_ops, s, 402 "icp-pic", 0x00800000); 403 sysbus_init_mmio(sbd, &s->iomem); 404 return 0; 405 } 406 407 /* CP control registers. */ 408 409 #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs" 410 #define ICP_CONTROL_REGS(obj) \ 411 OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS) 412 413 typedef struct ICPCtrlRegsState { 414 /*< private >*/ 415 SysBusDevice parent_obj; 416 /*< public >*/ 417 418 MemoryRegion iomem; 419 420 qemu_irq mmc_irq; 421 uint32_t intreg_state; 422 } ICPCtrlRegsState; 423 424 #define ICP_GPIO_MMC_WPROT "mmc-wprot" 425 #define ICP_GPIO_MMC_CARDIN "mmc-cardin" 426 427 #define ICP_INTREG_WPROT (1 << 0) 428 #define ICP_INTREG_CARDIN (1 << 3) 429 430 static uint64_t icp_control_read(void *opaque, hwaddr offset, 431 unsigned size) 432 { 433 ICPCtrlRegsState *s = opaque; 434 435 switch (offset >> 2) { 436 case 0: /* CP_IDFIELD */ 437 return 0x41034003; 438 case 1: /* CP_FLASHPROG */ 439 return 0; 440 case 2: /* CP_INTREG */ 441 return s->intreg_state; 442 case 3: /* CP_DECODE */ 443 return 0x11; 444 default: 445 hw_error("icp_control_read: Bad offset %x\n", (int)offset); 446 return 0; 447 } 448 } 449 450 static void icp_control_write(void *opaque, hwaddr offset, 451 uint64_t value, unsigned size) 452 { 453 ICPCtrlRegsState *s = opaque; 454 455 switch (offset >> 2) { 456 case 2: /* CP_INTREG */ 457 s->intreg_state &= ~(value & ICP_INTREG_CARDIN); 458 qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN)); 459 break; 460 case 1: /* CP_FLASHPROG */ 461 case 3: /* CP_DECODE */ 462 /* Nothing interesting implemented yet. */ 463 break; 464 default: 465 hw_error("icp_control_write: Bad offset %x\n", (int)offset); 466 } 467 } 468 469 static const MemoryRegionOps icp_control_ops = { 470 .read = icp_control_read, 471 .write = icp_control_write, 472 .endianness = DEVICE_NATIVE_ENDIAN, 473 }; 474 475 static void icp_control_mmc_wprot(void *opaque, int line, int level) 476 { 477 ICPCtrlRegsState *s = opaque; 478 479 s->intreg_state &= ~ICP_INTREG_WPROT; 480 if (level) { 481 s->intreg_state |= ICP_INTREG_WPROT; 482 } 483 } 484 485 static void icp_control_mmc_cardin(void *opaque, int line, int level) 486 { 487 ICPCtrlRegsState *s = opaque; 488 489 /* line is released by writing to CP_INTREG */ 490 if (level) { 491 s->intreg_state |= ICP_INTREG_CARDIN; 492 qemu_set_irq(s->mmc_irq, 1); 493 } 494 } 495 496 static void icp_control_init(Object *obj) 497 { 498 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 499 ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj); 500 DeviceState *dev = DEVICE(obj); 501 502 memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s, 503 "icp_ctrl_regs", 0x00800000); 504 sysbus_init_mmio(sbd, &s->iomem); 505 506 qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1); 507 qdev_init_gpio_in_named(dev, icp_control_mmc_cardin, 508 ICP_GPIO_MMC_CARDIN, 1); 509 sysbus_init_irq(sbd, &s->mmc_irq); 510 } 511 512 513 /* Board init. */ 514 515 static struct arm_boot_info integrator_binfo = { 516 .loader_start = 0x0, 517 .board_id = 0x113, 518 }; 519 520 static void integratorcp_init(MachineState *machine) 521 { 522 ram_addr_t ram_size = machine->ram_size; 523 const char *cpu_model = machine->cpu_model; 524 const char *kernel_filename = machine->kernel_filename; 525 const char *kernel_cmdline = machine->kernel_cmdline; 526 const char *initrd_filename = machine->initrd_filename; 527 ObjectClass *cpu_oc; 528 Object *cpuobj; 529 ARMCPU *cpu; 530 MemoryRegion *address_space_mem = get_system_memory(); 531 MemoryRegion *ram = g_new(MemoryRegion, 1); 532 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 533 qemu_irq pic[32]; 534 DeviceState *dev, *sic, *icp; 535 int i; 536 Error *err = NULL; 537 538 if (!cpu_model) { 539 cpu_model = "arm926"; 540 } 541 542 cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 543 if (!cpu_oc) { 544 fprintf(stderr, "Unable to find CPU definition\n"); 545 exit(1); 546 } 547 548 cpuobj = object_new(object_class_get_name(cpu_oc)); 549 550 /* By default ARM1176 CPUs have EL3 enabled. This board does not 551 * currently support EL3 so the CPU EL3 property is disabled before 552 * realization. 553 */ 554 if (object_property_find(cpuobj, "has_el3", NULL)) { 555 object_property_set_bool(cpuobj, false, "has_el3", &err); 556 if (err) { 557 error_report_err(err); 558 exit(1); 559 } 560 } 561 562 object_property_set_bool(cpuobj, true, "realized", &err); 563 if (err) { 564 error_report_err(err); 565 exit(1); 566 } 567 568 cpu = ARM_CPU(cpuobj); 569 570 memory_region_allocate_system_memory(ram, NULL, "integrator.ram", 571 ram_size); 572 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ 573 /* ??? RAM should repeat to fill physical memory space. */ 574 /* SDRAM at address zero*/ 575 memory_region_add_subregion(address_space_mem, 0, ram); 576 /* And again at address 0x80000000 */ 577 memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size); 578 memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias); 579 580 dev = qdev_create(NULL, TYPE_INTEGRATOR_CM); 581 qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); 582 qdev_init_nofail(dev); 583 sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); 584 585 dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000, 586 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), 587 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), 588 NULL); 589 for (i = 0; i < 32; i++) { 590 pic[i] = qdev_get_gpio_in(dev, i); 591 } 592 sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]); 593 sysbus_create_varargs("integrator_pit", 0x13000000, 594 pic[5], pic[6], pic[7], NULL); 595 sysbus_create_simple("pl031", 0x15000000, pic[8]); 596 sysbus_create_simple("pl011", 0x16000000, pic[1]); 597 sysbus_create_simple("pl011", 0x17000000, pic[2]); 598 icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000, 599 qdev_get_gpio_in(sic, 3)); 600 sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]); 601 sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]); 602 sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0); 603 604 dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL); 605 qdev_connect_gpio_out(dev, 0, 606 qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0)); 607 qdev_connect_gpio_out(dev, 1, 608 qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0)); 609 610 if (nd_table[0].used) 611 smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); 612 613 sysbus_create_simple("pl110", 0xc0000000, pic[22]); 614 615 integrator_binfo.ram_size = ram_size; 616 integrator_binfo.kernel_filename = kernel_filename; 617 integrator_binfo.kernel_cmdline = kernel_cmdline; 618 integrator_binfo.initrd_filename = initrd_filename; 619 arm_load_kernel(cpu, &integrator_binfo); 620 } 621 622 static void integratorcp_machine_init(MachineClass *mc) 623 { 624 mc->desc = "ARM Integrator/CP (ARM926EJ-S)"; 625 mc->init = integratorcp_init; 626 } 627 628 DEFINE_MACHINE("integratorcp", integratorcp_machine_init) 629 630 static Property core_properties[] = { 631 DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0), 632 DEFINE_PROP_END_OF_LIST(), 633 }; 634 635 static void core_class_init(ObjectClass *klass, void *data) 636 { 637 DeviceClass *dc = DEVICE_CLASS(klass); 638 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 639 640 k->init = integratorcm_init; 641 dc->props = core_properties; 642 } 643 644 static const TypeInfo core_info = { 645 .name = TYPE_INTEGRATOR_CM, 646 .parent = TYPE_SYS_BUS_DEVICE, 647 .instance_size = sizeof(IntegratorCMState), 648 .class_init = core_class_init, 649 }; 650 651 static void icp_pic_class_init(ObjectClass *klass, void *data) 652 { 653 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 654 655 sdc->init = icp_pic_init; 656 } 657 658 static const TypeInfo icp_pic_info = { 659 .name = TYPE_INTEGRATOR_PIC, 660 .parent = TYPE_SYS_BUS_DEVICE, 661 .instance_size = sizeof(icp_pic_state), 662 .class_init = icp_pic_class_init, 663 }; 664 665 static const TypeInfo icp_ctrl_regs_info = { 666 .name = TYPE_ICP_CONTROL_REGS, 667 .parent = TYPE_SYS_BUS_DEVICE, 668 .instance_size = sizeof(ICPCtrlRegsState), 669 .instance_init = icp_control_init, 670 }; 671 672 static void integratorcp_register_types(void) 673 { 674 type_register_static(&icp_pic_info); 675 type_register_static(&core_info); 676 type_register_static(&icp_ctrl_regs_info); 677 } 678 679 type_init(integratorcp_register_types) 680