xref: /openbmc/qemu/hw/arm/integratorcp.c (revision 650d103d3ea959212f826acb9d3fe80cf30e347b)
1 /*
2  * ARM Integrator CP System emulation.
3  *
4  * Copyright (c) 2005-2007 CodeSourcery.
5  * Written by Paul Brook
6  *
7  * This code is licensed under the GPL
8  */
9 
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "cpu.h"
13 #include "hw/sysbus.h"
14 #include "migration/vmstate.h"
15 #include "hw/boards.h"
16 #include "hw/arm/boot.h"
17 #include "hw/misc/arm_integrator_debug.h"
18 #include "hw/net/smc91c111.h"
19 #include "net/net.h"
20 #include "exec/address-spaces.h"
21 #include "sysemu/sysemu.h"
22 #include "qemu/error-report.h"
23 #include "hw/char/pl011.h"
24 #include "hw/hw.h"
25 #include "hw/irq.h"
26 
27 #define TYPE_INTEGRATOR_CM "integrator_core"
28 #define INTEGRATOR_CM(obj) \
29     OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM)
30 
31 typedef struct IntegratorCMState {
32     /*< private >*/
33     SysBusDevice parent_obj;
34     /*< public >*/
35 
36     MemoryRegion iomem;
37     uint32_t memsz;
38     MemoryRegion flash;
39     uint32_t cm_osc;
40     uint32_t cm_ctrl;
41     uint32_t cm_lock;
42     uint32_t cm_auxosc;
43     uint32_t cm_sdram;
44     uint32_t cm_init;
45     uint32_t cm_flags;
46     uint32_t cm_nvflags;
47     uint32_t cm_refcnt_offset;
48     uint32_t int_level;
49     uint32_t irq_enabled;
50     uint32_t fiq_enabled;
51 } IntegratorCMState;
52 
53 static uint8_t integrator_spd[128] = {
54    128, 8, 4, 11, 9, 1, 64, 0,  2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
55    0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
56 };
57 
58 static const VMStateDescription vmstate_integratorcm = {
59     .name = "integratorcm",
60     .version_id = 1,
61     .minimum_version_id = 1,
62     .fields      = (VMStateField[]) {
63         VMSTATE_UINT32(cm_osc, IntegratorCMState),
64         VMSTATE_UINT32(cm_ctrl, IntegratorCMState),
65         VMSTATE_UINT32(cm_lock, IntegratorCMState),
66         VMSTATE_UINT32(cm_auxosc, IntegratorCMState),
67         VMSTATE_UINT32(cm_sdram, IntegratorCMState),
68         VMSTATE_UINT32(cm_init, IntegratorCMState),
69         VMSTATE_UINT32(cm_flags, IntegratorCMState),
70         VMSTATE_UINT32(cm_nvflags, IntegratorCMState),
71         VMSTATE_UINT32(int_level, IntegratorCMState),
72         VMSTATE_UINT32(irq_enabled, IntegratorCMState),
73         VMSTATE_UINT32(fiq_enabled, IntegratorCMState),
74         VMSTATE_END_OF_LIST()
75     }
76 };
77 
78 static uint64_t integratorcm_read(void *opaque, hwaddr offset,
79                                   unsigned size)
80 {
81     IntegratorCMState *s = opaque;
82     if (offset >= 0x100 && offset < 0x200) {
83         /* CM_SPD */
84         if (offset >= 0x180)
85             return 0;
86         return integrator_spd[offset >> 2];
87     }
88     switch (offset >> 2) {
89     case 0: /* CM_ID */
90         return 0x411a3001;
91     case 1: /* CM_PROC */
92         return 0;
93     case 2: /* CM_OSC */
94         return s->cm_osc;
95     case 3: /* CM_CTRL */
96         return s->cm_ctrl;
97     case 4: /* CM_STAT */
98         return 0x00100000;
99     case 5: /* CM_LOCK */
100         if (s->cm_lock == 0xa05f) {
101             return 0x1a05f;
102         } else {
103             return s->cm_lock;
104         }
105     case 6: /* CM_LMBUSCNT */
106         /* ??? High frequency timer.  */
107         hw_error("integratorcm_read: CM_LMBUSCNT");
108     case 7: /* CM_AUXOSC */
109         return s->cm_auxosc;
110     case 8: /* CM_SDRAM */
111         return s->cm_sdram;
112     case 9: /* CM_INIT */
113         return s->cm_init;
114     case 10: /* CM_REFCNT */
115         /* This register, CM_REFCNT, provides a 32-bit count value.
116          * The count increments at the fixed reference clock frequency of 24MHz
117          * and can be used as a real-time counter.
118          */
119         return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
120                                   1000) - s->cm_refcnt_offset;
121     case 12: /* CM_FLAGS */
122         return s->cm_flags;
123     case 14: /* CM_NVFLAGS */
124         return s->cm_nvflags;
125     case 16: /* CM_IRQ_STAT */
126         return s->int_level & s->irq_enabled;
127     case 17: /* CM_IRQ_RSTAT */
128         return s->int_level;
129     case 18: /* CM_IRQ_ENSET */
130         return s->irq_enabled;
131     case 20: /* CM_SOFT_INTSET */
132         return s->int_level & 1;
133     case 24: /* CM_FIQ_STAT */
134         return s->int_level & s->fiq_enabled;
135     case 25: /* CM_FIQ_RSTAT */
136         return s->int_level;
137     case 26: /* CM_FIQ_ENSET */
138         return s->fiq_enabled;
139     case 32: /* CM_VOLTAGE_CTL0 */
140     case 33: /* CM_VOLTAGE_CTL1 */
141     case 34: /* CM_VOLTAGE_CTL2 */
142     case 35: /* CM_VOLTAGE_CTL3 */
143         /* ??? Voltage control unimplemented.  */
144         return 0;
145     default:
146         hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
147                  (int)offset);
148         return 0;
149     }
150 }
151 
152 static void integratorcm_do_remap(IntegratorCMState *s)
153 {
154     /* Sync memory region state with CM_CTRL REMAP bit:
155      * bit 0 => flash at address 0; bit 1 => RAM
156      */
157     memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4));
158 }
159 
160 static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value)
161 {
162     if (value & 8) {
163         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
164     }
165     if ((s->cm_ctrl ^ value) & 1) {
166         /* (value & 1) != 0 means the green "MISC LED" is lit.
167          * We don't have any nice place to display LEDs. printf is a bad
168          * idea because Linux uses the LED as a heartbeat and the output
169          * will swamp anything else on the terminal.
170          */
171     }
172     /* Note that the RESET bit [3] always reads as zero */
173     s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5);
174     integratorcm_do_remap(s);
175 }
176 
177 static void integratorcm_update(IntegratorCMState *s)
178 {
179     /* ??? The CPU irq/fiq is raised when either the core module or base PIC
180        are active.  */
181     if (s->int_level & (s->irq_enabled | s->fiq_enabled))
182         hw_error("Core module interrupt\n");
183 }
184 
185 static void integratorcm_write(void *opaque, hwaddr offset,
186                                uint64_t value, unsigned size)
187 {
188     IntegratorCMState *s = opaque;
189     switch (offset >> 2) {
190     case 2: /* CM_OSC */
191         if (s->cm_lock == 0xa05f)
192             s->cm_osc = value;
193         break;
194     case 3: /* CM_CTRL */
195         integratorcm_set_ctrl(s, value);
196         break;
197     case 5: /* CM_LOCK */
198         s->cm_lock = value & 0xffff;
199         break;
200     case 7: /* CM_AUXOSC */
201         if (s->cm_lock == 0xa05f)
202             s->cm_auxosc = value;
203         break;
204     case 8: /* CM_SDRAM */
205         s->cm_sdram = value;
206         break;
207     case 9: /* CM_INIT */
208         /* ??? This can change the memory bus frequency.  */
209         s->cm_init = value;
210         break;
211     case 12: /* CM_FLAGSS */
212         s->cm_flags |= value;
213         break;
214     case 13: /* CM_FLAGSC */
215         s->cm_flags &= ~value;
216         break;
217     case 14: /* CM_NVFLAGSS */
218         s->cm_nvflags |= value;
219         break;
220     case 15: /* CM_NVFLAGSS */
221         s->cm_nvflags &= ~value;
222         break;
223     case 18: /* CM_IRQ_ENSET */
224         s->irq_enabled |= value;
225         integratorcm_update(s);
226         break;
227     case 19: /* CM_IRQ_ENCLR */
228         s->irq_enabled &= ~value;
229         integratorcm_update(s);
230         break;
231     case 20: /* CM_SOFT_INTSET */
232         s->int_level |= (value & 1);
233         integratorcm_update(s);
234         break;
235     case 21: /* CM_SOFT_INTCLR */
236         s->int_level &= ~(value & 1);
237         integratorcm_update(s);
238         break;
239     case 26: /* CM_FIQ_ENSET */
240         s->fiq_enabled |= value;
241         integratorcm_update(s);
242         break;
243     case 27: /* CM_FIQ_ENCLR */
244         s->fiq_enabled &= ~value;
245         integratorcm_update(s);
246         break;
247     case 32: /* CM_VOLTAGE_CTL0 */
248     case 33: /* CM_VOLTAGE_CTL1 */
249     case 34: /* CM_VOLTAGE_CTL2 */
250     case 35: /* CM_VOLTAGE_CTL3 */
251         /* ??? Voltage control unimplemented.  */
252         break;
253     default:
254         hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
255                  (int)offset);
256         break;
257     }
258 }
259 
260 /* Integrator/CM control registers.  */
261 
262 static const MemoryRegionOps integratorcm_ops = {
263     .read = integratorcm_read,
264     .write = integratorcm_write,
265     .endianness = DEVICE_NATIVE_ENDIAN,
266 };
267 
268 static void integratorcm_init(Object *obj)
269 {
270     IntegratorCMState *s = INTEGRATOR_CM(obj);
271 
272     s->cm_osc = 0x01000048;
273     /* ??? What should the high bits of this value be?  */
274     s->cm_auxosc = 0x0007feff;
275     s->cm_sdram = 0x00011122;
276     memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
277     s->cm_init = 0x00000112;
278     s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
279                                    1000);
280 
281     /* ??? Save/restore.  */
282 }
283 
284 static void integratorcm_realize(DeviceState *d, Error **errp)
285 {
286     IntegratorCMState *s = INTEGRATOR_CM(d);
287     SysBusDevice *dev = SYS_BUS_DEVICE(d);
288     Error *local_err = NULL;
289 
290     memory_region_init_ram(&s->flash, OBJECT(d), "integrator.flash", 0x100000,
291                            &local_err);
292     if (local_err) {
293         error_propagate(errp, local_err);
294         return;
295     }
296 
297     memory_region_init_io(&s->iomem, OBJECT(d), &integratorcm_ops, s,
298                           "integratorcm", 0x00800000);
299     sysbus_init_mmio(dev, &s->iomem);
300 
301     integratorcm_do_remap(s);
302 
303     if (s->memsz >= 256) {
304         integrator_spd[31] = 64;
305         s->cm_sdram |= 0x10;
306     } else if (s->memsz >= 128) {
307         integrator_spd[31] = 32;
308         s->cm_sdram |= 0x0c;
309     } else if (s->memsz >= 64) {
310         integrator_spd[31] = 16;
311         s->cm_sdram |= 0x08;
312     } else if (s->memsz >= 32) {
313         integrator_spd[31] = 4;
314         s->cm_sdram |= 0x04;
315     } else {
316         integrator_spd[31] = 2;
317     }
318 }
319 
320 /* Integrator/CP hardware emulation.  */
321 /* Primary interrupt controller.  */
322 
323 #define TYPE_INTEGRATOR_PIC "integrator_pic"
324 #define INTEGRATOR_PIC(obj) \
325    OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC)
326 
327 typedef struct icp_pic_state {
328     /*< private >*/
329     SysBusDevice parent_obj;
330     /*< public >*/
331 
332     MemoryRegion iomem;
333     uint32_t level;
334     uint32_t irq_enabled;
335     uint32_t fiq_enabled;
336     qemu_irq parent_irq;
337     qemu_irq parent_fiq;
338 } icp_pic_state;
339 
340 static const VMStateDescription vmstate_icp_pic = {
341     .name = "icp_pic",
342     .version_id = 1,
343     .minimum_version_id = 1,
344     .fields      = (VMStateField[]) {
345         VMSTATE_UINT32(level, icp_pic_state),
346         VMSTATE_UINT32(irq_enabled, icp_pic_state),
347         VMSTATE_UINT32(fiq_enabled, icp_pic_state),
348         VMSTATE_END_OF_LIST()
349     }
350 };
351 
352 static void icp_pic_update(icp_pic_state *s)
353 {
354     uint32_t flags;
355 
356     flags = (s->level & s->irq_enabled);
357     qemu_set_irq(s->parent_irq, flags != 0);
358     flags = (s->level & s->fiq_enabled);
359     qemu_set_irq(s->parent_fiq, flags != 0);
360 }
361 
362 static void icp_pic_set_irq(void *opaque, int irq, int level)
363 {
364     icp_pic_state *s = (icp_pic_state *)opaque;
365     if (level)
366         s->level |= 1 << irq;
367     else
368         s->level &= ~(1 << irq);
369     icp_pic_update(s);
370 }
371 
372 static uint64_t icp_pic_read(void *opaque, hwaddr offset,
373                              unsigned size)
374 {
375     icp_pic_state *s = (icp_pic_state *)opaque;
376 
377     switch (offset >> 2) {
378     case 0: /* IRQ_STATUS */
379         return s->level & s->irq_enabled;
380     case 1: /* IRQ_RAWSTAT */
381         return s->level;
382     case 2: /* IRQ_ENABLESET */
383         return s->irq_enabled;
384     case 4: /* INT_SOFTSET */
385         return s->level & 1;
386     case 8: /* FRQ_STATUS */
387         return s->level & s->fiq_enabled;
388     case 9: /* FRQ_RAWSTAT */
389         return s->level;
390     case 10: /* FRQ_ENABLESET */
391         return s->fiq_enabled;
392     case 3: /* IRQ_ENABLECLR */
393     case 5: /* INT_SOFTCLR */
394     case 11: /* FRQ_ENABLECLR */
395     default:
396         printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
397         return 0;
398     }
399 }
400 
401 static void icp_pic_write(void *opaque, hwaddr offset,
402                           uint64_t value, unsigned size)
403 {
404     icp_pic_state *s = (icp_pic_state *)opaque;
405 
406     switch (offset >> 2) {
407     case 2: /* IRQ_ENABLESET */
408         s->irq_enabled |= value;
409         break;
410     case 3: /* IRQ_ENABLECLR */
411         s->irq_enabled &= ~value;
412         break;
413     case 4: /* INT_SOFTSET */
414         if (value & 1)
415             icp_pic_set_irq(s, 0, 1);
416         break;
417     case 5: /* INT_SOFTCLR */
418         if (value & 1)
419             icp_pic_set_irq(s, 0, 0);
420         break;
421     case 10: /* FRQ_ENABLESET */
422         s->fiq_enabled |= value;
423         break;
424     case 11: /* FRQ_ENABLECLR */
425         s->fiq_enabled &= ~value;
426         break;
427     case 0: /* IRQ_STATUS */
428     case 1: /* IRQ_RAWSTAT */
429     case 8: /* FRQ_STATUS */
430     case 9: /* FRQ_RAWSTAT */
431     default:
432         printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
433         return;
434     }
435     icp_pic_update(s);
436 }
437 
438 static const MemoryRegionOps icp_pic_ops = {
439     .read = icp_pic_read,
440     .write = icp_pic_write,
441     .endianness = DEVICE_NATIVE_ENDIAN,
442 };
443 
444 static void icp_pic_init(Object *obj)
445 {
446     DeviceState *dev = DEVICE(obj);
447     icp_pic_state *s = INTEGRATOR_PIC(obj);
448     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
449 
450     qdev_init_gpio_in(dev, icp_pic_set_irq, 32);
451     sysbus_init_irq(sbd, &s->parent_irq);
452     sysbus_init_irq(sbd, &s->parent_fiq);
453     memory_region_init_io(&s->iomem, obj, &icp_pic_ops, s,
454                           "icp-pic", 0x00800000);
455     sysbus_init_mmio(sbd, &s->iomem);
456 }
457 
458 /* CP control registers.  */
459 
460 #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs"
461 #define ICP_CONTROL_REGS(obj) \
462     OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS)
463 
464 typedef struct ICPCtrlRegsState {
465     /*< private >*/
466     SysBusDevice parent_obj;
467     /*< public >*/
468 
469     MemoryRegion iomem;
470 
471     qemu_irq mmc_irq;
472     uint32_t intreg_state;
473 } ICPCtrlRegsState;
474 
475 #define ICP_GPIO_MMC_WPROT      "mmc-wprot"
476 #define ICP_GPIO_MMC_CARDIN     "mmc-cardin"
477 
478 #define ICP_INTREG_WPROT        (1 << 0)
479 #define ICP_INTREG_CARDIN       (1 << 3)
480 
481 static const VMStateDescription vmstate_icp_control = {
482     .name = "icp_control",
483     .version_id = 1,
484     .minimum_version_id = 1,
485     .fields      = (VMStateField[]) {
486         VMSTATE_UINT32(intreg_state, ICPCtrlRegsState),
487         VMSTATE_END_OF_LIST()
488     }
489 };
490 
491 static uint64_t icp_control_read(void *opaque, hwaddr offset,
492                                  unsigned size)
493 {
494     ICPCtrlRegsState *s = opaque;
495 
496     switch (offset >> 2) {
497     case 0: /* CP_IDFIELD */
498         return 0x41034003;
499     case 1: /* CP_FLASHPROG */
500         return 0;
501     case 2: /* CP_INTREG */
502         return s->intreg_state;
503     case 3: /* CP_DECODE */
504         return 0x11;
505     default:
506         hw_error("icp_control_read: Bad offset %x\n", (int)offset);
507         return 0;
508     }
509 }
510 
511 static void icp_control_write(void *opaque, hwaddr offset,
512                           uint64_t value, unsigned size)
513 {
514     ICPCtrlRegsState *s = opaque;
515 
516     switch (offset >> 2) {
517     case 2: /* CP_INTREG */
518         s->intreg_state &= ~(value & ICP_INTREG_CARDIN);
519         qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN));
520         break;
521     case 1: /* CP_FLASHPROG */
522     case 3: /* CP_DECODE */
523         /* Nothing interesting implemented yet.  */
524         break;
525     default:
526         hw_error("icp_control_write: Bad offset %x\n", (int)offset);
527     }
528 }
529 
530 static const MemoryRegionOps icp_control_ops = {
531     .read = icp_control_read,
532     .write = icp_control_write,
533     .endianness = DEVICE_NATIVE_ENDIAN,
534 };
535 
536 static void icp_control_mmc_wprot(void *opaque, int line, int level)
537 {
538     ICPCtrlRegsState *s = opaque;
539 
540     s->intreg_state &= ~ICP_INTREG_WPROT;
541     if (level) {
542         s->intreg_state |= ICP_INTREG_WPROT;
543     }
544 }
545 
546 static void icp_control_mmc_cardin(void *opaque, int line, int level)
547 {
548     ICPCtrlRegsState *s = opaque;
549 
550     /* line is released by writing to CP_INTREG */
551     if (level) {
552         s->intreg_state |= ICP_INTREG_CARDIN;
553         qemu_set_irq(s->mmc_irq, 1);
554     }
555 }
556 
557 static void icp_control_init(Object *obj)
558 {
559     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
560     ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj);
561     DeviceState *dev = DEVICE(obj);
562 
563     memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s,
564                           "icp_ctrl_regs", 0x00800000);
565     sysbus_init_mmio(sbd, &s->iomem);
566 
567     qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1);
568     qdev_init_gpio_in_named(dev, icp_control_mmc_cardin,
569                             ICP_GPIO_MMC_CARDIN, 1);
570     sysbus_init_irq(sbd, &s->mmc_irq);
571 }
572 
573 
574 /* Board init.  */
575 
576 static struct arm_boot_info integrator_binfo = {
577     .loader_start = 0x0,
578     .board_id = 0x113,
579 };
580 
581 static void integratorcp_init(MachineState *machine)
582 {
583     ram_addr_t ram_size = machine->ram_size;
584     const char *kernel_filename = machine->kernel_filename;
585     const char *kernel_cmdline = machine->kernel_cmdline;
586     const char *initrd_filename = machine->initrd_filename;
587     Object *cpuobj;
588     ARMCPU *cpu;
589     MemoryRegion *address_space_mem = get_system_memory();
590     MemoryRegion *ram = g_new(MemoryRegion, 1);
591     MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
592     qemu_irq pic[32];
593     DeviceState *dev, *sic, *icp;
594     int i;
595 
596     cpuobj = object_new(machine->cpu_type);
597 
598     /* By default ARM1176 CPUs have EL3 enabled.  This board does not
599      * currently support EL3 so the CPU EL3 property is disabled before
600      * realization.
601      */
602     if (object_property_find(cpuobj, "has_el3", NULL)) {
603         object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
604     }
605 
606     object_property_set_bool(cpuobj, true, "realized", &error_fatal);
607 
608     cpu = ARM_CPU(cpuobj);
609 
610     memory_region_allocate_system_memory(ram, NULL, "integrator.ram",
611                                          ram_size);
612     /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash.  */
613     /* ??? RAM should repeat to fill physical memory space.  */
614     /* SDRAM at address zero*/
615     memory_region_add_subregion(address_space_mem, 0, ram);
616     /* And again at address 0x80000000 */
617     memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size);
618     memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
619 
620     dev = qdev_create(NULL, TYPE_INTEGRATOR_CM);
621     qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
622     qdev_init_nofail(dev);
623     sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
624 
625     dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000,
626                                 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
627                                 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
628                                 NULL);
629     for (i = 0; i < 32; i++) {
630         pic[i] = qdev_get_gpio_in(dev, i);
631     }
632     sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]);
633     sysbus_create_varargs("integrator_pit", 0x13000000,
634                           pic[5], pic[6], pic[7], NULL);
635     sysbus_create_simple("pl031", 0x15000000, pic[8]);
636     pl011_create(0x16000000, pic[1], serial_hd(0));
637     pl011_create(0x17000000, pic[2], serial_hd(1));
638     icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000,
639                                qdev_get_gpio_in(sic, 3));
640     sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
641     sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
642     sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0);
643 
644     dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
645     qdev_connect_gpio_out(dev, 0,
646                           qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0));
647     qdev_connect_gpio_out(dev, 1,
648                           qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));
649 
650     if (nd_table[0].used)
651         smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
652 
653     sysbus_create_simple("pl110", 0xc0000000, pic[22]);
654 
655     integrator_binfo.ram_size = ram_size;
656     integrator_binfo.kernel_filename = kernel_filename;
657     integrator_binfo.kernel_cmdline = kernel_cmdline;
658     integrator_binfo.initrd_filename = initrd_filename;
659     arm_load_kernel(cpu, &integrator_binfo);
660 }
661 
662 static void integratorcp_machine_init(MachineClass *mc)
663 {
664     mc->desc = "ARM Integrator/CP (ARM926EJ-S)";
665     mc->init = integratorcp_init;
666     mc->ignore_memory_transaction_failures = true;
667     mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
668 }
669 
670 DEFINE_MACHINE("integratorcp", integratorcp_machine_init)
671 
672 static Property core_properties[] = {
673     DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0),
674     DEFINE_PROP_END_OF_LIST(),
675 };
676 
677 static void core_class_init(ObjectClass *klass, void *data)
678 {
679     DeviceClass *dc = DEVICE_CLASS(klass);
680 
681     dc->props = core_properties;
682     dc->realize = integratorcm_realize;
683     dc->vmsd = &vmstate_integratorcm;
684 }
685 
686 static void icp_pic_class_init(ObjectClass *klass, void *data)
687 {
688     DeviceClass *dc = DEVICE_CLASS(klass);
689 
690     dc->vmsd = &vmstate_icp_pic;
691 }
692 
693 static void icp_control_class_init(ObjectClass *klass, void *data)
694 {
695     DeviceClass *dc = DEVICE_CLASS(klass);
696 
697     dc->vmsd = &vmstate_icp_control;
698 }
699 
700 static const TypeInfo core_info = {
701     .name          = TYPE_INTEGRATOR_CM,
702     .parent        = TYPE_SYS_BUS_DEVICE,
703     .instance_size = sizeof(IntegratorCMState),
704     .instance_init = integratorcm_init,
705     .class_init    = core_class_init,
706 };
707 
708 static const TypeInfo icp_pic_info = {
709     .name          = TYPE_INTEGRATOR_PIC,
710     .parent        = TYPE_SYS_BUS_DEVICE,
711     .instance_size = sizeof(icp_pic_state),
712     .instance_init = icp_pic_init,
713     .class_init    = icp_pic_class_init,
714 };
715 
716 static const TypeInfo icp_ctrl_regs_info = {
717     .name          = TYPE_ICP_CONTROL_REGS,
718     .parent        = TYPE_SYS_BUS_DEVICE,
719     .instance_size = sizeof(ICPCtrlRegsState),
720     .instance_init = icp_control_init,
721     .class_init    = icp_control_class_init,
722 };
723 
724 static void integratorcp_register_types(void)
725 {
726     type_register_static(&icp_pic_info);
727     type_register_static(&core_info);
728     type_register_static(&icp_ctrl_regs_info);
729 }
730 
731 type_init(integratorcp_register_types)
732