1 /* 2 * ARM Integrator CP System emulation. 3 * 4 * Copyright (c) 2005-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "qemu-common.h" 13 #include "cpu.h" 14 #include "hw/sysbus.h" 15 #include "hw/boards.h" 16 #include "hw/arm/arm.h" 17 #include "hw/misc/arm_integrator_debug.h" 18 #include "hw/net/smc91c111.h" 19 #include "net/net.h" 20 #include "exec/address-spaces.h" 21 #include "sysemu/sysemu.h" 22 #include "qemu/error-report.h" 23 #include "hw/char/pl011.h" 24 25 #define TYPE_INTEGRATOR_CM "integrator_core" 26 #define INTEGRATOR_CM(obj) \ 27 OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM) 28 29 typedef struct IntegratorCMState { 30 /*< private >*/ 31 SysBusDevice parent_obj; 32 /*< public >*/ 33 34 MemoryRegion iomem; 35 uint32_t memsz; 36 MemoryRegion flash; 37 uint32_t cm_osc; 38 uint32_t cm_ctrl; 39 uint32_t cm_lock; 40 uint32_t cm_auxosc; 41 uint32_t cm_sdram; 42 uint32_t cm_init; 43 uint32_t cm_flags; 44 uint32_t cm_nvflags; 45 uint32_t cm_refcnt_offset; 46 uint32_t int_level; 47 uint32_t irq_enabled; 48 uint32_t fiq_enabled; 49 } IntegratorCMState; 50 51 static uint8_t integrator_spd[128] = { 52 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1, 53 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 54 }; 55 56 static const VMStateDescription vmstate_integratorcm = { 57 .name = "integratorcm", 58 .version_id = 1, 59 .minimum_version_id = 1, 60 .fields = (VMStateField[]) { 61 VMSTATE_UINT32(cm_osc, IntegratorCMState), 62 VMSTATE_UINT32(cm_ctrl, IntegratorCMState), 63 VMSTATE_UINT32(cm_lock, IntegratorCMState), 64 VMSTATE_UINT32(cm_auxosc, IntegratorCMState), 65 VMSTATE_UINT32(cm_sdram, IntegratorCMState), 66 VMSTATE_UINT32(cm_init, IntegratorCMState), 67 VMSTATE_UINT32(cm_flags, IntegratorCMState), 68 VMSTATE_UINT32(cm_nvflags, IntegratorCMState), 69 VMSTATE_UINT32(int_level, IntegratorCMState), 70 VMSTATE_UINT32(irq_enabled, IntegratorCMState), 71 VMSTATE_UINT32(fiq_enabled, IntegratorCMState), 72 VMSTATE_END_OF_LIST() 73 } 74 }; 75 76 static uint64_t integratorcm_read(void *opaque, hwaddr offset, 77 unsigned size) 78 { 79 IntegratorCMState *s = opaque; 80 if (offset >= 0x100 && offset < 0x200) { 81 /* CM_SPD */ 82 if (offset >= 0x180) 83 return 0; 84 return integrator_spd[offset >> 2]; 85 } 86 switch (offset >> 2) { 87 case 0: /* CM_ID */ 88 return 0x411a3001; 89 case 1: /* CM_PROC */ 90 return 0; 91 case 2: /* CM_OSC */ 92 return s->cm_osc; 93 case 3: /* CM_CTRL */ 94 return s->cm_ctrl; 95 case 4: /* CM_STAT */ 96 return 0x00100000; 97 case 5: /* CM_LOCK */ 98 if (s->cm_lock == 0xa05f) { 99 return 0x1a05f; 100 } else { 101 return s->cm_lock; 102 } 103 case 6: /* CM_LMBUSCNT */ 104 /* ??? High frequency timer. */ 105 hw_error("integratorcm_read: CM_LMBUSCNT"); 106 case 7: /* CM_AUXOSC */ 107 return s->cm_auxosc; 108 case 8: /* CM_SDRAM */ 109 return s->cm_sdram; 110 case 9: /* CM_INIT */ 111 return s->cm_init; 112 case 10: /* CM_REFCNT */ 113 /* This register, CM_REFCNT, provides a 32-bit count value. 114 * The count increments at the fixed reference clock frequency of 24MHz 115 * and can be used as a real-time counter. 116 */ 117 return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 118 1000) - s->cm_refcnt_offset; 119 case 12: /* CM_FLAGS */ 120 return s->cm_flags; 121 case 14: /* CM_NVFLAGS */ 122 return s->cm_nvflags; 123 case 16: /* CM_IRQ_STAT */ 124 return s->int_level & s->irq_enabled; 125 case 17: /* CM_IRQ_RSTAT */ 126 return s->int_level; 127 case 18: /* CM_IRQ_ENSET */ 128 return s->irq_enabled; 129 case 20: /* CM_SOFT_INTSET */ 130 return s->int_level & 1; 131 case 24: /* CM_FIQ_STAT */ 132 return s->int_level & s->fiq_enabled; 133 case 25: /* CM_FIQ_RSTAT */ 134 return s->int_level; 135 case 26: /* CM_FIQ_ENSET */ 136 return s->fiq_enabled; 137 case 32: /* CM_VOLTAGE_CTL0 */ 138 case 33: /* CM_VOLTAGE_CTL1 */ 139 case 34: /* CM_VOLTAGE_CTL2 */ 140 case 35: /* CM_VOLTAGE_CTL3 */ 141 /* ??? Voltage control unimplemented. */ 142 return 0; 143 default: 144 hw_error("integratorcm_read: Unimplemented offset 0x%x\n", 145 (int)offset); 146 return 0; 147 } 148 } 149 150 static void integratorcm_do_remap(IntegratorCMState *s) 151 { 152 /* Sync memory region state with CM_CTRL REMAP bit: 153 * bit 0 => flash at address 0; bit 1 => RAM 154 */ 155 memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4)); 156 } 157 158 static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value) 159 { 160 if (value & 8) { 161 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 162 } 163 if ((s->cm_ctrl ^ value) & 1) { 164 /* (value & 1) != 0 means the green "MISC LED" is lit. 165 * We don't have any nice place to display LEDs. printf is a bad 166 * idea because Linux uses the LED as a heartbeat and the output 167 * will swamp anything else on the terminal. 168 */ 169 } 170 /* Note that the RESET bit [3] always reads as zero */ 171 s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5); 172 integratorcm_do_remap(s); 173 } 174 175 static void integratorcm_update(IntegratorCMState *s) 176 { 177 /* ??? The CPU irq/fiq is raised when either the core module or base PIC 178 are active. */ 179 if (s->int_level & (s->irq_enabled | s->fiq_enabled)) 180 hw_error("Core module interrupt\n"); 181 } 182 183 static void integratorcm_write(void *opaque, hwaddr offset, 184 uint64_t value, unsigned size) 185 { 186 IntegratorCMState *s = opaque; 187 switch (offset >> 2) { 188 case 2: /* CM_OSC */ 189 if (s->cm_lock == 0xa05f) 190 s->cm_osc = value; 191 break; 192 case 3: /* CM_CTRL */ 193 integratorcm_set_ctrl(s, value); 194 break; 195 case 5: /* CM_LOCK */ 196 s->cm_lock = value & 0xffff; 197 break; 198 case 7: /* CM_AUXOSC */ 199 if (s->cm_lock == 0xa05f) 200 s->cm_auxosc = value; 201 break; 202 case 8: /* CM_SDRAM */ 203 s->cm_sdram = value; 204 break; 205 case 9: /* CM_INIT */ 206 /* ??? This can change the memory bus frequency. */ 207 s->cm_init = value; 208 break; 209 case 12: /* CM_FLAGSS */ 210 s->cm_flags |= value; 211 break; 212 case 13: /* CM_FLAGSC */ 213 s->cm_flags &= ~value; 214 break; 215 case 14: /* CM_NVFLAGSS */ 216 s->cm_nvflags |= value; 217 break; 218 case 15: /* CM_NVFLAGSS */ 219 s->cm_nvflags &= ~value; 220 break; 221 case 18: /* CM_IRQ_ENSET */ 222 s->irq_enabled |= value; 223 integratorcm_update(s); 224 break; 225 case 19: /* CM_IRQ_ENCLR */ 226 s->irq_enabled &= ~value; 227 integratorcm_update(s); 228 break; 229 case 20: /* CM_SOFT_INTSET */ 230 s->int_level |= (value & 1); 231 integratorcm_update(s); 232 break; 233 case 21: /* CM_SOFT_INTCLR */ 234 s->int_level &= ~(value & 1); 235 integratorcm_update(s); 236 break; 237 case 26: /* CM_FIQ_ENSET */ 238 s->fiq_enabled |= value; 239 integratorcm_update(s); 240 break; 241 case 27: /* CM_FIQ_ENCLR */ 242 s->fiq_enabled &= ~value; 243 integratorcm_update(s); 244 break; 245 case 32: /* CM_VOLTAGE_CTL0 */ 246 case 33: /* CM_VOLTAGE_CTL1 */ 247 case 34: /* CM_VOLTAGE_CTL2 */ 248 case 35: /* CM_VOLTAGE_CTL3 */ 249 /* ??? Voltage control unimplemented. */ 250 break; 251 default: 252 hw_error("integratorcm_write: Unimplemented offset 0x%x\n", 253 (int)offset); 254 break; 255 } 256 } 257 258 /* Integrator/CM control registers. */ 259 260 static const MemoryRegionOps integratorcm_ops = { 261 .read = integratorcm_read, 262 .write = integratorcm_write, 263 .endianness = DEVICE_NATIVE_ENDIAN, 264 }; 265 266 static void integratorcm_init(Object *obj) 267 { 268 IntegratorCMState *s = INTEGRATOR_CM(obj); 269 270 s->cm_osc = 0x01000048; 271 /* ??? What should the high bits of this value be? */ 272 s->cm_auxosc = 0x0007feff; 273 s->cm_sdram = 0x00011122; 274 memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); 275 s->cm_init = 0x00000112; 276 s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 277 1000); 278 279 /* ??? Save/restore. */ 280 } 281 282 static void integratorcm_realize(DeviceState *d, Error **errp) 283 { 284 IntegratorCMState *s = INTEGRATOR_CM(d); 285 SysBusDevice *dev = SYS_BUS_DEVICE(d); 286 Error *local_err = NULL; 287 288 memory_region_init_ram(&s->flash, OBJECT(d), "integrator.flash", 0x100000, 289 &local_err); 290 if (local_err) { 291 error_propagate(errp, local_err); 292 return; 293 } 294 295 memory_region_init_io(&s->iomem, OBJECT(d), &integratorcm_ops, s, 296 "integratorcm", 0x00800000); 297 sysbus_init_mmio(dev, &s->iomem); 298 299 integratorcm_do_remap(s); 300 301 if (s->memsz >= 256) { 302 integrator_spd[31] = 64; 303 s->cm_sdram |= 0x10; 304 } else if (s->memsz >= 128) { 305 integrator_spd[31] = 32; 306 s->cm_sdram |= 0x0c; 307 } else if (s->memsz >= 64) { 308 integrator_spd[31] = 16; 309 s->cm_sdram |= 0x08; 310 } else if (s->memsz >= 32) { 311 integrator_spd[31] = 4; 312 s->cm_sdram |= 0x04; 313 } else { 314 integrator_spd[31] = 2; 315 } 316 } 317 318 /* Integrator/CP hardware emulation. */ 319 /* Primary interrupt controller. */ 320 321 #define TYPE_INTEGRATOR_PIC "integrator_pic" 322 #define INTEGRATOR_PIC(obj) \ 323 OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC) 324 325 typedef struct icp_pic_state { 326 /*< private >*/ 327 SysBusDevice parent_obj; 328 /*< public >*/ 329 330 MemoryRegion iomem; 331 uint32_t level; 332 uint32_t irq_enabled; 333 uint32_t fiq_enabled; 334 qemu_irq parent_irq; 335 qemu_irq parent_fiq; 336 } icp_pic_state; 337 338 static const VMStateDescription vmstate_icp_pic = { 339 .name = "icp_pic", 340 .version_id = 1, 341 .minimum_version_id = 1, 342 .fields = (VMStateField[]) { 343 VMSTATE_UINT32(level, icp_pic_state), 344 VMSTATE_UINT32(irq_enabled, icp_pic_state), 345 VMSTATE_UINT32(fiq_enabled, icp_pic_state), 346 VMSTATE_END_OF_LIST() 347 } 348 }; 349 350 static void icp_pic_update(icp_pic_state *s) 351 { 352 uint32_t flags; 353 354 flags = (s->level & s->irq_enabled); 355 qemu_set_irq(s->parent_irq, flags != 0); 356 flags = (s->level & s->fiq_enabled); 357 qemu_set_irq(s->parent_fiq, flags != 0); 358 } 359 360 static void icp_pic_set_irq(void *opaque, int irq, int level) 361 { 362 icp_pic_state *s = (icp_pic_state *)opaque; 363 if (level) 364 s->level |= 1 << irq; 365 else 366 s->level &= ~(1 << irq); 367 icp_pic_update(s); 368 } 369 370 static uint64_t icp_pic_read(void *opaque, hwaddr offset, 371 unsigned size) 372 { 373 icp_pic_state *s = (icp_pic_state *)opaque; 374 375 switch (offset >> 2) { 376 case 0: /* IRQ_STATUS */ 377 return s->level & s->irq_enabled; 378 case 1: /* IRQ_RAWSTAT */ 379 return s->level; 380 case 2: /* IRQ_ENABLESET */ 381 return s->irq_enabled; 382 case 4: /* INT_SOFTSET */ 383 return s->level & 1; 384 case 8: /* FRQ_STATUS */ 385 return s->level & s->fiq_enabled; 386 case 9: /* FRQ_RAWSTAT */ 387 return s->level; 388 case 10: /* FRQ_ENABLESET */ 389 return s->fiq_enabled; 390 case 3: /* IRQ_ENABLECLR */ 391 case 5: /* INT_SOFTCLR */ 392 case 11: /* FRQ_ENABLECLR */ 393 default: 394 printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset); 395 return 0; 396 } 397 } 398 399 static void icp_pic_write(void *opaque, hwaddr offset, 400 uint64_t value, unsigned size) 401 { 402 icp_pic_state *s = (icp_pic_state *)opaque; 403 404 switch (offset >> 2) { 405 case 2: /* IRQ_ENABLESET */ 406 s->irq_enabled |= value; 407 break; 408 case 3: /* IRQ_ENABLECLR */ 409 s->irq_enabled &= ~value; 410 break; 411 case 4: /* INT_SOFTSET */ 412 if (value & 1) 413 icp_pic_set_irq(s, 0, 1); 414 break; 415 case 5: /* INT_SOFTCLR */ 416 if (value & 1) 417 icp_pic_set_irq(s, 0, 0); 418 break; 419 case 10: /* FRQ_ENABLESET */ 420 s->fiq_enabled |= value; 421 break; 422 case 11: /* FRQ_ENABLECLR */ 423 s->fiq_enabled &= ~value; 424 break; 425 case 0: /* IRQ_STATUS */ 426 case 1: /* IRQ_RAWSTAT */ 427 case 8: /* FRQ_STATUS */ 428 case 9: /* FRQ_RAWSTAT */ 429 default: 430 printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset); 431 return; 432 } 433 icp_pic_update(s); 434 } 435 436 static const MemoryRegionOps icp_pic_ops = { 437 .read = icp_pic_read, 438 .write = icp_pic_write, 439 .endianness = DEVICE_NATIVE_ENDIAN, 440 }; 441 442 static void icp_pic_init(Object *obj) 443 { 444 DeviceState *dev = DEVICE(obj); 445 icp_pic_state *s = INTEGRATOR_PIC(obj); 446 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 447 448 qdev_init_gpio_in(dev, icp_pic_set_irq, 32); 449 sysbus_init_irq(sbd, &s->parent_irq); 450 sysbus_init_irq(sbd, &s->parent_fiq); 451 memory_region_init_io(&s->iomem, obj, &icp_pic_ops, s, 452 "icp-pic", 0x00800000); 453 sysbus_init_mmio(sbd, &s->iomem); 454 } 455 456 /* CP control registers. */ 457 458 #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs" 459 #define ICP_CONTROL_REGS(obj) \ 460 OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS) 461 462 typedef struct ICPCtrlRegsState { 463 /*< private >*/ 464 SysBusDevice parent_obj; 465 /*< public >*/ 466 467 MemoryRegion iomem; 468 469 qemu_irq mmc_irq; 470 uint32_t intreg_state; 471 } ICPCtrlRegsState; 472 473 #define ICP_GPIO_MMC_WPROT "mmc-wprot" 474 #define ICP_GPIO_MMC_CARDIN "mmc-cardin" 475 476 #define ICP_INTREG_WPROT (1 << 0) 477 #define ICP_INTREG_CARDIN (1 << 3) 478 479 static const VMStateDescription vmstate_icp_control = { 480 .name = "icp_control", 481 .version_id = 1, 482 .minimum_version_id = 1, 483 .fields = (VMStateField[]) { 484 VMSTATE_UINT32(intreg_state, ICPCtrlRegsState), 485 VMSTATE_END_OF_LIST() 486 } 487 }; 488 489 static uint64_t icp_control_read(void *opaque, hwaddr offset, 490 unsigned size) 491 { 492 ICPCtrlRegsState *s = opaque; 493 494 switch (offset >> 2) { 495 case 0: /* CP_IDFIELD */ 496 return 0x41034003; 497 case 1: /* CP_FLASHPROG */ 498 return 0; 499 case 2: /* CP_INTREG */ 500 return s->intreg_state; 501 case 3: /* CP_DECODE */ 502 return 0x11; 503 default: 504 hw_error("icp_control_read: Bad offset %x\n", (int)offset); 505 return 0; 506 } 507 } 508 509 static void icp_control_write(void *opaque, hwaddr offset, 510 uint64_t value, unsigned size) 511 { 512 ICPCtrlRegsState *s = opaque; 513 514 switch (offset >> 2) { 515 case 2: /* CP_INTREG */ 516 s->intreg_state &= ~(value & ICP_INTREG_CARDIN); 517 qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN)); 518 break; 519 case 1: /* CP_FLASHPROG */ 520 case 3: /* CP_DECODE */ 521 /* Nothing interesting implemented yet. */ 522 break; 523 default: 524 hw_error("icp_control_write: Bad offset %x\n", (int)offset); 525 } 526 } 527 528 static const MemoryRegionOps icp_control_ops = { 529 .read = icp_control_read, 530 .write = icp_control_write, 531 .endianness = DEVICE_NATIVE_ENDIAN, 532 }; 533 534 static void icp_control_mmc_wprot(void *opaque, int line, int level) 535 { 536 ICPCtrlRegsState *s = opaque; 537 538 s->intreg_state &= ~ICP_INTREG_WPROT; 539 if (level) { 540 s->intreg_state |= ICP_INTREG_WPROT; 541 } 542 } 543 544 static void icp_control_mmc_cardin(void *opaque, int line, int level) 545 { 546 ICPCtrlRegsState *s = opaque; 547 548 /* line is released by writing to CP_INTREG */ 549 if (level) { 550 s->intreg_state |= ICP_INTREG_CARDIN; 551 qemu_set_irq(s->mmc_irq, 1); 552 } 553 } 554 555 static void icp_control_init(Object *obj) 556 { 557 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 558 ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj); 559 DeviceState *dev = DEVICE(obj); 560 561 memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s, 562 "icp_ctrl_regs", 0x00800000); 563 sysbus_init_mmio(sbd, &s->iomem); 564 565 qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1); 566 qdev_init_gpio_in_named(dev, icp_control_mmc_cardin, 567 ICP_GPIO_MMC_CARDIN, 1); 568 sysbus_init_irq(sbd, &s->mmc_irq); 569 } 570 571 572 /* Board init. */ 573 574 static struct arm_boot_info integrator_binfo = { 575 .loader_start = 0x0, 576 .board_id = 0x113, 577 }; 578 579 static void integratorcp_init(MachineState *machine) 580 { 581 ram_addr_t ram_size = machine->ram_size; 582 const char *kernel_filename = machine->kernel_filename; 583 const char *kernel_cmdline = machine->kernel_cmdline; 584 const char *initrd_filename = machine->initrd_filename; 585 Object *cpuobj; 586 ARMCPU *cpu; 587 MemoryRegion *address_space_mem = get_system_memory(); 588 MemoryRegion *ram = g_new(MemoryRegion, 1); 589 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 590 qemu_irq pic[32]; 591 DeviceState *dev, *sic, *icp; 592 int i; 593 594 cpuobj = object_new(machine->cpu_type); 595 596 /* By default ARM1176 CPUs have EL3 enabled. This board does not 597 * currently support EL3 so the CPU EL3 property is disabled before 598 * realization. 599 */ 600 if (object_property_find(cpuobj, "has_el3", NULL)) { 601 object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 602 } 603 604 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 605 606 cpu = ARM_CPU(cpuobj); 607 608 memory_region_allocate_system_memory(ram, NULL, "integrator.ram", 609 ram_size); 610 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ 611 /* ??? RAM should repeat to fill physical memory space. */ 612 /* SDRAM at address zero*/ 613 memory_region_add_subregion(address_space_mem, 0, ram); 614 /* And again at address 0x80000000 */ 615 memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size); 616 memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias); 617 618 dev = qdev_create(NULL, TYPE_INTEGRATOR_CM); 619 qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); 620 qdev_init_nofail(dev); 621 sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); 622 623 dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000, 624 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), 625 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), 626 NULL); 627 for (i = 0; i < 32; i++) { 628 pic[i] = qdev_get_gpio_in(dev, i); 629 } 630 sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]); 631 sysbus_create_varargs("integrator_pit", 0x13000000, 632 pic[5], pic[6], pic[7], NULL); 633 sysbus_create_simple("pl031", 0x15000000, pic[8]); 634 pl011_create(0x16000000, pic[1], serial_hd(0)); 635 pl011_create(0x17000000, pic[2], serial_hd(1)); 636 icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000, 637 qdev_get_gpio_in(sic, 3)); 638 sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]); 639 sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]); 640 sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0); 641 642 dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL); 643 qdev_connect_gpio_out(dev, 0, 644 qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0)); 645 qdev_connect_gpio_out(dev, 1, 646 qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0)); 647 648 if (nd_table[0].used) 649 smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); 650 651 sysbus_create_simple("pl110", 0xc0000000, pic[22]); 652 653 integrator_binfo.ram_size = ram_size; 654 integrator_binfo.kernel_filename = kernel_filename; 655 integrator_binfo.kernel_cmdline = kernel_cmdline; 656 integrator_binfo.initrd_filename = initrd_filename; 657 arm_load_kernel(cpu, &integrator_binfo); 658 } 659 660 static void integratorcp_machine_init(MachineClass *mc) 661 { 662 mc->desc = "ARM Integrator/CP (ARM926EJ-S)"; 663 mc->init = integratorcp_init; 664 mc->ignore_memory_transaction_failures = true; 665 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 666 } 667 668 DEFINE_MACHINE("integratorcp", integratorcp_machine_init) 669 670 static Property core_properties[] = { 671 DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0), 672 DEFINE_PROP_END_OF_LIST(), 673 }; 674 675 static void core_class_init(ObjectClass *klass, void *data) 676 { 677 DeviceClass *dc = DEVICE_CLASS(klass); 678 679 dc->props = core_properties; 680 dc->realize = integratorcm_realize; 681 dc->vmsd = &vmstate_integratorcm; 682 } 683 684 static void icp_pic_class_init(ObjectClass *klass, void *data) 685 { 686 DeviceClass *dc = DEVICE_CLASS(klass); 687 688 dc->vmsd = &vmstate_icp_pic; 689 } 690 691 static void icp_control_class_init(ObjectClass *klass, void *data) 692 { 693 DeviceClass *dc = DEVICE_CLASS(klass); 694 695 dc->vmsd = &vmstate_icp_control; 696 } 697 698 static const TypeInfo core_info = { 699 .name = TYPE_INTEGRATOR_CM, 700 .parent = TYPE_SYS_BUS_DEVICE, 701 .instance_size = sizeof(IntegratorCMState), 702 .instance_init = integratorcm_init, 703 .class_init = core_class_init, 704 }; 705 706 static const TypeInfo icp_pic_info = { 707 .name = TYPE_INTEGRATOR_PIC, 708 .parent = TYPE_SYS_BUS_DEVICE, 709 .instance_size = sizeof(icp_pic_state), 710 .instance_init = icp_pic_init, 711 .class_init = icp_pic_class_init, 712 }; 713 714 static const TypeInfo icp_ctrl_regs_info = { 715 .name = TYPE_ICP_CONTROL_REGS, 716 .parent = TYPE_SYS_BUS_DEVICE, 717 .instance_size = sizeof(ICPCtrlRegsState), 718 .instance_init = icp_control_init, 719 .class_init = icp_control_class_init, 720 }; 721 722 static void integratorcp_register_types(void) 723 { 724 type_register_static(&icp_pic_info); 725 type_register_static(&core_info); 726 type_register_static(&icp_ctrl_regs_info); 727 } 728 729 type_init(integratorcp_register_types) 730