1 /* 2 * ARM Integrator CP System emulation. 3 * 4 * Copyright (c) 2005-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL 8 */ 9 10 #include "hw/sysbus.h" 11 #include "hw/devices.h" 12 #include "hw/boards.h" 13 #include "hw/arm/arm.h" 14 #include "net/net.h" 15 #include "exec/address-spaces.h" 16 #include "sysemu/sysemu.h" 17 18 #define TYPE_INTEGRATOR_CM "integrator_core" 19 #define INTEGRATOR_CM(obj) \ 20 OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM) 21 22 typedef struct IntegratorCMState { 23 /*< private >*/ 24 SysBusDevice parent_obj; 25 /*< public >*/ 26 27 MemoryRegion iomem; 28 uint32_t memsz; 29 MemoryRegion flash; 30 uint32_t cm_osc; 31 uint32_t cm_ctrl; 32 uint32_t cm_lock; 33 uint32_t cm_auxosc; 34 uint32_t cm_sdram; 35 uint32_t cm_init; 36 uint32_t cm_flags; 37 uint32_t cm_nvflags; 38 uint32_t int_level; 39 uint32_t irq_enabled; 40 uint32_t fiq_enabled; 41 } IntegratorCMState; 42 43 static uint8_t integrator_spd[128] = { 44 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1, 45 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 46 }; 47 48 static uint64_t integratorcm_read(void *opaque, hwaddr offset, 49 unsigned size) 50 { 51 IntegratorCMState *s = opaque; 52 if (offset >= 0x100 && offset < 0x200) { 53 /* CM_SPD */ 54 if (offset >= 0x180) 55 return 0; 56 return integrator_spd[offset >> 2]; 57 } 58 switch (offset >> 2) { 59 case 0: /* CM_ID */ 60 return 0x411a3001; 61 case 1: /* CM_PROC */ 62 return 0; 63 case 2: /* CM_OSC */ 64 return s->cm_osc; 65 case 3: /* CM_CTRL */ 66 return s->cm_ctrl; 67 case 4: /* CM_STAT */ 68 return 0x00100000; 69 case 5: /* CM_LOCK */ 70 if (s->cm_lock == 0xa05f) { 71 return 0x1a05f; 72 } else { 73 return s->cm_lock; 74 } 75 case 6: /* CM_LMBUSCNT */ 76 /* ??? High frequency timer. */ 77 hw_error("integratorcm_read: CM_LMBUSCNT"); 78 case 7: /* CM_AUXOSC */ 79 return s->cm_auxosc; 80 case 8: /* CM_SDRAM */ 81 return s->cm_sdram; 82 case 9: /* CM_INIT */ 83 return s->cm_init; 84 case 10: /* CM_REFCT */ 85 /* ??? High frequency timer. */ 86 hw_error("integratorcm_read: CM_REFCT"); 87 case 12: /* CM_FLAGS */ 88 return s->cm_flags; 89 case 14: /* CM_NVFLAGS */ 90 return s->cm_nvflags; 91 case 16: /* CM_IRQ_STAT */ 92 return s->int_level & s->irq_enabled; 93 case 17: /* CM_IRQ_RSTAT */ 94 return s->int_level; 95 case 18: /* CM_IRQ_ENSET */ 96 return s->irq_enabled; 97 case 20: /* CM_SOFT_INTSET */ 98 return s->int_level & 1; 99 case 24: /* CM_FIQ_STAT */ 100 return s->int_level & s->fiq_enabled; 101 case 25: /* CM_FIQ_RSTAT */ 102 return s->int_level; 103 case 26: /* CM_FIQ_ENSET */ 104 return s->fiq_enabled; 105 case 32: /* CM_VOLTAGE_CTL0 */ 106 case 33: /* CM_VOLTAGE_CTL1 */ 107 case 34: /* CM_VOLTAGE_CTL2 */ 108 case 35: /* CM_VOLTAGE_CTL3 */ 109 /* ??? Voltage control unimplemented. */ 110 return 0; 111 default: 112 hw_error("integratorcm_read: Unimplemented offset 0x%x\n", 113 (int)offset); 114 return 0; 115 } 116 } 117 118 static void integratorcm_do_remap(IntegratorCMState *s) 119 { 120 /* Sync memory region state with CM_CTRL REMAP bit: 121 * bit 0 => flash at address 0; bit 1 => RAM 122 */ 123 memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4)); 124 } 125 126 static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value) 127 { 128 if (value & 8) { 129 qemu_system_reset_request(); 130 } 131 if ((s->cm_ctrl ^ value) & 1) { 132 /* (value & 1) != 0 means the green "MISC LED" is lit. 133 * We don't have any nice place to display LEDs. printf is a bad 134 * idea because Linux uses the LED as a heartbeat and the output 135 * will swamp anything else on the terminal. 136 */ 137 } 138 /* Note that the RESET bit [3] always reads as zero */ 139 s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5); 140 integratorcm_do_remap(s); 141 } 142 143 static void integratorcm_update(IntegratorCMState *s) 144 { 145 /* ??? The CPU irq/fiq is raised when either the core module or base PIC 146 are active. */ 147 if (s->int_level & (s->irq_enabled | s->fiq_enabled)) 148 hw_error("Core module interrupt\n"); 149 } 150 151 static void integratorcm_write(void *opaque, hwaddr offset, 152 uint64_t value, unsigned size) 153 { 154 IntegratorCMState *s = opaque; 155 switch (offset >> 2) { 156 case 2: /* CM_OSC */ 157 if (s->cm_lock == 0xa05f) 158 s->cm_osc = value; 159 break; 160 case 3: /* CM_CTRL */ 161 integratorcm_set_ctrl(s, value); 162 break; 163 case 5: /* CM_LOCK */ 164 s->cm_lock = value & 0xffff; 165 break; 166 case 7: /* CM_AUXOSC */ 167 if (s->cm_lock == 0xa05f) 168 s->cm_auxosc = value; 169 break; 170 case 8: /* CM_SDRAM */ 171 s->cm_sdram = value; 172 break; 173 case 9: /* CM_INIT */ 174 /* ??? This can change the memory bus frequency. */ 175 s->cm_init = value; 176 break; 177 case 12: /* CM_FLAGSS */ 178 s->cm_flags |= value; 179 break; 180 case 13: /* CM_FLAGSC */ 181 s->cm_flags &= ~value; 182 break; 183 case 14: /* CM_NVFLAGSS */ 184 s->cm_nvflags |= value; 185 break; 186 case 15: /* CM_NVFLAGSS */ 187 s->cm_nvflags &= ~value; 188 break; 189 case 18: /* CM_IRQ_ENSET */ 190 s->irq_enabled |= value; 191 integratorcm_update(s); 192 break; 193 case 19: /* CM_IRQ_ENCLR */ 194 s->irq_enabled &= ~value; 195 integratorcm_update(s); 196 break; 197 case 20: /* CM_SOFT_INTSET */ 198 s->int_level |= (value & 1); 199 integratorcm_update(s); 200 break; 201 case 21: /* CM_SOFT_INTCLR */ 202 s->int_level &= ~(value & 1); 203 integratorcm_update(s); 204 break; 205 case 26: /* CM_FIQ_ENSET */ 206 s->fiq_enabled |= value; 207 integratorcm_update(s); 208 break; 209 case 27: /* CM_FIQ_ENCLR */ 210 s->fiq_enabled &= ~value; 211 integratorcm_update(s); 212 break; 213 case 32: /* CM_VOLTAGE_CTL0 */ 214 case 33: /* CM_VOLTAGE_CTL1 */ 215 case 34: /* CM_VOLTAGE_CTL2 */ 216 case 35: /* CM_VOLTAGE_CTL3 */ 217 /* ??? Voltage control unimplemented. */ 218 break; 219 default: 220 hw_error("integratorcm_write: Unimplemented offset 0x%x\n", 221 (int)offset); 222 break; 223 } 224 } 225 226 /* Integrator/CM control registers. */ 227 228 static const MemoryRegionOps integratorcm_ops = { 229 .read = integratorcm_read, 230 .write = integratorcm_write, 231 .endianness = DEVICE_NATIVE_ENDIAN, 232 }; 233 234 static int integratorcm_init(SysBusDevice *dev) 235 { 236 IntegratorCMState *s = INTEGRATOR_CM(dev); 237 238 s->cm_osc = 0x01000048; 239 /* ??? What should the high bits of this value be? */ 240 s->cm_auxosc = 0x0007feff; 241 s->cm_sdram = 0x00011122; 242 if (s->memsz >= 256) { 243 integrator_spd[31] = 64; 244 s->cm_sdram |= 0x10; 245 } else if (s->memsz >= 128) { 246 integrator_spd[31] = 32; 247 s->cm_sdram |= 0x0c; 248 } else if (s->memsz >= 64) { 249 integrator_spd[31] = 16; 250 s->cm_sdram |= 0x08; 251 } else if (s->memsz >= 32) { 252 integrator_spd[31] = 4; 253 s->cm_sdram |= 0x04; 254 } else { 255 integrator_spd[31] = 2; 256 } 257 memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); 258 s->cm_init = 0x00000112; 259 memory_region_init_ram(&s->flash, OBJECT(s), "integrator.flash", 0x100000); 260 vmstate_register_ram_global(&s->flash); 261 262 memory_region_init_io(&s->iomem, OBJECT(s), &integratorcm_ops, s, 263 "integratorcm", 0x00800000); 264 sysbus_init_mmio(dev, &s->iomem); 265 266 integratorcm_do_remap(s); 267 /* ??? Save/restore. */ 268 return 0; 269 } 270 271 /* Integrator/CP hardware emulation. */ 272 /* Primary interrupt controller. */ 273 274 #define TYPE_INTEGRATOR_PIC "integrator_pic" 275 #define INTEGRATOR_PIC(obj) \ 276 OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC) 277 278 typedef struct icp_pic_state { 279 /*< private >*/ 280 SysBusDevice parent_obj; 281 /*< public >*/ 282 283 MemoryRegion iomem; 284 uint32_t level; 285 uint32_t irq_enabled; 286 uint32_t fiq_enabled; 287 qemu_irq parent_irq; 288 qemu_irq parent_fiq; 289 } icp_pic_state; 290 291 static void icp_pic_update(icp_pic_state *s) 292 { 293 uint32_t flags; 294 295 flags = (s->level & s->irq_enabled); 296 qemu_set_irq(s->parent_irq, flags != 0); 297 flags = (s->level & s->fiq_enabled); 298 qemu_set_irq(s->parent_fiq, flags != 0); 299 } 300 301 static void icp_pic_set_irq(void *opaque, int irq, int level) 302 { 303 icp_pic_state *s = (icp_pic_state *)opaque; 304 if (level) 305 s->level |= 1 << irq; 306 else 307 s->level &= ~(1 << irq); 308 icp_pic_update(s); 309 } 310 311 static uint64_t icp_pic_read(void *opaque, hwaddr offset, 312 unsigned size) 313 { 314 icp_pic_state *s = (icp_pic_state *)opaque; 315 316 switch (offset >> 2) { 317 case 0: /* IRQ_STATUS */ 318 return s->level & s->irq_enabled; 319 case 1: /* IRQ_RAWSTAT */ 320 return s->level; 321 case 2: /* IRQ_ENABLESET */ 322 return s->irq_enabled; 323 case 4: /* INT_SOFTSET */ 324 return s->level & 1; 325 case 8: /* FRQ_STATUS */ 326 return s->level & s->fiq_enabled; 327 case 9: /* FRQ_RAWSTAT */ 328 return s->level; 329 case 10: /* FRQ_ENABLESET */ 330 return s->fiq_enabled; 331 case 3: /* IRQ_ENABLECLR */ 332 case 5: /* INT_SOFTCLR */ 333 case 11: /* FRQ_ENABLECLR */ 334 default: 335 printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset); 336 return 0; 337 } 338 } 339 340 static void icp_pic_write(void *opaque, hwaddr offset, 341 uint64_t value, unsigned size) 342 { 343 icp_pic_state *s = (icp_pic_state *)opaque; 344 345 switch (offset >> 2) { 346 case 2: /* IRQ_ENABLESET */ 347 s->irq_enabled |= value; 348 break; 349 case 3: /* IRQ_ENABLECLR */ 350 s->irq_enabled &= ~value; 351 break; 352 case 4: /* INT_SOFTSET */ 353 if (value & 1) 354 icp_pic_set_irq(s, 0, 1); 355 break; 356 case 5: /* INT_SOFTCLR */ 357 if (value & 1) 358 icp_pic_set_irq(s, 0, 0); 359 break; 360 case 10: /* FRQ_ENABLESET */ 361 s->fiq_enabled |= value; 362 break; 363 case 11: /* FRQ_ENABLECLR */ 364 s->fiq_enabled &= ~value; 365 break; 366 case 0: /* IRQ_STATUS */ 367 case 1: /* IRQ_RAWSTAT */ 368 case 8: /* FRQ_STATUS */ 369 case 9: /* FRQ_RAWSTAT */ 370 default: 371 printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset); 372 return; 373 } 374 icp_pic_update(s); 375 } 376 377 static const MemoryRegionOps icp_pic_ops = { 378 .read = icp_pic_read, 379 .write = icp_pic_write, 380 .endianness = DEVICE_NATIVE_ENDIAN, 381 }; 382 383 static int icp_pic_init(SysBusDevice *sbd) 384 { 385 DeviceState *dev = DEVICE(sbd); 386 icp_pic_state *s = INTEGRATOR_PIC(dev); 387 388 qdev_init_gpio_in(dev, icp_pic_set_irq, 32); 389 sysbus_init_irq(sbd, &s->parent_irq); 390 sysbus_init_irq(sbd, &s->parent_fiq); 391 memory_region_init_io(&s->iomem, OBJECT(s), &icp_pic_ops, s, 392 "icp-pic", 0x00800000); 393 sysbus_init_mmio(sbd, &s->iomem); 394 return 0; 395 } 396 397 /* CP control registers. */ 398 399 static uint64_t icp_control_read(void *opaque, hwaddr offset, 400 unsigned size) 401 { 402 switch (offset >> 2) { 403 case 0: /* CP_IDFIELD */ 404 return 0x41034003; 405 case 1: /* CP_FLASHPROG */ 406 return 0; 407 case 2: /* CP_INTREG */ 408 return 0; 409 case 3: /* CP_DECODE */ 410 return 0x11; 411 default: 412 hw_error("icp_control_read: Bad offset %x\n", (int)offset); 413 return 0; 414 } 415 } 416 417 static void icp_control_write(void *opaque, hwaddr offset, 418 uint64_t value, unsigned size) 419 { 420 switch (offset >> 2) { 421 case 1: /* CP_FLASHPROG */ 422 case 2: /* CP_INTREG */ 423 case 3: /* CP_DECODE */ 424 /* Nothing interesting implemented yet. */ 425 break; 426 default: 427 hw_error("icp_control_write: Bad offset %x\n", (int)offset); 428 } 429 } 430 431 static const MemoryRegionOps icp_control_ops = { 432 .read = icp_control_read, 433 .write = icp_control_write, 434 .endianness = DEVICE_NATIVE_ENDIAN, 435 }; 436 437 static void icp_control_init(hwaddr base) 438 { 439 MemoryRegion *io; 440 441 io = (MemoryRegion *)g_malloc0(sizeof(MemoryRegion)); 442 memory_region_init_io(io, NULL, &icp_control_ops, NULL, 443 "control", 0x00800000); 444 memory_region_add_subregion(get_system_memory(), base, io); 445 /* ??? Save/restore. */ 446 } 447 448 449 /* Board init. */ 450 451 static struct arm_boot_info integrator_binfo = { 452 .loader_start = 0x0, 453 .board_id = 0x113, 454 }; 455 456 static void integratorcp_init(QEMUMachineInitArgs *args) 457 { 458 ram_addr_t ram_size = args->ram_size; 459 const char *cpu_model = args->cpu_model; 460 const char *kernel_filename = args->kernel_filename; 461 const char *kernel_cmdline = args->kernel_cmdline; 462 const char *initrd_filename = args->initrd_filename; 463 ARMCPU *cpu; 464 MemoryRegion *address_space_mem = get_system_memory(); 465 MemoryRegion *ram = g_new(MemoryRegion, 1); 466 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 467 qemu_irq pic[32]; 468 qemu_irq *cpu_pic; 469 DeviceState *dev; 470 int i; 471 472 if (!cpu_model) { 473 cpu_model = "arm926"; 474 } 475 cpu = cpu_arm_init(cpu_model); 476 if (!cpu) { 477 fprintf(stderr, "Unable to find CPU definition\n"); 478 exit(1); 479 } 480 481 memory_region_init_ram(ram, NULL, "integrator.ram", ram_size); 482 vmstate_register_ram_global(ram); 483 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ 484 /* ??? RAM should repeat to fill physical memory space. */ 485 /* SDRAM at address zero*/ 486 memory_region_add_subregion(address_space_mem, 0, ram); 487 /* And again at address 0x80000000 */ 488 memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size); 489 memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias); 490 491 dev = qdev_create(NULL, TYPE_INTEGRATOR_CM); 492 qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); 493 qdev_init_nofail(dev); 494 sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); 495 496 cpu_pic = arm_pic_init_cpu(cpu); 497 dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000, 498 cpu_pic[ARM_PIC_CPU_IRQ], 499 cpu_pic[ARM_PIC_CPU_FIQ], NULL); 500 for (i = 0; i < 32; i++) { 501 pic[i] = qdev_get_gpio_in(dev, i); 502 } 503 sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]); 504 sysbus_create_varargs("integrator_pit", 0x13000000, 505 pic[5], pic[6], pic[7], NULL); 506 sysbus_create_simple("pl031", 0x15000000, pic[8]); 507 sysbus_create_simple("pl011", 0x16000000, pic[1]); 508 sysbus_create_simple("pl011", 0x17000000, pic[2]); 509 icp_control_init(0xcb000000); 510 sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]); 511 sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]); 512 sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL); 513 if (nd_table[0].used) 514 smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); 515 516 sysbus_create_simple("pl110", 0xc0000000, pic[22]); 517 518 integrator_binfo.ram_size = ram_size; 519 integrator_binfo.kernel_filename = kernel_filename; 520 integrator_binfo.kernel_cmdline = kernel_cmdline; 521 integrator_binfo.initrd_filename = initrd_filename; 522 arm_load_kernel(cpu, &integrator_binfo); 523 } 524 525 static QEMUMachine integratorcp_machine = { 526 .name = "integratorcp", 527 .desc = "ARM Integrator/CP (ARM926EJ-S)", 528 .init = integratorcp_init, 529 .is_default = 1, 530 DEFAULT_MACHINE_OPTIONS, 531 }; 532 533 static void integratorcp_machine_init(void) 534 { 535 qemu_register_machine(&integratorcp_machine); 536 } 537 538 machine_init(integratorcp_machine_init); 539 540 static Property core_properties[] = { 541 DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0), 542 DEFINE_PROP_END_OF_LIST(), 543 }; 544 545 static void core_class_init(ObjectClass *klass, void *data) 546 { 547 DeviceClass *dc = DEVICE_CLASS(klass); 548 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 549 550 k->init = integratorcm_init; 551 dc->props = core_properties; 552 } 553 554 static const TypeInfo core_info = { 555 .name = TYPE_INTEGRATOR_CM, 556 .parent = TYPE_SYS_BUS_DEVICE, 557 .instance_size = sizeof(IntegratorCMState), 558 .class_init = core_class_init, 559 }; 560 561 static void icp_pic_class_init(ObjectClass *klass, void *data) 562 { 563 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 564 565 sdc->init = icp_pic_init; 566 } 567 568 static const TypeInfo icp_pic_info = { 569 .name = TYPE_INTEGRATOR_PIC, 570 .parent = TYPE_SYS_BUS_DEVICE, 571 .instance_size = sizeof(icp_pic_state), 572 .class_init = icp_pic_class_init, 573 }; 574 575 static void integratorcp_register_types(void) 576 { 577 type_register_static(&icp_pic_info); 578 type_register_static(&core_info); 579 } 580 581 type_init(integratorcp_register_types) 582