1 /* 2 * ARM Integrator CP System emulation. 3 * 4 * Copyright (c) 2005-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "cpu.h" 13 #include "hw/sysbus.h" 14 #include "migration/vmstate.h" 15 #include "hw/boards.h" 16 #include "hw/arm/boot.h" 17 #include "hw/misc/arm_integrator_debug.h" 18 #include "hw/net/smc91c111.h" 19 #include "net/net.h" 20 #include "exec/address-spaces.h" 21 #include "sysemu/runstate.h" 22 #include "sysemu/sysemu.h" 23 #include "qemu/log.h" 24 #include "qemu/error-report.h" 25 #include "hw/char/pl011.h" 26 #include "hw/hw.h" 27 #include "hw/irq.h" 28 #include "hw/sd/sd.h" 29 30 #define TYPE_INTEGRATOR_CM "integrator_core" 31 #define INTEGRATOR_CM(obj) \ 32 OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM) 33 34 typedef struct IntegratorCMState { 35 /*< private >*/ 36 SysBusDevice parent_obj; 37 /*< public >*/ 38 39 MemoryRegion iomem; 40 uint32_t memsz; 41 MemoryRegion flash; 42 uint32_t cm_osc; 43 uint32_t cm_ctrl; 44 uint32_t cm_lock; 45 uint32_t cm_auxosc; 46 uint32_t cm_sdram; 47 uint32_t cm_init; 48 uint32_t cm_flags; 49 uint32_t cm_nvflags; 50 uint32_t cm_refcnt_offset; 51 uint32_t int_level; 52 uint32_t irq_enabled; 53 uint32_t fiq_enabled; 54 } IntegratorCMState; 55 56 static uint8_t integrator_spd[128] = { 57 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1, 58 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 59 }; 60 61 static const VMStateDescription vmstate_integratorcm = { 62 .name = "integratorcm", 63 .version_id = 1, 64 .minimum_version_id = 1, 65 .fields = (VMStateField[]) { 66 VMSTATE_UINT32(cm_osc, IntegratorCMState), 67 VMSTATE_UINT32(cm_ctrl, IntegratorCMState), 68 VMSTATE_UINT32(cm_lock, IntegratorCMState), 69 VMSTATE_UINT32(cm_auxosc, IntegratorCMState), 70 VMSTATE_UINT32(cm_sdram, IntegratorCMState), 71 VMSTATE_UINT32(cm_init, IntegratorCMState), 72 VMSTATE_UINT32(cm_flags, IntegratorCMState), 73 VMSTATE_UINT32(cm_nvflags, IntegratorCMState), 74 VMSTATE_UINT32(int_level, IntegratorCMState), 75 VMSTATE_UINT32(irq_enabled, IntegratorCMState), 76 VMSTATE_UINT32(fiq_enabled, IntegratorCMState), 77 VMSTATE_END_OF_LIST() 78 } 79 }; 80 81 static uint64_t integratorcm_read(void *opaque, hwaddr offset, 82 unsigned size) 83 { 84 IntegratorCMState *s = opaque; 85 if (offset >= 0x100 && offset < 0x200) { 86 /* CM_SPD */ 87 if (offset >= 0x180) 88 return 0; 89 return integrator_spd[offset >> 2]; 90 } 91 switch (offset >> 2) { 92 case 0: /* CM_ID */ 93 return 0x411a3001; 94 case 1: /* CM_PROC */ 95 return 0; 96 case 2: /* CM_OSC */ 97 return s->cm_osc; 98 case 3: /* CM_CTRL */ 99 return s->cm_ctrl; 100 case 4: /* CM_STAT */ 101 return 0x00100000; 102 case 5: /* CM_LOCK */ 103 if (s->cm_lock == 0xa05f) { 104 return 0x1a05f; 105 } else { 106 return s->cm_lock; 107 } 108 case 6: /* CM_LMBUSCNT */ 109 /* ??? High frequency timer. */ 110 hw_error("integratorcm_read: CM_LMBUSCNT"); 111 case 7: /* CM_AUXOSC */ 112 return s->cm_auxosc; 113 case 8: /* CM_SDRAM */ 114 return s->cm_sdram; 115 case 9: /* CM_INIT */ 116 return s->cm_init; 117 case 10: /* CM_REFCNT */ 118 /* This register, CM_REFCNT, provides a 32-bit count value. 119 * The count increments at the fixed reference clock frequency of 24MHz 120 * and can be used as a real-time counter. 121 */ 122 return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 123 1000) - s->cm_refcnt_offset; 124 case 12: /* CM_FLAGS */ 125 return s->cm_flags; 126 case 14: /* CM_NVFLAGS */ 127 return s->cm_nvflags; 128 case 16: /* CM_IRQ_STAT */ 129 return s->int_level & s->irq_enabled; 130 case 17: /* CM_IRQ_RSTAT */ 131 return s->int_level; 132 case 18: /* CM_IRQ_ENSET */ 133 return s->irq_enabled; 134 case 20: /* CM_SOFT_INTSET */ 135 return s->int_level & 1; 136 case 24: /* CM_FIQ_STAT */ 137 return s->int_level & s->fiq_enabled; 138 case 25: /* CM_FIQ_RSTAT */ 139 return s->int_level; 140 case 26: /* CM_FIQ_ENSET */ 141 return s->fiq_enabled; 142 case 32: /* CM_VOLTAGE_CTL0 */ 143 case 33: /* CM_VOLTAGE_CTL1 */ 144 case 34: /* CM_VOLTAGE_CTL2 */ 145 case 35: /* CM_VOLTAGE_CTL3 */ 146 /* ??? Voltage control unimplemented. */ 147 return 0; 148 default: 149 qemu_log_mask(LOG_UNIMP, 150 "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n", 151 __func__, offset); 152 return 0; 153 } 154 } 155 156 static void integratorcm_do_remap(IntegratorCMState *s) 157 { 158 /* Sync memory region state with CM_CTRL REMAP bit: 159 * bit 0 => flash at address 0; bit 1 => RAM 160 */ 161 memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4)); 162 } 163 164 static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value) 165 { 166 if (value & 8) { 167 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 168 } 169 if ((s->cm_ctrl ^ value) & 1) { 170 /* (value & 1) != 0 means the green "MISC LED" is lit. 171 * We don't have any nice place to display LEDs. printf is a bad 172 * idea because Linux uses the LED as a heartbeat and the output 173 * will swamp anything else on the terminal. 174 */ 175 } 176 /* Note that the RESET bit [3] always reads as zero */ 177 s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5); 178 integratorcm_do_remap(s); 179 } 180 181 static void integratorcm_update(IntegratorCMState *s) 182 { 183 /* ??? The CPU irq/fiq is raised when either the core module or base PIC 184 are active. */ 185 if (s->int_level & (s->irq_enabled | s->fiq_enabled)) 186 hw_error("Core module interrupt\n"); 187 } 188 189 static void integratorcm_write(void *opaque, hwaddr offset, 190 uint64_t value, unsigned size) 191 { 192 IntegratorCMState *s = opaque; 193 switch (offset >> 2) { 194 case 2: /* CM_OSC */ 195 if (s->cm_lock == 0xa05f) 196 s->cm_osc = value; 197 break; 198 case 3: /* CM_CTRL */ 199 integratorcm_set_ctrl(s, value); 200 break; 201 case 5: /* CM_LOCK */ 202 s->cm_lock = value & 0xffff; 203 break; 204 case 7: /* CM_AUXOSC */ 205 if (s->cm_lock == 0xa05f) 206 s->cm_auxosc = value; 207 break; 208 case 8: /* CM_SDRAM */ 209 s->cm_sdram = value; 210 break; 211 case 9: /* CM_INIT */ 212 /* ??? This can change the memory bus frequency. */ 213 s->cm_init = value; 214 break; 215 case 12: /* CM_FLAGSS */ 216 s->cm_flags |= value; 217 break; 218 case 13: /* CM_FLAGSC */ 219 s->cm_flags &= ~value; 220 break; 221 case 14: /* CM_NVFLAGSS */ 222 s->cm_nvflags |= value; 223 break; 224 case 15: /* CM_NVFLAGSS */ 225 s->cm_nvflags &= ~value; 226 break; 227 case 18: /* CM_IRQ_ENSET */ 228 s->irq_enabled |= value; 229 integratorcm_update(s); 230 break; 231 case 19: /* CM_IRQ_ENCLR */ 232 s->irq_enabled &= ~value; 233 integratorcm_update(s); 234 break; 235 case 20: /* CM_SOFT_INTSET */ 236 s->int_level |= (value & 1); 237 integratorcm_update(s); 238 break; 239 case 21: /* CM_SOFT_INTCLR */ 240 s->int_level &= ~(value & 1); 241 integratorcm_update(s); 242 break; 243 case 26: /* CM_FIQ_ENSET */ 244 s->fiq_enabled |= value; 245 integratorcm_update(s); 246 break; 247 case 27: /* CM_FIQ_ENCLR */ 248 s->fiq_enabled &= ~value; 249 integratorcm_update(s); 250 break; 251 case 32: /* CM_VOLTAGE_CTL0 */ 252 case 33: /* CM_VOLTAGE_CTL1 */ 253 case 34: /* CM_VOLTAGE_CTL2 */ 254 case 35: /* CM_VOLTAGE_CTL3 */ 255 /* ??? Voltage control unimplemented. */ 256 break; 257 default: 258 qemu_log_mask(LOG_UNIMP, 259 "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n", 260 __func__, offset); 261 break; 262 } 263 } 264 265 /* Integrator/CM control registers. */ 266 267 static const MemoryRegionOps integratorcm_ops = { 268 .read = integratorcm_read, 269 .write = integratorcm_write, 270 .endianness = DEVICE_NATIVE_ENDIAN, 271 }; 272 273 static void integratorcm_init(Object *obj) 274 { 275 IntegratorCMState *s = INTEGRATOR_CM(obj); 276 277 s->cm_osc = 0x01000048; 278 /* ??? What should the high bits of this value be? */ 279 s->cm_auxosc = 0x0007feff; 280 s->cm_sdram = 0x00011122; 281 memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); 282 s->cm_init = 0x00000112; 283 s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 284 1000); 285 286 /* ??? Save/restore. */ 287 } 288 289 static void integratorcm_realize(DeviceState *d, Error **errp) 290 { 291 IntegratorCMState *s = INTEGRATOR_CM(d); 292 SysBusDevice *dev = SYS_BUS_DEVICE(d); 293 Error *local_err = NULL; 294 295 memory_region_init_ram(&s->flash, OBJECT(d), "integrator.flash", 0x100000, 296 &local_err); 297 if (local_err) { 298 error_propagate(errp, local_err); 299 return; 300 } 301 302 memory_region_init_io(&s->iomem, OBJECT(d), &integratorcm_ops, s, 303 "integratorcm", 0x00800000); 304 sysbus_init_mmio(dev, &s->iomem); 305 306 integratorcm_do_remap(s); 307 308 if (s->memsz >= 256) { 309 integrator_spd[31] = 64; 310 s->cm_sdram |= 0x10; 311 } else if (s->memsz >= 128) { 312 integrator_spd[31] = 32; 313 s->cm_sdram |= 0x0c; 314 } else if (s->memsz >= 64) { 315 integrator_spd[31] = 16; 316 s->cm_sdram |= 0x08; 317 } else if (s->memsz >= 32) { 318 integrator_spd[31] = 4; 319 s->cm_sdram |= 0x04; 320 } else { 321 integrator_spd[31] = 2; 322 } 323 } 324 325 /* Integrator/CP hardware emulation. */ 326 /* Primary interrupt controller. */ 327 328 #define TYPE_INTEGRATOR_PIC "integrator_pic" 329 #define INTEGRATOR_PIC(obj) \ 330 OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC) 331 332 typedef struct icp_pic_state { 333 /*< private >*/ 334 SysBusDevice parent_obj; 335 /*< public >*/ 336 337 MemoryRegion iomem; 338 uint32_t level; 339 uint32_t irq_enabled; 340 uint32_t fiq_enabled; 341 qemu_irq parent_irq; 342 qemu_irq parent_fiq; 343 } icp_pic_state; 344 345 static const VMStateDescription vmstate_icp_pic = { 346 .name = "icp_pic", 347 .version_id = 1, 348 .minimum_version_id = 1, 349 .fields = (VMStateField[]) { 350 VMSTATE_UINT32(level, icp_pic_state), 351 VMSTATE_UINT32(irq_enabled, icp_pic_state), 352 VMSTATE_UINT32(fiq_enabled, icp_pic_state), 353 VMSTATE_END_OF_LIST() 354 } 355 }; 356 357 static void icp_pic_update(icp_pic_state *s) 358 { 359 uint32_t flags; 360 361 flags = (s->level & s->irq_enabled); 362 qemu_set_irq(s->parent_irq, flags != 0); 363 flags = (s->level & s->fiq_enabled); 364 qemu_set_irq(s->parent_fiq, flags != 0); 365 } 366 367 static void icp_pic_set_irq(void *opaque, int irq, int level) 368 { 369 icp_pic_state *s = (icp_pic_state *)opaque; 370 if (level) 371 s->level |= 1 << irq; 372 else 373 s->level &= ~(1 << irq); 374 icp_pic_update(s); 375 } 376 377 static uint64_t icp_pic_read(void *opaque, hwaddr offset, 378 unsigned size) 379 { 380 icp_pic_state *s = (icp_pic_state *)opaque; 381 382 switch (offset >> 2) { 383 case 0: /* IRQ_STATUS */ 384 return s->level & s->irq_enabled; 385 case 1: /* IRQ_RAWSTAT */ 386 return s->level; 387 case 2: /* IRQ_ENABLESET */ 388 return s->irq_enabled; 389 case 4: /* INT_SOFTSET */ 390 return s->level & 1; 391 case 8: /* FRQ_STATUS */ 392 return s->level & s->fiq_enabled; 393 case 9: /* FRQ_RAWSTAT */ 394 return s->level; 395 case 10: /* FRQ_ENABLESET */ 396 return s->fiq_enabled; 397 case 3: /* IRQ_ENABLECLR */ 398 case 5: /* INT_SOFTCLR */ 399 case 11: /* FRQ_ENABLECLR */ 400 default: 401 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 402 __func__, offset); 403 return 0; 404 } 405 } 406 407 static void icp_pic_write(void *opaque, hwaddr offset, 408 uint64_t value, unsigned size) 409 { 410 icp_pic_state *s = (icp_pic_state *)opaque; 411 412 switch (offset >> 2) { 413 case 2: /* IRQ_ENABLESET */ 414 s->irq_enabled |= value; 415 break; 416 case 3: /* IRQ_ENABLECLR */ 417 s->irq_enabled &= ~value; 418 break; 419 case 4: /* INT_SOFTSET */ 420 if (value & 1) 421 icp_pic_set_irq(s, 0, 1); 422 break; 423 case 5: /* INT_SOFTCLR */ 424 if (value & 1) 425 icp_pic_set_irq(s, 0, 0); 426 break; 427 case 10: /* FRQ_ENABLESET */ 428 s->fiq_enabled |= value; 429 break; 430 case 11: /* FRQ_ENABLECLR */ 431 s->fiq_enabled &= ~value; 432 break; 433 case 0: /* IRQ_STATUS */ 434 case 1: /* IRQ_RAWSTAT */ 435 case 8: /* FRQ_STATUS */ 436 case 9: /* FRQ_RAWSTAT */ 437 default: 438 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 439 __func__, offset); 440 return; 441 } 442 icp_pic_update(s); 443 } 444 445 static const MemoryRegionOps icp_pic_ops = { 446 .read = icp_pic_read, 447 .write = icp_pic_write, 448 .endianness = DEVICE_NATIVE_ENDIAN, 449 }; 450 451 static void icp_pic_init(Object *obj) 452 { 453 DeviceState *dev = DEVICE(obj); 454 icp_pic_state *s = INTEGRATOR_PIC(obj); 455 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 456 457 qdev_init_gpio_in(dev, icp_pic_set_irq, 32); 458 sysbus_init_irq(sbd, &s->parent_irq); 459 sysbus_init_irq(sbd, &s->parent_fiq); 460 memory_region_init_io(&s->iomem, obj, &icp_pic_ops, s, 461 "icp-pic", 0x00800000); 462 sysbus_init_mmio(sbd, &s->iomem); 463 } 464 465 /* CP control registers. */ 466 467 #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs" 468 #define ICP_CONTROL_REGS(obj) \ 469 OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS) 470 471 typedef struct ICPCtrlRegsState { 472 /*< private >*/ 473 SysBusDevice parent_obj; 474 /*< public >*/ 475 476 MemoryRegion iomem; 477 478 qemu_irq mmc_irq; 479 uint32_t intreg_state; 480 } ICPCtrlRegsState; 481 482 #define ICP_GPIO_MMC_WPROT "mmc-wprot" 483 #define ICP_GPIO_MMC_CARDIN "mmc-cardin" 484 485 #define ICP_INTREG_WPROT (1 << 0) 486 #define ICP_INTREG_CARDIN (1 << 3) 487 488 static const VMStateDescription vmstate_icp_control = { 489 .name = "icp_control", 490 .version_id = 1, 491 .minimum_version_id = 1, 492 .fields = (VMStateField[]) { 493 VMSTATE_UINT32(intreg_state, ICPCtrlRegsState), 494 VMSTATE_END_OF_LIST() 495 } 496 }; 497 498 static uint64_t icp_control_read(void *opaque, hwaddr offset, 499 unsigned size) 500 { 501 ICPCtrlRegsState *s = opaque; 502 503 switch (offset >> 2) { 504 case 0: /* CP_IDFIELD */ 505 return 0x41034003; 506 case 1: /* CP_FLASHPROG */ 507 return 0; 508 case 2: /* CP_INTREG */ 509 return s->intreg_state; 510 case 3: /* CP_DECODE */ 511 return 0x11; 512 default: 513 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 514 __func__, offset); 515 return 0; 516 } 517 } 518 519 static void icp_control_write(void *opaque, hwaddr offset, 520 uint64_t value, unsigned size) 521 { 522 ICPCtrlRegsState *s = opaque; 523 524 switch (offset >> 2) { 525 case 2: /* CP_INTREG */ 526 s->intreg_state &= ~(value & ICP_INTREG_CARDIN); 527 qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN)); 528 break; 529 case 1: /* CP_FLASHPROG */ 530 case 3: /* CP_DECODE */ 531 /* Nothing interesting implemented yet. */ 532 break; 533 default: 534 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 535 __func__, offset); 536 } 537 } 538 539 static const MemoryRegionOps icp_control_ops = { 540 .read = icp_control_read, 541 .write = icp_control_write, 542 .endianness = DEVICE_NATIVE_ENDIAN, 543 }; 544 545 static void icp_control_mmc_wprot(void *opaque, int line, int level) 546 { 547 ICPCtrlRegsState *s = opaque; 548 549 s->intreg_state &= ~ICP_INTREG_WPROT; 550 if (level) { 551 s->intreg_state |= ICP_INTREG_WPROT; 552 } 553 } 554 555 static void icp_control_mmc_cardin(void *opaque, int line, int level) 556 { 557 ICPCtrlRegsState *s = opaque; 558 559 /* line is released by writing to CP_INTREG */ 560 if (level) { 561 s->intreg_state |= ICP_INTREG_CARDIN; 562 qemu_set_irq(s->mmc_irq, 1); 563 } 564 } 565 566 static void icp_control_init(Object *obj) 567 { 568 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 569 ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj); 570 DeviceState *dev = DEVICE(obj); 571 572 memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s, 573 "icp_ctrl_regs", 0x00800000); 574 sysbus_init_mmio(sbd, &s->iomem); 575 576 qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1); 577 qdev_init_gpio_in_named(dev, icp_control_mmc_cardin, 578 ICP_GPIO_MMC_CARDIN, 1); 579 sysbus_init_irq(sbd, &s->mmc_irq); 580 } 581 582 583 /* Board init. */ 584 585 static struct arm_boot_info integrator_binfo = { 586 .loader_start = 0x0, 587 .board_id = 0x113, 588 }; 589 590 static void integratorcp_init(MachineState *machine) 591 { 592 ram_addr_t ram_size = machine->ram_size; 593 Object *cpuobj; 594 ARMCPU *cpu; 595 MemoryRegion *address_space_mem = get_system_memory(); 596 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 597 qemu_irq pic[32]; 598 DeviceState *dev, *sic, *icp; 599 DriveInfo *dinfo; 600 int i; 601 602 cpuobj = object_new(machine->cpu_type); 603 604 /* By default ARM1176 CPUs have EL3 enabled. This board does not 605 * currently support EL3 so the CPU EL3 property is disabled before 606 * realization. 607 */ 608 if (object_property_find(cpuobj, "has_el3", NULL)) { 609 object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); 610 } 611 612 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 613 614 cpu = ARM_CPU(cpuobj); 615 616 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ 617 /* ??? RAM should repeat to fill physical memory space. */ 618 /* SDRAM at address zero*/ 619 memory_region_add_subregion(address_space_mem, 0, machine->ram); 620 /* And again at address 0x80000000 */ 621 memory_region_init_alias(ram_alias, NULL, "ram.alias", machine->ram, 622 0, ram_size); 623 memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias); 624 625 dev = qdev_new(TYPE_INTEGRATOR_CM); 626 qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); 627 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 628 sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); 629 630 dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000, 631 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), 632 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), 633 NULL); 634 for (i = 0; i < 32; i++) { 635 pic[i] = qdev_get_gpio_in(dev, i); 636 } 637 sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]); 638 sysbus_create_varargs("integrator_pit", 0x13000000, 639 pic[5], pic[6], pic[7], NULL); 640 sysbus_create_simple("pl031", 0x15000000, pic[8]); 641 pl011_create(0x16000000, pic[1], serial_hd(0)); 642 pl011_create(0x17000000, pic[2], serial_hd(1)); 643 icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000, 644 qdev_get_gpio_in(sic, 3)); 645 sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]); 646 sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]); 647 sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0); 648 649 dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL); 650 qdev_connect_gpio_out_named(dev, "card-read-only", 0, 651 qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0)); 652 qdev_connect_gpio_out_named(dev, "card-inserted", 0, 653 qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0)); 654 dinfo = drive_get_next(IF_SD); 655 if (dinfo) { 656 DeviceState *card; 657 658 card = qdev_new(TYPE_SD_CARD); 659 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 660 &error_fatal); 661 qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"), 662 &error_fatal); 663 } 664 665 sysbus_create_varargs("pl041", 0x1d000000, pic[25], NULL); 666 667 if (nd_table[0].used) 668 smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); 669 670 sysbus_create_simple("pl110", 0xc0000000, pic[22]); 671 672 integrator_binfo.ram_size = ram_size; 673 arm_load_kernel(cpu, machine, &integrator_binfo); 674 } 675 676 static void integratorcp_machine_init(MachineClass *mc) 677 { 678 mc->desc = "ARM Integrator/CP (ARM926EJ-S)"; 679 mc->init = integratorcp_init; 680 mc->ignore_memory_transaction_failures = true; 681 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 682 mc->default_ram_id = "integrator.ram"; 683 } 684 685 DEFINE_MACHINE("integratorcp", integratorcp_machine_init) 686 687 static Property core_properties[] = { 688 DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0), 689 DEFINE_PROP_END_OF_LIST(), 690 }; 691 692 static void core_class_init(ObjectClass *klass, void *data) 693 { 694 DeviceClass *dc = DEVICE_CLASS(klass); 695 696 device_class_set_props(dc, core_properties); 697 dc->realize = integratorcm_realize; 698 dc->vmsd = &vmstate_integratorcm; 699 } 700 701 static void icp_pic_class_init(ObjectClass *klass, void *data) 702 { 703 DeviceClass *dc = DEVICE_CLASS(klass); 704 705 dc->vmsd = &vmstate_icp_pic; 706 } 707 708 static void icp_control_class_init(ObjectClass *klass, void *data) 709 { 710 DeviceClass *dc = DEVICE_CLASS(klass); 711 712 dc->vmsd = &vmstate_icp_control; 713 } 714 715 static const TypeInfo core_info = { 716 .name = TYPE_INTEGRATOR_CM, 717 .parent = TYPE_SYS_BUS_DEVICE, 718 .instance_size = sizeof(IntegratorCMState), 719 .instance_init = integratorcm_init, 720 .class_init = core_class_init, 721 }; 722 723 static const TypeInfo icp_pic_info = { 724 .name = TYPE_INTEGRATOR_PIC, 725 .parent = TYPE_SYS_BUS_DEVICE, 726 .instance_size = sizeof(icp_pic_state), 727 .instance_init = icp_pic_init, 728 .class_init = icp_pic_class_init, 729 }; 730 731 static const TypeInfo icp_ctrl_regs_info = { 732 .name = TYPE_ICP_CONTROL_REGS, 733 .parent = TYPE_SYS_BUS_DEVICE, 734 .instance_size = sizeof(ICPCtrlRegsState), 735 .instance_init = icp_control_init, 736 .class_init = icp_control_class_init, 737 }; 738 739 static void integratorcp_register_types(void) 740 { 741 type_register_static(&icp_pic_info); 742 type_register_static(&core_info); 743 type_register_static(&icp_ctrl_regs_info); 744 } 745 746 type_init(integratorcp_register_types) 747