1 /* 2 * ARM Integrator CP System emulation. 3 * 4 * Copyright (c) 2005-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL 8 */ 9 10 #include "hw/sysbus.h" 11 #include "hw/devices.h" 12 #include "hw/boards.h" 13 #include "hw/arm/arm.h" 14 #include "hw/misc/arm_integrator_debug.h" 15 #include "net/net.h" 16 #include "exec/address-spaces.h" 17 #include "sysemu/sysemu.h" 18 19 #define TYPE_INTEGRATOR_CM "integrator_core" 20 #define INTEGRATOR_CM(obj) \ 21 OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM) 22 23 typedef struct IntegratorCMState { 24 /*< private >*/ 25 SysBusDevice parent_obj; 26 /*< public >*/ 27 28 MemoryRegion iomem; 29 uint32_t memsz; 30 MemoryRegion flash; 31 uint32_t cm_osc; 32 uint32_t cm_ctrl; 33 uint32_t cm_lock; 34 uint32_t cm_auxosc; 35 uint32_t cm_sdram; 36 uint32_t cm_init; 37 uint32_t cm_flags; 38 uint32_t cm_nvflags; 39 uint32_t int_level; 40 uint32_t irq_enabled; 41 uint32_t fiq_enabled; 42 } IntegratorCMState; 43 44 static uint8_t integrator_spd[128] = { 45 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1, 46 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 47 }; 48 49 static uint64_t integratorcm_read(void *opaque, hwaddr offset, 50 unsigned size) 51 { 52 IntegratorCMState *s = opaque; 53 if (offset >= 0x100 && offset < 0x200) { 54 /* CM_SPD */ 55 if (offset >= 0x180) 56 return 0; 57 return integrator_spd[offset >> 2]; 58 } 59 switch (offset >> 2) { 60 case 0: /* CM_ID */ 61 return 0x411a3001; 62 case 1: /* CM_PROC */ 63 return 0; 64 case 2: /* CM_OSC */ 65 return s->cm_osc; 66 case 3: /* CM_CTRL */ 67 return s->cm_ctrl; 68 case 4: /* CM_STAT */ 69 return 0x00100000; 70 case 5: /* CM_LOCK */ 71 if (s->cm_lock == 0xa05f) { 72 return 0x1a05f; 73 } else { 74 return s->cm_lock; 75 } 76 case 6: /* CM_LMBUSCNT */ 77 /* ??? High frequency timer. */ 78 hw_error("integratorcm_read: CM_LMBUSCNT"); 79 case 7: /* CM_AUXOSC */ 80 return s->cm_auxosc; 81 case 8: /* CM_SDRAM */ 82 return s->cm_sdram; 83 case 9: /* CM_INIT */ 84 return s->cm_init; 85 case 10: /* CM_REFCT */ 86 /* ??? High frequency timer. */ 87 hw_error("integratorcm_read: CM_REFCT"); 88 case 12: /* CM_FLAGS */ 89 return s->cm_flags; 90 case 14: /* CM_NVFLAGS */ 91 return s->cm_nvflags; 92 case 16: /* CM_IRQ_STAT */ 93 return s->int_level & s->irq_enabled; 94 case 17: /* CM_IRQ_RSTAT */ 95 return s->int_level; 96 case 18: /* CM_IRQ_ENSET */ 97 return s->irq_enabled; 98 case 20: /* CM_SOFT_INTSET */ 99 return s->int_level & 1; 100 case 24: /* CM_FIQ_STAT */ 101 return s->int_level & s->fiq_enabled; 102 case 25: /* CM_FIQ_RSTAT */ 103 return s->int_level; 104 case 26: /* CM_FIQ_ENSET */ 105 return s->fiq_enabled; 106 case 32: /* CM_VOLTAGE_CTL0 */ 107 case 33: /* CM_VOLTAGE_CTL1 */ 108 case 34: /* CM_VOLTAGE_CTL2 */ 109 case 35: /* CM_VOLTAGE_CTL3 */ 110 /* ??? Voltage control unimplemented. */ 111 return 0; 112 default: 113 hw_error("integratorcm_read: Unimplemented offset 0x%x\n", 114 (int)offset); 115 return 0; 116 } 117 } 118 119 static void integratorcm_do_remap(IntegratorCMState *s) 120 { 121 /* Sync memory region state with CM_CTRL REMAP bit: 122 * bit 0 => flash at address 0; bit 1 => RAM 123 */ 124 memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4)); 125 } 126 127 static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value) 128 { 129 if (value & 8) { 130 qemu_system_reset_request(); 131 } 132 if ((s->cm_ctrl ^ value) & 1) { 133 /* (value & 1) != 0 means the green "MISC LED" is lit. 134 * We don't have any nice place to display LEDs. printf is a bad 135 * idea because Linux uses the LED as a heartbeat and the output 136 * will swamp anything else on the terminal. 137 */ 138 } 139 /* Note that the RESET bit [3] always reads as zero */ 140 s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5); 141 integratorcm_do_remap(s); 142 } 143 144 static void integratorcm_update(IntegratorCMState *s) 145 { 146 /* ??? The CPU irq/fiq is raised when either the core module or base PIC 147 are active. */ 148 if (s->int_level & (s->irq_enabled | s->fiq_enabled)) 149 hw_error("Core module interrupt\n"); 150 } 151 152 static void integratorcm_write(void *opaque, hwaddr offset, 153 uint64_t value, unsigned size) 154 { 155 IntegratorCMState *s = opaque; 156 switch (offset >> 2) { 157 case 2: /* CM_OSC */ 158 if (s->cm_lock == 0xa05f) 159 s->cm_osc = value; 160 break; 161 case 3: /* CM_CTRL */ 162 integratorcm_set_ctrl(s, value); 163 break; 164 case 5: /* CM_LOCK */ 165 s->cm_lock = value & 0xffff; 166 break; 167 case 7: /* CM_AUXOSC */ 168 if (s->cm_lock == 0xa05f) 169 s->cm_auxosc = value; 170 break; 171 case 8: /* CM_SDRAM */ 172 s->cm_sdram = value; 173 break; 174 case 9: /* CM_INIT */ 175 /* ??? This can change the memory bus frequency. */ 176 s->cm_init = value; 177 break; 178 case 12: /* CM_FLAGSS */ 179 s->cm_flags |= value; 180 break; 181 case 13: /* CM_FLAGSC */ 182 s->cm_flags &= ~value; 183 break; 184 case 14: /* CM_NVFLAGSS */ 185 s->cm_nvflags |= value; 186 break; 187 case 15: /* CM_NVFLAGSS */ 188 s->cm_nvflags &= ~value; 189 break; 190 case 18: /* CM_IRQ_ENSET */ 191 s->irq_enabled |= value; 192 integratorcm_update(s); 193 break; 194 case 19: /* CM_IRQ_ENCLR */ 195 s->irq_enabled &= ~value; 196 integratorcm_update(s); 197 break; 198 case 20: /* CM_SOFT_INTSET */ 199 s->int_level |= (value & 1); 200 integratorcm_update(s); 201 break; 202 case 21: /* CM_SOFT_INTCLR */ 203 s->int_level &= ~(value & 1); 204 integratorcm_update(s); 205 break; 206 case 26: /* CM_FIQ_ENSET */ 207 s->fiq_enabled |= value; 208 integratorcm_update(s); 209 break; 210 case 27: /* CM_FIQ_ENCLR */ 211 s->fiq_enabled &= ~value; 212 integratorcm_update(s); 213 break; 214 case 32: /* CM_VOLTAGE_CTL0 */ 215 case 33: /* CM_VOLTAGE_CTL1 */ 216 case 34: /* CM_VOLTAGE_CTL2 */ 217 case 35: /* CM_VOLTAGE_CTL3 */ 218 /* ??? Voltage control unimplemented. */ 219 break; 220 default: 221 hw_error("integratorcm_write: Unimplemented offset 0x%x\n", 222 (int)offset); 223 break; 224 } 225 } 226 227 /* Integrator/CM control registers. */ 228 229 static const MemoryRegionOps integratorcm_ops = { 230 .read = integratorcm_read, 231 .write = integratorcm_write, 232 .endianness = DEVICE_NATIVE_ENDIAN, 233 }; 234 235 static int integratorcm_init(SysBusDevice *dev) 236 { 237 IntegratorCMState *s = INTEGRATOR_CM(dev); 238 239 s->cm_osc = 0x01000048; 240 /* ??? What should the high bits of this value be? */ 241 s->cm_auxosc = 0x0007feff; 242 s->cm_sdram = 0x00011122; 243 if (s->memsz >= 256) { 244 integrator_spd[31] = 64; 245 s->cm_sdram |= 0x10; 246 } else if (s->memsz >= 128) { 247 integrator_spd[31] = 32; 248 s->cm_sdram |= 0x0c; 249 } else if (s->memsz >= 64) { 250 integrator_spd[31] = 16; 251 s->cm_sdram |= 0x08; 252 } else if (s->memsz >= 32) { 253 integrator_spd[31] = 4; 254 s->cm_sdram |= 0x04; 255 } else { 256 integrator_spd[31] = 2; 257 } 258 memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); 259 s->cm_init = 0x00000112; 260 memory_region_init_ram(&s->flash, OBJECT(s), "integrator.flash", 0x100000); 261 vmstate_register_ram_global(&s->flash); 262 263 memory_region_init_io(&s->iomem, OBJECT(s), &integratorcm_ops, s, 264 "integratorcm", 0x00800000); 265 sysbus_init_mmio(dev, &s->iomem); 266 267 integratorcm_do_remap(s); 268 /* ??? Save/restore. */ 269 return 0; 270 } 271 272 /* Integrator/CP hardware emulation. */ 273 /* Primary interrupt controller. */ 274 275 #define TYPE_INTEGRATOR_PIC "integrator_pic" 276 #define INTEGRATOR_PIC(obj) \ 277 OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC) 278 279 typedef struct icp_pic_state { 280 /*< private >*/ 281 SysBusDevice parent_obj; 282 /*< public >*/ 283 284 MemoryRegion iomem; 285 uint32_t level; 286 uint32_t irq_enabled; 287 uint32_t fiq_enabled; 288 qemu_irq parent_irq; 289 qemu_irq parent_fiq; 290 } icp_pic_state; 291 292 static void icp_pic_update(icp_pic_state *s) 293 { 294 uint32_t flags; 295 296 flags = (s->level & s->irq_enabled); 297 qemu_set_irq(s->parent_irq, flags != 0); 298 flags = (s->level & s->fiq_enabled); 299 qemu_set_irq(s->parent_fiq, flags != 0); 300 } 301 302 static void icp_pic_set_irq(void *opaque, int irq, int level) 303 { 304 icp_pic_state *s = (icp_pic_state *)opaque; 305 if (level) 306 s->level |= 1 << irq; 307 else 308 s->level &= ~(1 << irq); 309 icp_pic_update(s); 310 } 311 312 static uint64_t icp_pic_read(void *opaque, hwaddr offset, 313 unsigned size) 314 { 315 icp_pic_state *s = (icp_pic_state *)opaque; 316 317 switch (offset >> 2) { 318 case 0: /* IRQ_STATUS */ 319 return s->level & s->irq_enabled; 320 case 1: /* IRQ_RAWSTAT */ 321 return s->level; 322 case 2: /* IRQ_ENABLESET */ 323 return s->irq_enabled; 324 case 4: /* INT_SOFTSET */ 325 return s->level & 1; 326 case 8: /* FRQ_STATUS */ 327 return s->level & s->fiq_enabled; 328 case 9: /* FRQ_RAWSTAT */ 329 return s->level; 330 case 10: /* FRQ_ENABLESET */ 331 return s->fiq_enabled; 332 case 3: /* IRQ_ENABLECLR */ 333 case 5: /* INT_SOFTCLR */ 334 case 11: /* FRQ_ENABLECLR */ 335 default: 336 printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset); 337 return 0; 338 } 339 } 340 341 static void icp_pic_write(void *opaque, hwaddr offset, 342 uint64_t value, unsigned size) 343 { 344 icp_pic_state *s = (icp_pic_state *)opaque; 345 346 switch (offset >> 2) { 347 case 2: /* IRQ_ENABLESET */ 348 s->irq_enabled |= value; 349 break; 350 case 3: /* IRQ_ENABLECLR */ 351 s->irq_enabled &= ~value; 352 break; 353 case 4: /* INT_SOFTSET */ 354 if (value & 1) 355 icp_pic_set_irq(s, 0, 1); 356 break; 357 case 5: /* INT_SOFTCLR */ 358 if (value & 1) 359 icp_pic_set_irq(s, 0, 0); 360 break; 361 case 10: /* FRQ_ENABLESET */ 362 s->fiq_enabled |= value; 363 break; 364 case 11: /* FRQ_ENABLECLR */ 365 s->fiq_enabled &= ~value; 366 break; 367 case 0: /* IRQ_STATUS */ 368 case 1: /* IRQ_RAWSTAT */ 369 case 8: /* FRQ_STATUS */ 370 case 9: /* FRQ_RAWSTAT */ 371 default: 372 printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset); 373 return; 374 } 375 icp_pic_update(s); 376 } 377 378 static const MemoryRegionOps icp_pic_ops = { 379 .read = icp_pic_read, 380 .write = icp_pic_write, 381 .endianness = DEVICE_NATIVE_ENDIAN, 382 }; 383 384 static int icp_pic_init(SysBusDevice *sbd) 385 { 386 DeviceState *dev = DEVICE(sbd); 387 icp_pic_state *s = INTEGRATOR_PIC(dev); 388 389 qdev_init_gpio_in(dev, icp_pic_set_irq, 32); 390 sysbus_init_irq(sbd, &s->parent_irq); 391 sysbus_init_irq(sbd, &s->parent_fiq); 392 memory_region_init_io(&s->iomem, OBJECT(s), &icp_pic_ops, s, 393 "icp-pic", 0x00800000); 394 sysbus_init_mmio(sbd, &s->iomem); 395 return 0; 396 } 397 398 /* CP control registers. */ 399 400 static uint64_t icp_control_read(void *opaque, hwaddr offset, 401 unsigned size) 402 { 403 switch (offset >> 2) { 404 case 0: /* CP_IDFIELD */ 405 return 0x41034003; 406 case 1: /* CP_FLASHPROG */ 407 return 0; 408 case 2: /* CP_INTREG */ 409 return 0; 410 case 3: /* CP_DECODE */ 411 return 0x11; 412 default: 413 hw_error("icp_control_read: Bad offset %x\n", (int)offset); 414 return 0; 415 } 416 } 417 418 static void icp_control_write(void *opaque, hwaddr offset, 419 uint64_t value, unsigned size) 420 { 421 switch (offset >> 2) { 422 case 1: /* CP_FLASHPROG */ 423 case 2: /* CP_INTREG */ 424 case 3: /* CP_DECODE */ 425 /* Nothing interesting implemented yet. */ 426 break; 427 default: 428 hw_error("icp_control_write: Bad offset %x\n", (int)offset); 429 } 430 } 431 432 static const MemoryRegionOps icp_control_ops = { 433 .read = icp_control_read, 434 .write = icp_control_write, 435 .endianness = DEVICE_NATIVE_ENDIAN, 436 }; 437 438 static void icp_control_init(hwaddr base) 439 { 440 MemoryRegion *io; 441 442 io = (MemoryRegion *)g_malloc0(sizeof(MemoryRegion)); 443 memory_region_init_io(io, NULL, &icp_control_ops, NULL, 444 "control", 0x00800000); 445 memory_region_add_subregion(get_system_memory(), base, io); 446 /* ??? Save/restore. */ 447 } 448 449 450 /* Board init. */ 451 452 static struct arm_boot_info integrator_binfo = { 453 .loader_start = 0x0, 454 .board_id = 0x113, 455 }; 456 457 static void integratorcp_init(QEMUMachineInitArgs *args) 458 { 459 ram_addr_t ram_size = args->ram_size; 460 const char *cpu_model = args->cpu_model; 461 const char *kernel_filename = args->kernel_filename; 462 const char *kernel_cmdline = args->kernel_cmdline; 463 const char *initrd_filename = args->initrd_filename; 464 ARMCPU *cpu; 465 MemoryRegion *address_space_mem = get_system_memory(); 466 MemoryRegion *ram = g_new(MemoryRegion, 1); 467 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 468 qemu_irq pic[32]; 469 DeviceState *dev; 470 int i; 471 472 if (!cpu_model) { 473 cpu_model = "arm926"; 474 } 475 cpu = cpu_arm_init(cpu_model); 476 if (!cpu) { 477 fprintf(stderr, "Unable to find CPU definition\n"); 478 exit(1); 479 } 480 481 memory_region_init_ram(ram, NULL, "integrator.ram", ram_size); 482 vmstate_register_ram_global(ram); 483 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ 484 /* ??? RAM should repeat to fill physical memory space. */ 485 /* SDRAM at address zero*/ 486 memory_region_add_subregion(address_space_mem, 0, ram); 487 /* And again at address 0x80000000 */ 488 memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size); 489 memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias); 490 491 dev = qdev_create(NULL, TYPE_INTEGRATOR_CM); 492 qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); 493 qdev_init_nofail(dev); 494 sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); 495 496 dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000, 497 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), 498 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), 499 NULL); 500 for (i = 0; i < 32; i++) { 501 pic[i] = qdev_get_gpio_in(dev, i); 502 } 503 sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]); 504 sysbus_create_varargs("integrator_pit", 0x13000000, 505 pic[5], pic[6], pic[7], NULL); 506 sysbus_create_simple("pl031", 0x15000000, pic[8]); 507 sysbus_create_simple("pl011", 0x16000000, pic[1]); 508 sysbus_create_simple("pl011", 0x17000000, pic[2]); 509 icp_control_init(0xcb000000); 510 sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]); 511 sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]); 512 sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0); 513 sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL); 514 if (nd_table[0].used) 515 smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); 516 517 sysbus_create_simple("pl110", 0xc0000000, pic[22]); 518 519 integrator_binfo.ram_size = ram_size; 520 integrator_binfo.kernel_filename = kernel_filename; 521 integrator_binfo.kernel_cmdline = kernel_cmdline; 522 integrator_binfo.initrd_filename = initrd_filename; 523 arm_load_kernel(cpu, &integrator_binfo); 524 } 525 526 static QEMUMachine integratorcp_machine = { 527 .name = "integratorcp", 528 .desc = "ARM Integrator/CP (ARM926EJ-S)", 529 .init = integratorcp_init, 530 .is_default = 1, 531 }; 532 533 static void integratorcp_machine_init(void) 534 { 535 qemu_register_machine(&integratorcp_machine); 536 } 537 538 machine_init(integratorcp_machine_init); 539 540 static Property core_properties[] = { 541 DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0), 542 DEFINE_PROP_END_OF_LIST(), 543 }; 544 545 static void core_class_init(ObjectClass *klass, void *data) 546 { 547 DeviceClass *dc = DEVICE_CLASS(klass); 548 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 549 550 k->init = integratorcm_init; 551 dc->props = core_properties; 552 } 553 554 static const TypeInfo core_info = { 555 .name = TYPE_INTEGRATOR_CM, 556 .parent = TYPE_SYS_BUS_DEVICE, 557 .instance_size = sizeof(IntegratorCMState), 558 .class_init = core_class_init, 559 }; 560 561 static void icp_pic_class_init(ObjectClass *klass, void *data) 562 { 563 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 564 565 sdc->init = icp_pic_init; 566 } 567 568 static const TypeInfo icp_pic_info = { 569 .name = TYPE_INTEGRATOR_PIC, 570 .parent = TYPE_SYS_BUS_DEVICE, 571 .instance_size = sizeof(icp_pic_state), 572 .class_init = icp_pic_class_init, 573 }; 574 575 static void integratorcp_register_types(void) 576 { 577 type_register_static(&icp_pic_info); 578 type_register_static(&core_info); 579 } 580 581 type_init(integratorcp_register_types) 582