1 /* 2 * ARM Integrator CP System emulation. 3 * 4 * Copyright (c) 2005-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "cpu.h" 13 #include "hw/sysbus.h" 14 #include "migration/vmstate.h" 15 #include "hw/boards.h" 16 #include "hw/arm/boot.h" 17 #include "hw/misc/arm_integrator_debug.h" 18 #include "hw/net/smc91c111.h" 19 #include "net/net.h" 20 #include "exec/address-spaces.h" 21 #include "sysemu/runstate.h" 22 #include "sysemu/sysemu.h" 23 #include "qemu/error-report.h" 24 #include "hw/char/pl011.h" 25 #include "hw/hw.h" 26 #include "hw/irq.h" 27 28 #define TYPE_INTEGRATOR_CM "integrator_core" 29 #define INTEGRATOR_CM(obj) \ 30 OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM) 31 32 typedef struct IntegratorCMState { 33 /*< private >*/ 34 SysBusDevice parent_obj; 35 /*< public >*/ 36 37 MemoryRegion iomem; 38 uint32_t memsz; 39 MemoryRegion flash; 40 uint32_t cm_osc; 41 uint32_t cm_ctrl; 42 uint32_t cm_lock; 43 uint32_t cm_auxosc; 44 uint32_t cm_sdram; 45 uint32_t cm_init; 46 uint32_t cm_flags; 47 uint32_t cm_nvflags; 48 uint32_t cm_refcnt_offset; 49 uint32_t int_level; 50 uint32_t irq_enabled; 51 uint32_t fiq_enabled; 52 } IntegratorCMState; 53 54 static uint8_t integrator_spd[128] = { 55 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1, 56 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 57 }; 58 59 static const VMStateDescription vmstate_integratorcm = { 60 .name = "integratorcm", 61 .version_id = 1, 62 .minimum_version_id = 1, 63 .fields = (VMStateField[]) { 64 VMSTATE_UINT32(cm_osc, IntegratorCMState), 65 VMSTATE_UINT32(cm_ctrl, IntegratorCMState), 66 VMSTATE_UINT32(cm_lock, IntegratorCMState), 67 VMSTATE_UINT32(cm_auxosc, IntegratorCMState), 68 VMSTATE_UINT32(cm_sdram, IntegratorCMState), 69 VMSTATE_UINT32(cm_init, IntegratorCMState), 70 VMSTATE_UINT32(cm_flags, IntegratorCMState), 71 VMSTATE_UINT32(cm_nvflags, IntegratorCMState), 72 VMSTATE_UINT32(int_level, IntegratorCMState), 73 VMSTATE_UINT32(irq_enabled, IntegratorCMState), 74 VMSTATE_UINT32(fiq_enabled, IntegratorCMState), 75 VMSTATE_END_OF_LIST() 76 } 77 }; 78 79 static uint64_t integratorcm_read(void *opaque, hwaddr offset, 80 unsigned size) 81 { 82 IntegratorCMState *s = opaque; 83 if (offset >= 0x100 && offset < 0x200) { 84 /* CM_SPD */ 85 if (offset >= 0x180) 86 return 0; 87 return integrator_spd[offset >> 2]; 88 } 89 switch (offset >> 2) { 90 case 0: /* CM_ID */ 91 return 0x411a3001; 92 case 1: /* CM_PROC */ 93 return 0; 94 case 2: /* CM_OSC */ 95 return s->cm_osc; 96 case 3: /* CM_CTRL */ 97 return s->cm_ctrl; 98 case 4: /* CM_STAT */ 99 return 0x00100000; 100 case 5: /* CM_LOCK */ 101 if (s->cm_lock == 0xa05f) { 102 return 0x1a05f; 103 } else { 104 return s->cm_lock; 105 } 106 case 6: /* CM_LMBUSCNT */ 107 /* ??? High frequency timer. */ 108 hw_error("integratorcm_read: CM_LMBUSCNT"); 109 case 7: /* CM_AUXOSC */ 110 return s->cm_auxosc; 111 case 8: /* CM_SDRAM */ 112 return s->cm_sdram; 113 case 9: /* CM_INIT */ 114 return s->cm_init; 115 case 10: /* CM_REFCNT */ 116 /* This register, CM_REFCNT, provides a 32-bit count value. 117 * The count increments at the fixed reference clock frequency of 24MHz 118 * and can be used as a real-time counter. 119 */ 120 return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 121 1000) - s->cm_refcnt_offset; 122 case 12: /* CM_FLAGS */ 123 return s->cm_flags; 124 case 14: /* CM_NVFLAGS */ 125 return s->cm_nvflags; 126 case 16: /* CM_IRQ_STAT */ 127 return s->int_level & s->irq_enabled; 128 case 17: /* CM_IRQ_RSTAT */ 129 return s->int_level; 130 case 18: /* CM_IRQ_ENSET */ 131 return s->irq_enabled; 132 case 20: /* CM_SOFT_INTSET */ 133 return s->int_level & 1; 134 case 24: /* CM_FIQ_STAT */ 135 return s->int_level & s->fiq_enabled; 136 case 25: /* CM_FIQ_RSTAT */ 137 return s->int_level; 138 case 26: /* CM_FIQ_ENSET */ 139 return s->fiq_enabled; 140 case 32: /* CM_VOLTAGE_CTL0 */ 141 case 33: /* CM_VOLTAGE_CTL1 */ 142 case 34: /* CM_VOLTAGE_CTL2 */ 143 case 35: /* CM_VOLTAGE_CTL3 */ 144 /* ??? Voltage control unimplemented. */ 145 return 0; 146 default: 147 hw_error("integratorcm_read: Unimplemented offset 0x%x\n", 148 (int)offset); 149 return 0; 150 } 151 } 152 153 static void integratorcm_do_remap(IntegratorCMState *s) 154 { 155 /* Sync memory region state with CM_CTRL REMAP bit: 156 * bit 0 => flash at address 0; bit 1 => RAM 157 */ 158 memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4)); 159 } 160 161 static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value) 162 { 163 if (value & 8) { 164 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 165 } 166 if ((s->cm_ctrl ^ value) & 1) { 167 /* (value & 1) != 0 means the green "MISC LED" is lit. 168 * We don't have any nice place to display LEDs. printf is a bad 169 * idea because Linux uses the LED as a heartbeat and the output 170 * will swamp anything else on the terminal. 171 */ 172 } 173 /* Note that the RESET bit [3] always reads as zero */ 174 s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5); 175 integratorcm_do_remap(s); 176 } 177 178 static void integratorcm_update(IntegratorCMState *s) 179 { 180 /* ??? The CPU irq/fiq is raised when either the core module or base PIC 181 are active. */ 182 if (s->int_level & (s->irq_enabled | s->fiq_enabled)) 183 hw_error("Core module interrupt\n"); 184 } 185 186 static void integratorcm_write(void *opaque, hwaddr offset, 187 uint64_t value, unsigned size) 188 { 189 IntegratorCMState *s = opaque; 190 switch (offset >> 2) { 191 case 2: /* CM_OSC */ 192 if (s->cm_lock == 0xa05f) 193 s->cm_osc = value; 194 break; 195 case 3: /* CM_CTRL */ 196 integratorcm_set_ctrl(s, value); 197 break; 198 case 5: /* CM_LOCK */ 199 s->cm_lock = value & 0xffff; 200 break; 201 case 7: /* CM_AUXOSC */ 202 if (s->cm_lock == 0xa05f) 203 s->cm_auxosc = value; 204 break; 205 case 8: /* CM_SDRAM */ 206 s->cm_sdram = value; 207 break; 208 case 9: /* CM_INIT */ 209 /* ??? This can change the memory bus frequency. */ 210 s->cm_init = value; 211 break; 212 case 12: /* CM_FLAGSS */ 213 s->cm_flags |= value; 214 break; 215 case 13: /* CM_FLAGSC */ 216 s->cm_flags &= ~value; 217 break; 218 case 14: /* CM_NVFLAGSS */ 219 s->cm_nvflags |= value; 220 break; 221 case 15: /* CM_NVFLAGSS */ 222 s->cm_nvflags &= ~value; 223 break; 224 case 18: /* CM_IRQ_ENSET */ 225 s->irq_enabled |= value; 226 integratorcm_update(s); 227 break; 228 case 19: /* CM_IRQ_ENCLR */ 229 s->irq_enabled &= ~value; 230 integratorcm_update(s); 231 break; 232 case 20: /* CM_SOFT_INTSET */ 233 s->int_level |= (value & 1); 234 integratorcm_update(s); 235 break; 236 case 21: /* CM_SOFT_INTCLR */ 237 s->int_level &= ~(value & 1); 238 integratorcm_update(s); 239 break; 240 case 26: /* CM_FIQ_ENSET */ 241 s->fiq_enabled |= value; 242 integratorcm_update(s); 243 break; 244 case 27: /* CM_FIQ_ENCLR */ 245 s->fiq_enabled &= ~value; 246 integratorcm_update(s); 247 break; 248 case 32: /* CM_VOLTAGE_CTL0 */ 249 case 33: /* CM_VOLTAGE_CTL1 */ 250 case 34: /* CM_VOLTAGE_CTL2 */ 251 case 35: /* CM_VOLTAGE_CTL3 */ 252 /* ??? Voltage control unimplemented. */ 253 break; 254 default: 255 hw_error("integratorcm_write: Unimplemented offset 0x%x\n", 256 (int)offset); 257 break; 258 } 259 } 260 261 /* Integrator/CM control registers. */ 262 263 static const MemoryRegionOps integratorcm_ops = { 264 .read = integratorcm_read, 265 .write = integratorcm_write, 266 .endianness = DEVICE_NATIVE_ENDIAN, 267 }; 268 269 static void integratorcm_init(Object *obj) 270 { 271 IntegratorCMState *s = INTEGRATOR_CM(obj); 272 273 s->cm_osc = 0x01000048; 274 /* ??? What should the high bits of this value be? */ 275 s->cm_auxosc = 0x0007feff; 276 s->cm_sdram = 0x00011122; 277 memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); 278 s->cm_init = 0x00000112; 279 s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 280 1000); 281 282 /* ??? Save/restore. */ 283 } 284 285 static void integratorcm_realize(DeviceState *d, Error **errp) 286 { 287 IntegratorCMState *s = INTEGRATOR_CM(d); 288 SysBusDevice *dev = SYS_BUS_DEVICE(d); 289 Error *local_err = NULL; 290 291 memory_region_init_ram(&s->flash, OBJECT(d), "integrator.flash", 0x100000, 292 &local_err); 293 if (local_err) { 294 error_propagate(errp, local_err); 295 return; 296 } 297 298 memory_region_init_io(&s->iomem, OBJECT(d), &integratorcm_ops, s, 299 "integratorcm", 0x00800000); 300 sysbus_init_mmio(dev, &s->iomem); 301 302 integratorcm_do_remap(s); 303 304 if (s->memsz >= 256) { 305 integrator_spd[31] = 64; 306 s->cm_sdram |= 0x10; 307 } else if (s->memsz >= 128) { 308 integrator_spd[31] = 32; 309 s->cm_sdram |= 0x0c; 310 } else if (s->memsz >= 64) { 311 integrator_spd[31] = 16; 312 s->cm_sdram |= 0x08; 313 } else if (s->memsz >= 32) { 314 integrator_spd[31] = 4; 315 s->cm_sdram |= 0x04; 316 } else { 317 integrator_spd[31] = 2; 318 } 319 } 320 321 /* Integrator/CP hardware emulation. */ 322 /* Primary interrupt controller. */ 323 324 #define TYPE_INTEGRATOR_PIC "integrator_pic" 325 #define INTEGRATOR_PIC(obj) \ 326 OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC) 327 328 typedef struct icp_pic_state { 329 /*< private >*/ 330 SysBusDevice parent_obj; 331 /*< public >*/ 332 333 MemoryRegion iomem; 334 uint32_t level; 335 uint32_t irq_enabled; 336 uint32_t fiq_enabled; 337 qemu_irq parent_irq; 338 qemu_irq parent_fiq; 339 } icp_pic_state; 340 341 static const VMStateDescription vmstate_icp_pic = { 342 .name = "icp_pic", 343 .version_id = 1, 344 .minimum_version_id = 1, 345 .fields = (VMStateField[]) { 346 VMSTATE_UINT32(level, icp_pic_state), 347 VMSTATE_UINT32(irq_enabled, icp_pic_state), 348 VMSTATE_UINT32(fiq_enabled, icp_pic_state), 349 VMSTATE_END_OF_LIST() 350 } 351 }; 352 353 static void icp_pic_update(icp_pic_state *s) 354 { 355 uint32_t flags; 356 357 flags = (s->level & s->irq_enabled); 358 qemu_set_irq(s->parent_irq, flags != 0); 359 flags = (s->level & s->fiq_enabled); 360 qemu_set_irq(s->parent_fiq, flags != 0); 361 } 362 363 static void icp_pic_set_irq(void *opaque, int irq, int level) 364 { 365 icp_pic_state *s = (icp_pic_state *)opaque; 366 if (level) 367 s->level |= 1 << irq; 368 else 369 s->level &= ~(1 << irq); 370 icp_pic_update(s); 371 } 372 373 static uint64_t icp_pic_read(void *opaque, hwaddr offset, 374 unsigned size) 375 { 376 icp_pic_state *s = (icp_pic_state *)opaque; 377 378 switch (offset >> 2) { 379 case 0: /* IRQ_STATUS */ 380 return s->level & s->irq_enabled; 381 case 1: /* IRQ_RAWSTAT */ 382 return s->level; 383 case 2: /* IRQ_ENABLESET */ 384 return s->irq_enabled; 385 case 4: /* INT_SOFTSET */ 386 return s->level & 1; 387 case 8: /* FRQ_STATUS */ 388 return s->level & s->fiq_enabled; 389 case 9: /* FRQ_RAWSTAT */ 390 return s->level; 391 case 10: /* FRQ_ENABLESET */ 392 return s->fiq_enabled; 393 case 3: /* IRQ_ENABLECLR */ 394 case 5: /* INT_SOFTCLR */ 395 case 11: /* FRQ_ENABLECLR */ 396 default: 397 printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset); 398 return 0; 399 } 400 } 401 402 static void icp_pic_write(void *opaque, hwaddr offset, 403 uint64_t value, unsigned size) 404 { 405 icp_pic_state *s = (icp_pic_state *)opaque; 406 407 switch (offset >> 2) { 408 case 2: /* IRQ_ENABLESET */ 409 s->irq_enabled |= value; 410 break; 411 case 3: /* IRQ_ENABLECLR */ 412 s->irq_enabled &= ~value; 413 break; 414 case 4: /* INT_SOFTSET */ 415 if (value & 1) 416 icp_pic_set_irq(s, 0, 1); 417 break; 418 case 5: /* INT_SOFTCLR */ 419 if (value & 1) 420 icp_pic_set_irq(s, 0, 0); 421 break; 422 case 10: /* FRQ_ENABLESET */ 423 s->fiq_enabled |= value; 424 break; 425 case 11: /* FRQ_ENABLECLR */ 426 s->fiq_enabled &= ~value; 427 break; 428 case 0: /* IRQ_STATUS */ 429 case 1: /* IRQ_RAWSTAT */ 430 case 8: /* FRQ_STATUS */ 431 case 9: /* FRQ_RAWSTAT */ 432 default: 433 printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset); 434 return; 435 } 436 icp_pic_update(s); 437 } 438 439 static const MemoryRegionOps icp_pic_ops = { 440 .read = icp_pic_read, 441 .write = icp_pic_write, 442 .endianness = DEVICE_NATIVE_ENDIAN, 443 }; 444 445 static void icp_pic_init(Object *obj) 446 { 447 DeviceState *dev = DEVICE(obj); 448 icp_pic_state *s = INTEGRATOR_PIC(obj); 449 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 450 451 qdev_init_gpio_in(dev, icp_pic_set_irq, 32); 452 sysbus_init_irq(sbd, &s->parent_irq); 453 sysbus_init_irq(sbd, &s->parent_fiq); 454 memory_region_init_io(&s->iomem, obj, &icp_pic_ops, s, 455 "icp-pic", 0x00800000); 456 sysbus_init_mmio(sbd, &s->iomem); 457 } 458 459 /* CP control registers. */ 460 461 #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs" 462 #define ICP_CONTROL_REGS(obj) \ 463 OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS) 464 465 typedef struct ICPCtrlRegsState { 466 /*< private >*/ 467 SysBusDevice parent_obj; 468 /*< public >*/ 469 470 MemoryRegion iomem; 471 472 qemu_irq mmc_irq; 473 uint32_t intreg_state; 474 } ICPCtrlRegsState; 475 476 #define ICP_GPIO_MMC_WPROT "mmc-wprot" 477 #define ICP_GPIO_MMC_CARDIN "mmc-cardin" 478 479 #define ICP_INTREG_WPROT (1 << 0) 480 #define ICP_INTREG_CARDIN (1 << 3) 481 482 static const VMStateDescription vmstate_icp_control = { 483 .name = "icp_control", 484 .version_id = 1, 485 .minimum_version_id = 1, 486 .fields = (VMStateField[]) { 487 VMSTATE_UINT32(intreg_state, ICPCtrlRegsState), 488 VMSTATE_END_OF_LIST() 489 } 490 }; 491 492 static uint64_t icp_control_read(void *opaque, hwaddr offset, 493 unsigned size) 494 { 495 ICPCtrlRegsState *s = opaque; 496 497 switch (offset >> 2) { 498 case 0: /* CP_IDFIELD */ 499 return 0x41034003; 500 case 1: /* CP_FLASHPROG */ 501 return 0; 502 case 2: /* CP_INTREG */ 503 return s->intreg_state; 504 case 3: /* CP_DECODE */ 505 return 0x11; 506 default: 507 hw_error("icp_control_read: Bad offset %x\n", (int)offset); 508 return 0; 509 } 510 } 511 512 static void icp_control_write(void *opaque, hwaddr offset, 513 uint64_t value, unsigned size) 514 { 515 ICPCtrlRegsState *s = opaque; 516 517 switch (offset >> 2) { 518 case 2: /* CP_INTREG */ 519 s->intreg_state &= ~(value & ICP_INTREG_CARDIN); 520 qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN)); 521 break; 522 case 1: /* CP_FLASHPROG */ 523 case 3: /* CP_DECODE */ 524 /* Nothing interesting implemented yet. */ 525 break; 526 default: 527 hw_error("icp_control_write: Bad offset %x\n", (int)offset); 528 } 529 } 530 531 static const MemoryRegionOps icp_control_ops = { 532 .read = icp_control_read, 533 .write = icp_control_write, 534 .endianness = DEVICE_NATIVE_ENDIAN, 535 }; 536 537 static void icp_control_mmc_wprot(void *opaque, int line, int level) 538 { 539 ICPCtrlRegsState *s = opaque; 540 541 s->intreg_state &= ~ICP_INTREG_WPROT; 542 if (level) { 543 s->intreg_state |= ICP_INTREG_WPROT; 544 } 545 } 546 547 static void icp_control_mmc_cardin(void *opaque, int line, int level) 548 { 549 ICPCtrlRegsState *s = opaque; 550 551 /* line is released by writing to CP_INTREG */ 552 if (level) { 553 s->intreg_state |= ICP_INTREG_CARDIN; 554 qemu_set_irq(s->mmc_irq, 1); 555 } 556 } 557 558 static void icp_control_init(Object *obj) 559 { 560 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 561 ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj); 562 DeviceState *dev = DEVICE(obj); 563 564 memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s, 565 "icp_ctrl_regs", 0x00800000); 566 sysbus_init_mmio(sbd, &s->iomem); 567 568 qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1); 569 qdev_init_gpio_in_named(dev, icp_control_mmc_cardin, 570 ICP_GPIO_MMC_CARDIN, 1); 571 sysbus_init_irq(sbd, &s->mmc_irq); 572 } 573 574 575 /* Board init. */ 576 577 static struct arm_boot_info integrator_binfo = { 578 .loader_start = 0x0, 579 .board_id = 0x113, 580 }; 581 582 static void integratorcp_init(MachineState *machine) 583 { 584 ram_addr_t ram_size = machine->ram_size; 585 Object *cpuobj; 586 ARMCPU *cpu; 587 MemoryRegion *address_space_mem = get_system_memory(); 588 MemoryRegion *ram = g_new(MemoryRegion, 1); 589 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 590 qemu_irq pic[32]; 591 DeviceState *dev, *sic, *icp; 592 int i; 593 594 cpuobj = object_new(machine->cpu_type); 595 596 /* By default ARM1176 CPUs have EL3 enabled. This board does not 597 * currently support EL3 so the CPU EL3 property is disabled before 598 * realization. 599 */ 600 if (object_property_find(cpuobj, "has_el3", NULL)) { 601 object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 602 } 603 604 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 605 606 cpu = ARM_CPU(cpuobj); 607 608 memory_region_allocate_system_memory(ram, NULL, "integrator.ram", 609 ram_size); 610 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ 611 /* ??? RAM should repeat to fill physical memory space. */ 612 /* SDRAM at address zero*/ 613 memory_region_add_subregion(address_space_mem, 0, ram); 614 /* And again at address 0x80000000 */ 615 memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size); 616 memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias); 617 618 dev = qdev_create(NULL, TYPE_INTEGRATOR_CM); 619 qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); 620 qdev_init_nofail(dev); 621 sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); 622 623 dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000, 624 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), 625 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), 626 NULL); 627 for (i = 0; i < 32; i++) { 628 pic[i] = qdev_get_gpio_in(dev, i); 629 } 630 sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]); 631 sysbus_create_varargs("integrator_pit", 0x13000000, 632 pic[5], pic[6], pic[7], NULL); 633 sysbus_create_simple("pl031", 0x15000000, pic[8]); 634 pl011_create(0x16000000, pic[1], serial_hd(0)); 635 pl011_create(0x17000000, pic[2], serial_hd(1)); 636 icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000, 637 qdev_get_gpio_in(sic, 3)); 638 sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]); 639 sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]); 640 sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0); 641 642 dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL); 643 qdev_connect_gpio_out(dev, 0, 644 qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0)); 645 qdev_connect_gpio_out(dev, 1, 646 qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0)); 647 648 if (nd_table[0].used) 649 smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); 650 651 sysbus_create_simple("pl110", 0xc0000000, pic[22]); 652 653 integrator_binfo.ram_size = ram_size; 654 arm_load_kernel(cpu, machine, &integrator_binfo); 655 } 656 657 static void integratorcp_machine_init(MachineClass *mc) 658 { 659 mc->desc = "ARM Integrator/CP (ARM926EJ-S)"; 660 mc->init = integratorcp_init; 661 mc->ignore_memory_transaction_failures = true; 662 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 663 } 664 665 DEFINE_MACHINE("integratorcp", integratorcp_machine_init) 666 667 static Property core_properties[] = { 668 DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0), 669 DEFINE_PROP_END_OF_LIST(), 670 }; 671 672 static void core_class_init(ObjectClass *klass, void *data) 673 { 674 DeviceClass *dc = DEVICE_CLASS(klass); 675 676 dc->props = core_properties; 677 dc->realize = integratorcm_realize; 678 dc->vmsd = &vmstate_integratorcm; 679 } 680 681 static void icp_pic_class_init(ObjectClass *klass, void *data) 682 { 683 DeviceClass *dc = DEVICE_CLASS(klass); 684 685 dc->vmsd = &vmstate_icp_pic; 686 } 687 688 static void icp_control_class_init(ObjectClass *klass, void *data) 689 { 690 DeviceClass *dc = DEVICE_CLASS(klass); 691 692 dc->vmsd = &vmstate_icp_control; 693 } 694 695 static const TypeInfo core_info = { 696 .name = TYPE_INTEGRATOR_CM, 697 .parent = TYPE_SYS_BUS_DEVICE, 698 .instance_size = sizeof(IntegratorCMState), 699 .instance_init = integratorcm_init, 700 .class_init = core_class_init, 701 }; 702 703 static const TypeInfo icp_pic_info = { 704 .name = TYPE_INTEGRATOR_PIC, 705 .parent = TYPE_SYS_BUS_DEVICE, 706 .instance_size = sizeof(icp_pic_state), 707 .instance_init = icp_pic_init, 708 .class_init = icp_pic_class_init, 709 }; 710 711 static const TypeInfo icp_ctrl_regs_info = { 712 .name = TYPE_ICP_CONTROL_REGS, 713 .parent = TYPE_SYS_BUS_DEVICE, 714 .instance_size = sizeof(ICPCtrlRegsState), 715 .instance_init = icp_control_init, 716 .class_init = icp_control_class_init, 717 }; 718 719 static void integratorcp_register_types(void) 720 { 721 type_register_static(&icp_pic_info); 722 type_register_static(&core_info); 723 type_register_static(&icp_ctrl_regs_info); 724 } 725 726 type_init(integratorcp_register_types) 727