1 /* 2 * Calxeda Highbank SoC emulation 3 * 4 * Copyright (c) 2010-2012 Calxeda 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/sysbus.h" 22 #include "hw/arm/arm.h" 23 #include "hw/devices.h" 24 #include "hw/loader.h" 25 #include "net/net.h" 26 #include "sysemu/kvm.h" 27 #include "sysemu/sysemu.h" 28 #include "hw/boards.h" 29 #include "sysemu/block-backend.h" 30 #include "exec/address-spaces.h" 31 #include "qemu/error-report.h" 32 33 #define SMP_BOOT_ADDR 0x100 34 #define SMP_BOOT_REG 0x40 35 #define MPCORE_PERIPHBASE 0xfff10000 36 37 #define MVBAR_ADDR 0x200 38 39 #define NIRQ_GIC 160 40 41 /* Board init. */ 42 43 /* MVBAR_ADDR is limited by precision of movw */ 44 45 QEMU_BUILD_BUG_ON(MVBAR_ADDR >= (1 << 16)); 46 47 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \ 48 extract32((x), 12, 4) << 16) 49 50 static void hb_write_board_setup(ARMCPU *cpu, 51 const struct arm_boot_info *info) 52 { 53 int n; 54 uint32_t board_setup_blob[] = { 55 /* MVBAR_ADDR */ 56 /* Default unimplemented and unused vectors to spin. Makes it 57 * easier to debug (as opposed to the CPU running away). 58 */ 59 0xeafffffe, /* notused1: b notused */ 60 0xeafffffe, /* notused2: b notused */ 61 0xe1b0f00e, /* smc: movs pc, lr - exception return */ 62 0xeafffffe, /* prefetch_abort: b prefetch_abort */ 63 0xeafffffe, /* data_abort: b data_abort */ 64 0xeafffffe, /* notused3: b notused3 */ 65 0xeafffffe, /* irq: b irq */ 66 0xeafffffe, /* fiq: b fiq */ 67 #define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t)) 68 0xe3000000 + ARMV7_IMM16(MVBAR_ADDR), /* movw r0, MVBAR_ADDR */ 69 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 - set MVBAR */ 70 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 - get SCR */ 71 0xe3810001, /* orr r0, #1 - set NS */ 72 0xee010f11, /* mcr p15, 0, r0, c1 , c1, 0 - set SCR */ 73 0xe1600070, /* smc - go to monitor mode to flush NS change */ 74 0xe12fff1e, /* bx lr - return to caller */ 75 }; 76 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 77 board_setup_blob[n] = tswap32(board_setup_blob[n]); 78 } 79 rom_add_blob_fixed("board-setup", board_setup_blob, 80 sizeof(board_setup_blob), MVBAR_ADDR); 81 } 82 83 static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 84 { 85 int n; 86 uint32_t smpboot[] = { 87 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */ 88 0xe210000f, /* ands r0, r0, #0x0f */ 89 0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */ 90 0xe0830200, /* add r0, r3, r0, lsl #4 */ 91 0xe59f2024, /* ldr r2, privbase */ 92 0xe3a01001, /* mov r1, #1 */ 93 0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */ 94 0xe3a010ff, /* mov r1, #0xff */ 95 0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */ 96 0xf57ff04f, /* dsb */ 97 0xe320f003, /* wfi */ 98 0xe5901000, /* ldr r1, [r0] */ 99 0xe1110001, /* tst r1, r1 */ 100 0x0afffffb, /* beq <wfi> */ 101 0xe12fff11, /* bx r1 */ 102 MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */ 103 }; 104 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 105 smpboot[n] = tswap32(smpboot[n]); 106 } 107 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR); 108 } 109 110 static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 111 { 112 CPUARMState *env = &cpu->env; 113 114 switch (info->nb_cpus) { 115 case 4: 116 address_space_stl_notdirty(&address_space_memory, 117 SMP_BOOT_REG + 0x30, 0, 118 MEMTXATTRS_UNSPECIFIED, NULL); 119 case 3: 120 address_space_stl_notdirty(&address_space_memory, 121 SMP_BOOT_REG + 0x20, 0, 122 MEMTXATTRS_UNSPECIFIED, NULL); 123 case 2: 124 address_space_stl_notdirty(&address_space_memory, 125 SMP_BOOT_REG + 0x10, 0, 126 MEMTXATTRS_UNSPECIFIED, NULL); 127 env->regs[15] = SMP_BOOT_ADDR; 128 break; 129 default: 130 break; 131 } 132 } 133 134 #define NUM_REGS 0x200 135 static void hb_regs_write(void *opaque, hwaddr offset, 136 uint64_t value, unsigned size) 137 { 138 uint32_t *regs = opaque; 139 140 if (offset == 0xf00) { 141 if (value == 1 || value == 2) { 142 qemu_system_reset_request(); 143 } else if (value == 3) { 144 qemu_system_shutdown_request(); 145 } 146 } 147 148 regs[offset/4] = value; 149 } 150 151 static uint64_t hb_regs_read(void *opaque, hwaddr offset, 152 unsigned size) 153 { 154 uint32_t *regs = opaque; 155 uint32_t value = regs[offset/4]; 156 157 if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) { 158 value |= 0x30000000; 159 } 160 161 return value; 162 } 163 164 static const MemoryRegionOps hb_mem_ops = { 165 .read = hb_regs_read, 166 .write = hb_regs_write, 167 .endianness = DEVICE_NATIVE_ENDIAN, 168 }; 169 170 #define TYPE_HIGHBANK_REGISTERS "highbank-regs" 171 #define HIGHBANK_REGISTERS(obj) \ 172 OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS) 173 174 typedef struct { 175 /*< private >*/ 176 SysBusDevice parent_obj; 177 /*< public >*/ 178 179 MemoryRegion iomem; 180 uint32_t regs[NUM_REGS]; 181 } HighbankRegsState; 182 183 static VMStateDescription vmstate_highbank_regs = { 184 .name = "highbank-regs", 185 .version_id = 0, 186 .minimum_version_id = 0, 187 .fields = (VMStateField[]) { 188 VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS), 189 VMSTATE_END_OF_LIST(), 190 }, 191 }; 192 193 static void highbank_regs_reset(DeviceState *dev) 194 { 195 HighbankRegsState *s = HIGHBANK_REGISTERS(dev); 196 197 s->regs[0x40] = 0x05F20121; 198 s->regs[0x41] = 0x2; 199 s->regs[0x42] = 0x05F30121; 200 s->regs[0x43] = 0x05F40121; 201 } 202 203 static int highbank_regs_init(SysBusDevice *dev) 204 { 205 HighbankRegsState *s = HIGHBANK_REGISTERS(dev); 206 207 memory_region_init_io(&s->iomem, OBJECT(s), &hb_mem_ops, s->regs, 208 "highbank_regs", 0x1000); 209 sysbus_init_mmio(dev, &s->iomem); 210 211 return 0; 212 } 213 214 static void highbank_regs_class_init(ObjectClass *klass, void *data) 215 { 216 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); 217 DeviceClass *dc = DEVICE_CLASS(klass); 218 219 sbc->init = highbank_regs_init; 220 dc->desc = "Calxeda Highbank registers"; 221 dc->vmsd = &vmstate_highbank_regs; 222 dc->reset = highbank_regs_reset; 223 } 224 225 static const TypeInfo highbank_regs_info = { 226 .name = TYPE_HIGHBANK_REGISTERS, 227 .parent = TYPE_SYS_BUS_DEVICE, 228 .instance_size = sizeof(HighbankRegsState), 229 .class_init = highbank_regs_class_init, 230 }; 231 232 static void highbank_regs_register_types(void) 233 { 234 type_register_static(&highbank_regs_info); 235 } 236 237 type_init(highbank_regs_register_types) 238 239 static struct arm_boot_info highbank_binfo; 240 241 enum cxmachines { 242 CALXEDA_HIGHBANK, 243 CALXEDA_MIDWAY, 244 }; 245 246 /* ram_size must be set to match the upper bound of memory in the 247 * device tree (linux/arch/arm/boot/dts/highbank.dts), which is 248 * normally 0xff900000 or -m 4089. When running this board on a 249 * 32-bit host, set the reg value of memory to 0xf7ff00000 in the 250 * device tree and pass -m 2047 to QEMU. 251 */ 252 static void calxeda_init(MachineState *machine, enum cxmachines machine_id) 253 { 254 ram_addr_t ram_size = machine->ram_size; 255 const char *cpu_model = machine->cpu_model; 256 const char *kernel_filename = machine->kernel_filename; 257 const char *kernel_cmdline = machine->kernel_cmdline; 258 const char *initrd_filename = machine->initrd_filename; 259 DeviceState *dev = NULL; 260 SysBusDevice *busdev; 261 qemu_irq pic[128]; 262 int n; 263 qemu_irq cpu_irq[4]; 264 qemu_irq cpu_fiq[4]; 265 MemoryRegion *sysram; 266 MemoryRegion *dram; 267 MemoryRegion *sysmem; 268 char *sysboot_filename; 269 270 switch (machine_id) { 271 case CALXEDA_HIGHBANK: 272 cpu_model = "cortex-a9"; 273 break; 274 case CALXEDA_MIDWAY: 275 cpu_model = "cortex-a15"; 276 break; 277 } 278 279 for (n = 0; n < smp_cpus; n++) { 280 ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 281 Object *cpuobj; 282 ARMCPU *cpu; 283 284 cpuobj = object_new(object_class_get_name(oc)); 285 cpu = ARM_CPU(cpuobj); 286 287 object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC, 288 "psci-conduit", &error_abort); 289 290 if (n) { 291 /* Secondary CPUs start in PSCI powered-down state */ 292 object_property_set_bool(cpuobj, true, 293 "start-powered-off", &error_abort); 294 } 295 296 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 297 object_property_set_int(cpuobj, MPCORE_PERIPHBASE, 298 "reset-cbar", &error_abort); 299 } 300 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 301 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ); 302 cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ); 303 } 304 305 sysmem = get_system_memory(); 306 dram = g_new(MemoryRegion, 1); 307 memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size); 308 /* SDRAM at address zero. */ 309 memory_region_add_subregion(sysmem, 0, dram); 310 311 sysram = g_new(MemoryRegion, 1); 312 memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000, 313 &error_fatal); 314 memory_region_add_subregion(sysmem, 0xfff88000, sysram); 315 if (bios_name != NULL) { 316 sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 317 if (sysboot_filename != NULL) { 318 if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) { 319 error_report("Unable to load %s", bios_name); 320 exit(1); 321 } 322 g_free(sysboot_filename); 323 } else { 324 error_report("Unable to find %s", bios_name); 325 exit(1); 326 } 327 } 328 329 switch (machine_id) { 330 case CALXEDA_HIGHBANK: 331 dev = qdev_create(NULL, "l2x0"); 332 qdev_init_nofail(dev); 333 busdev = SYS_BUS_DEVICE(dev); 334 sysbus_mmio_map(busdev, 0, 0xfff12000); 335 336 dev = qdev_create(NULL, "a9mpcore_priv"); 337 break; 338 case CALXEDA_MIDWAY: 339 dev = qdev_create(NULL, "a15mpcore_priv"); 340 break; 341 } 342 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 343 qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC); 344 qdev_init_nofail(dev); 345 busdev = SYS_BUS_DEVICE(dev); 346 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); 347 for (n = 0; n < smp_cpus; n++) { 348 sysbus_connect_irq(busdev, n, cpu_irq[n]); 349 sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]); 350 } 351 352 for (n = 0; n < 128; n++) { 353 pic[n] = qdev_get_gpio_in(dev, n); 354 } 355 356 dev = qdev_create(NULL, "sp804"); 357 qdev_prop_set_uint32(dev, "freq0", 150000000); 358 qdev_prop_set_uint32(dev, "freq1", 150000000); 359 qdev_init_nofail(dev); 360 busdev = SYS_BUS_DEVICE(dev); 361 sysbus_mmio_map(busdev, 0, 0xfff34000); 362 sysbus_connect_irq(busdev, 0, pic[18]); 363 sysbus_create_simple("pl011", 0xfff36000, pic[20]); 364 365 dev = qdev_create(NULL, "highbank-regs"); 366 qdev_init_nofail(dev); 367 busdev = SYS_BUS_DEVICE(dev); 368 sysbus_mmio_map(busdev, 0, 0xfff3c000); 369 370 sysbus_create_simple("pl061", 0xfff30000, pic[14]); 371 sysbus_create_simple("pl061", 0xfff31000, pic[15]); 372 sysbus_create_simple("pl061", 0xfff32000, pic[16]); 373 sysbus_create_simple("pl061", 0xfff33000, pic[17]); 374 sysbus_create_simple("pl031", 0xfff35000, pic[19]); 375 sysbus_create_simple("pl022", 0xfff39000, pic[23]); 376 377 sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]); 378 379 if (nd_table[0].used) { 380 qemu_check_nic_model(&nd_table[0], "xgmac"); 381 dev = qdev_create(NULL, "xgmac"); 382 qdev_set_nic_properties(dev, &nd_table[0]); 383 qdev_init_nofail(dev); 384 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000); 385 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]); 386 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]); 387 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]); 388 389 qemu_check_nic_model(&nd_table[1], "xgmac"); 390 dev = qdev_create(NULL, "xgmac"); 391 qdev_set_nic_properties(dev, &nd_table[1]); 392 qdev_init_nofail(dev); 393 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000); 394 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]); 395 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]); 396 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]); 397 } 398 399 highbank_binfo.ram_size = ram_size; 400 highbank_binfo.kernel_filename = kernel_filename; 401 highbank_binfo.kernel_cmdline = kernel_cmdline; 402 highbank_binfo.initrd_filename = initrd_filename; 403 /* highbank requires a dtb in order to boot, and the dtb will override 404 * the board ID. The following value is ignored, so set it to -1 to be 405 * clear that the value is meaningless. 406 */ 407 highbank_binfo.board_id = -1; 408 highbank_binfo.nb_cpus = smp_cpus; 409 highbank_binfo.loader_start = 0; 410 highbank_binfo.write_secondary_boot = hb_write_secondary; 411 highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary; 412 if (!kvm_enabled()) { 413 highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR; 414 highbank_binfo.write_board_setup = hb_write_board_setup; 415 highbank_binfo.secure_board_setup = true; 416 } else { 417 error_report("WARNING: cannot load built-in Monitor support " 418 "if KVM is enabled. Some guests (such as Linux) " 419 "may not boot."); 420 } 421 422 arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo); 423 } 424 425 static void highbank_init(MachineState *machine) 426 { 427 calxeda_init(machine, CALXEDA_HIGHBANK); 428 } 429 430 static void midway_init(MachineState *machine) 431 { 432 calxeda_init(machine, CALXEDA_MIDWAY); 433 } 434 435 static void highbank_class_init(ObjectClass *oc, void *data) 436 { 437 MachineClass *mc = MACHINE_CLASS(oc); 438 439 mc->desc = "Calxeda Highbank (ECX-1000)"; 440 mc->init = highbank_init; 441 mc->block_default_type = IF_SCSI; 442 mc->max_cpus = 4; 443 } 444 445 static const TypeInfo highbank_type = { 446 .name = MACHINE_TYPE_NAME("highbank"), 447 .parent = TYPE_MACHINE, 448 .class_init = highbank_class_init, 449 }; 450 451 static void midway_class_init(ObjectClass *oc, void *data) 452 { 453 MachineClass *mc = MACHINE_CLASS(oc); 454 455 mc->desc = "Calxeda Midway (ECX-2000)"; 456 mc->init = midway_init; 457 mc->block_default_type = IF_SCSI; 458 mc->max_cpus = 4; 459 } 460 461 static const TypeInfo midway_type = { 462 .name = MACHINE_TYPE_NAME("midway"), 463 .parent = TYPE_MACHINE, 464 .class_init = midway_class_init, 465 }; 466 467 static void calxeda_machines_init(void) 468 { 469 type_register_static(&highbank_type); 470 type_register_static(&midway_type); 471 } 472 473 machine_init(calxeda_machines_init) 474