1 /* 2 * Calxeda Highbank SoC emulation 3 * 4 * Copyright (c) 2010-2012 Calxeda 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 */ 19 20 #include "hw/sysbus.h" 21 #include "hw/arm/arm.h" 22 #include "hw/devices.h" 23 #include "hw/loader.h" 24 #include "net/net.h" 25 #include "sysemu/sysemu.h" 26 #include "hw/boards.h" 27 #include "sysemu/blockdev.h" 28 #include "exec/address-spaces.h" 29 #include "qemu/error-report.h" 30 31 #define SMP_BOOT_ADDR 0x100 32 #define SMP_BOOT_REG 0x40 33 #define MPCORE_PERIPHBASE 0xfff10000 34 35 #define NIRQ_GIC 160 36 37 /* Board init. */ 38 39 static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 40 { 41 int n; 42 uint32_t smpboot[] = { 43 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */ 44 0xe210000f, /* ands r0, r0, #0x0f */ 45 0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */ 46 0xe0830200, /* add r0, r3, r0, lsl #4 */ 47 0xe59f2024, /* ldr r2, privbase */ 48 0xe3a01001, /* mov r1, #1 */ 49 0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */ 50 0xe3a010ff, /* mov r1, #0xff */ 51 0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */ 52 0xf57ff04f, /* dsb */ 53 0xe320f003, /* wfi */ 54 0xe5901000, /* ldr r1, [r0] */ 55 0xe1110001, /* tst r1, r1 */ 56 0x0afffffb, /* beq <wfi> */ 57 0xe12fff11, /* bx r1 */ 58 MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */ 59 }; 60 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 61 smpboot[n] = tswap32(smpboot[n]); 62 } 63 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR); 64 } 65 66 static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 67 { 68 CPUARMState *env = &cpu->env; 69 70 switch (info->nb_cpus) { 71 case 4: 72 stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x30, 0); 73 case 3: 74 stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x20, 0); 75 case 2: 76 stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x10, 0); 77 env->regs[15] = SMP_BOOT_ADDR; 78 break; 79 default: 80 break; 81 } 82 } 83 84 #define NUM_REGS 0x200 85 static void hb_regs_write(void *opaque, hwaddr offset, 86 uint64_t value, unsigned size) 87 { 88 uint32_t *regs = opaque; 89 90 if (offset == 0xf00) { 91 if (value == 1 || value == 2) { 92 qemu_system_reset_request(); 93 } else if (value == 3) { 94 qemu_system_shutdown_request(); 95 } 96 } 97 98 regs[offset/4] = value; 99 } 100 101 static uint64_t hb_regs_read(void *opaque, hwaddr offset, 102 unsigned size) 103 { 104 uint32_t *regs = opaque; 105 uint32_t value = regs[offset/4]; 106 107 if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) { 108 value |= 0x30000000; 109 } 110 111 return value; 112 } 113 114 static const MemoryRegionOps hb_mem_ops = { 115 .read = hb_regs_read, 116 .write = hb_regs_write, 117 .endianness = DEVICE_NATIVE_ENDIAN, 118 }; 119 120 #define TYPE_HIGHBANK_REGISTERS "highbank-regs" 121 #define HIGHBANK_REGISTERS(obj) \ 122 OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS) 123 124 typedef struct { 125 /*< private >*/ 126 SysBusDevice parent_obj; 127 /*< public >*/ 128 129 MemoryRegion iomem; 130 uint32_t regs[NUM_REGS]; 131 } HighbankRegsState; 132 133 static VMStateDescription vmstate_highbank_regs = { 134 .name = "highbank-regs", 135 .version_id = 0, 136 .minimum_version_id = 0, 137 .minimum_version_id_old = 0, 138 .fields = (VMStateField[]) { 139 VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS), 140 VMSTATE_END_OF_LIST(), 141 }, 142 }; 143 144 static void highbank_regs_reset(DeviceState *dev) 145 { 146 HighbankRegsState *s = HIGHBANK_REGISTERS(dev); 147 148 s->regs[0x40] = 0x05F20121; 149 s->regs[0x41] = 0x2; 150 s->regs[0x42] = 0x05F30121; 151 s->regs[0x43] = 0x05F40121; 152 } 153 154 static int highbank_regs_init(SysBusDevice *dev) 155 { 156 HighbankRegsState *s = HIGHBANK_REGISTERS(dev); 157 158 memory_region_init_io(&s->iomem, OBJECT(s), &hb_mem_ops, s->regs, 159 "highbank_regs", 0x1000); 160 sysbus_init_mmio(dev, &s->iomem); 161 162 return 0; 163 } 164 165 static void highbank_regs_class_init(ObjectClass *klass, void *data) 166 { 167 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); 168 DeviceClass *dc = DEVICE_CLASS(klass); 169 170 sbc->init = highbank_regs_init; 171 dc->desc = "Calxeda Highbank registers"; 172 dc->vmsd = &vmstate_highbank_regs; 173 dc->reset = highbank_regs_reset; 174 } 175 176 static const TypeInfo highbank_regs_info = { 177 .name = TYPE_HIGHBANK_REGISTERS, 178 .parent = TYPE_SYS_BUS_DEVICE, 179 .instance_size = sizeof(HighbankRegsState), 180 .class_init = highbank_regs_class_init, 181 }; 182 183 static void highbank_regs_register_types(void) 184 { 185 type_register_static(&highbank_regs_info); 186 } 187 188 type_init(highbank_regs_register_types) 189 190 static struct arm_boot_info highbank_binfo; 191 192 enum cxmachines { 193 CALXEDA_HIGHBANK, 194 CALXEDA_MIDWAY, 195 }; 196 197 /* ram_size must be set to match the upper bound of memory in the 198 * device tree (linux/arch/arm/boot/dts/highbank.dts), which is 199 * normally 0xff900000 or -m 4089. When running this board on a 200 * 32-bit host, set the reg value of memory to 0xf7ff00000 in the 201 * device tree and pass -m 2047 to QEMU. 202 */ 203 static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine) 204 { 205 ram_addr_t ram_size = args->ram_size; 206 const char *cpu_model = args->cpu_model; 207 const char *kernel_filename = args->kernel_filename; 208 const char *kernel_cmdline = args->kernel_cmdline; 209 const char *initrd_filename = args->initrd_filename; 210 DeviceState *dev = NULL; 211 SysBusDevice *busdev; 212 qemu_irq pic[128]; 213 int n; 214 qemu_irq cpu_irq[4]; 215 MemoryRegion *sysram; 216 MemoryRegion *dram; 217 MemoryRegion *sysmem; 218 char *sysboot_filename; 219 220 if (!cpu_model) { 221 switch (machine) { 222 case CALXEDA_HIGHBANK: 223 cpu_model = "cortex-a9"; 224 break; 225 case CALXEDA_MIDWAY: 226 cpu_model = "cortex-a15"; 227 break; 228 } 229 } 230 231 for (n = 0; n < smp_cpus; n++) { 232 ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 233 Object *cpuobj; 234 ARMCPU *cpu; 235 Error *err = NULL; 236 237 if (!oc) { 238 error_report("Unable to find CPU definition"); 239 exit(1); 240 } 241 242 cpuobj = object_new(object_class_get_name(oc)); 243 cpu = ARM_CPU(cpuobj); 244 245 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 246 object_property_set_int(cpuobj, MPCORE_PERIPHBASE, 247 "reset-cbar", &error_abort); 248 } 249 object_property_set_bool(cpuobj, true, "realized", &err); 250 if (err) { 251 error_report("%s", error_get_pretty(err)); 252 exit(1); 253 } 254 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ); 255 } 256 257 sysmem = get_system_memory(); 258 dram = g_new(MemoryRegion, 1); 259 memory_region_init_ram(dram, NULL, "highbank.dram", ram_size); 260 /* SDRAM at address zero. */ 261 memory_region_add_subregion(sysmem, 0, dram); 262 263 sysram = g_new(MemoryRegion, 1); 264 memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000); 265 memory_region_add_subregion(sysmem, 0xfff88000, sysram); 266 if (bios_name != NULL) { 267 sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 268 if (sysboot_filename != NULL) { 269 uint32_t filesize = get_image_size(sysboot_filename); 270 if (load_image_targphys("sysram.bin", 0xfff88000, filesize) < 0) { 271 hw_error("Unable to load %s\n", bios_name); 272 } 273 } else { 274 hw_error("Unable to find %s\n", bios_name); 275 } 276 } 277 278 switch (machine) { 279 case CALXEDA_HIGHBANK: 280 dev = qdev_create(NULL, "l2x0"); 281 qdev_init_nofail(dev); 282 busdev = SYS_BUS_DEVICE(dev); 283 sysbus_mmio_map(busdev, 0, 0xfff12000); 284 285 dev = qdev_create(NULL, "a9mpcore_priv"); 286 break; 287 case CALXEDA_MIDWAY: 288 dev = qdev_create(NULL, "a15mpcore_priv"); 289 break; 290 } 291 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 292 qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC); 293 qdev_init_nofail(dev); 294 busdev = SYS_BUS_DEVICE(dev); 295 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); 296 for (n = 0; n < smp_cpus; n++) { 297 sysbus_connect_irq(busdev, n, cpu_irq[n]); 298 } 299 300 for (n = 0; n < 128; n++) { 301 pic[n] = qdev_get_gpio_in(dev, n); 302 } 303 304 dev = qdev_create(NULL, "sp804"); 305 qdev_prop_set_uint32(dev, "freq0", 150000000); 306 qdev_prop_set_uint32(dev, "freq1", 150000000); 307 qdev_init_nofail(dev); 308 busdev = SYS_BUS_DEVICE(dev); 309 sysbus_mmio_map(busdev, 0, 0xfff34000); 310 sysbus_connect_irq(busdev, 0, pic[18]); 311 sysbus_create_simple("pl011", 0xfff36000, pic[20]); 312 313 dev = qdev_create(NULL, "highbank-regs"); 314 qdev_init_nofail(dev); 315 busdev = SYS_BUS_DEVICE(dev); 316 sysbus_mmio_map(busdev, 0, 0xfff3c000); 317 318 sysbus_create_simple("pl061", 0xfff30000, pic[14]); 319 sysbus_create_simple("pl061", 0xfff31000, pic[15]); 320 sysbus_create_simple("pl061", 0xfff32000, pic[16]); 321 sysbus_create_simple("pl061", 0xfff33000, pic[17]); 322 sysbus_create_simple("pl031", 0xfff35000, pic[19]); 323 sysbus_create_simple("pl022", 0xfff39000, pic[23]); 324 325 sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]); 326 327 if (nd_table[0].used) { 328 qemu_check_nic_model(&nd_table[0], "xgmac"); 329 dev = qdev_create(NULL, "xgmac"); 330 qdev_set_nic_properties(dev, &nd_table[0]); 331 qdev_init_nofail(dev); 332 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000); 333 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]); 334 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]); 335 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]); 336 337 qemu_check_nic_model(&nd_table[1], "xgmac"); 338 dev = qdev_create(NULL, "xgmac"); 339 qdev_set_nic_properties(dev, &nd_table[1]); 340 qdev_init_nofail(dev); 341 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000); 342 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]); 343 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]); 344 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]); 345 } 346 347 highbank_binfo.ram_size = ram_size; 348 highbank_binfo.kernel_filename = kernel_filename; 349 highbank_binfo.kernel_cmdline = kernel_cmdline; 350 highbank_binfo.initrd_filename = initrd_filename; 351 /* highbank requires a dtb in order to boot, and the dtb will override 352 * the board ID. The following value is ignored, so set it to -1 to be 353 * clear that the value is meaningless. 354 */ 355 highbank_binfo.board_id = -1; 356 highbank_binfo.nb_cpus = smp_cpus; 357 highbank_binfo.loader_start = 0; 358 highbank_binfo.write_secondary_boot = hb_write_secondary; 359 highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary; 360 arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo); 361 } 362 363 static void highbank_init(QEMUMachineInitArgs *args) 364 { 365 calxeda_init(args, CALXEDA_HIGHBANK); 366 } 367 368 static void midway_init(QEMUMachineInitArgs *args) 369 { 370 calxeda_init(args, CALXEDA_MIDWAY); 371 } 372 373 static QEMUMachine highbank_machine = { 374 .name = "highbank", 375 .desc = "Calxeda Highbank (ECX-1000)", 376 .init = highbank_init, 377 .block_default_type = IF_SCSI, 378 .max_cpus = 4, 379 }; 380 381 static QEMUMachine midway_machine = { 382 .name = "midway", 383 .desc = "Calxeda Midway (ECX-2000)", 384 .init = midway_init, 385 .block_default_type = IF_SCSI, 386 .max_cpus = 4, 387 }; 388 389 static void calxeda_machines_init(void) 390 { 391 qemu_register_machine(&highbank_machine); 392 qemu_register_machine(&midway_machine); 393 } 394 395 machine_init(calxeda_machines_init); 396