1 /* 2 * Calxeda Highbank SoC emulation 3 * 4 * Copyright (c) 2010-2012 Calxeda 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 */ 19 20 #include "hw/sysbus.h" 21 #include "hw/arm/arm.h" 22 #include "hw/devices.h" 23 #include "hw/loader.h" 24 #include "net/net.h" 25 #include "sysemu/kvm.h" 26 #include "sysemu/sysemu.h" 27 #include "hw/boards.h" 28 #include "sysemu/block-backend.h" 29 #include "exec/address-spaces.h" 30 #include "qemu/error-report.h" 31 32 #define SMP_BOOT_ADDR 0x100 33 #define SMP_BOOT_REG 0x40 34 #define MPCORE_PERIPHBASE 0xfff10000 35 36 #define MVBAR_ADDR 0x200 37 38 #define NIRQ_GIC 160 39 40 /* Board init. */ 41 42 /* MVBAR_ADDR is limited by precision of movw */ 43 44 QEMU_BUILD_BUG_ON(MVBAR_ADDR >= (1 << 16)); 45 46 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \ 47 extract32((x), 12, 4) << 16) 48 49 static void hb_write_board_setup(ARMCPU *cpu, 50 const struct arm_boot_info *info) 51 { 52 int n; 53 uint32_t board_setup_blob[] = { 54 /* MVBAR_ADDR */ 55 /* Default unimplemented and unused vectors to spin. Makes it 56 * easier to debug (as opposed to the CPU running away). 57 */ 58 0xeafffffe, /* notused1: b notused */ 59 0xeafffffe, /* notused2: b notused */ 60 0xe1b0f00e, /* smc: movs pc, lr - exception return */ 61 0xeafffffe, /* prefetch_abort: b prefetch_abort */ 62 0xeafffffe, /* data_abort: b data_abort */ 63 0xeafffffe, /* notused3: b notused3 */ 64 0xeafffffe, /* irq: b irq */ 65 0xeafffffe, /* fiq: b fiq */ 66 #define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t)) 67 0xe3000000 + ARMV7_IMM16(MVBAR_ADDR), /* movw r0, MVBAR_ADDR */ 68 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 - set MVBAR */ 69 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 - get SCR */ 70 0xe3810001, /* orr r0, #1 - set NS */ 71 0xee010f11, /* mcr p15, 0, r0, c1 , c1, 0 - set SCR */ 72 0xe1600070, /* smc - go to monitor mode to flush NS change */ 73 0xe12fff1e, /* bx lr - return to caller */ 74 }; 75 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 76 board_setup_blob[n] = tswap32(board_setup_blob[n]); 77 } 78 rom_add_blob_fixed("board-setup", board_setup_blob, 79 sizeof(board_setup_blob), MVBAR_ADDR); 80 } 81 82 static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 83 { 84 int n; 85 uint32_t smpboot[] = { 86 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */ 87 0xe210000f, /* ands r0, r0, #0x0f */ 88 0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */ 89 0xe0830200, /* add r0, r3, r0, lsl #4 */ 90 0xe59f2024, /* ldr r2, privbase */ 91 0xe3a01001, /* mov r1, #1 */ 92 0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */ 93 0xe3a010ff, /* mov r1, #0xff */ 94 0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */ 95 0xf57ff04f, /* dsb */ 96 0xe320f003, /* wfi */ 97 0xe5901000, /* ldr r1, [r0] */ 98 0xe1110001, /* tst r1, r1 */ 99 0x0afffffb, /* beq <wfi> */ 100 0xe12fff11, /* bx r1 */ 101 MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */ 102 }; 103 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 104 smpboot[n] = tswap32(smpboot[n]); 105 } 106 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR); 107 } 108 109 static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 110 { 111 CPUARMState *env = &cpu->env; 112 113 switch (info->nb_cpus) { 114 case 4: 115 address_space_stl_notdirty(&address_space_memory, 116 SMP_BOOT_REG + 0x30, 0, 117 MEMTXATTRS_UNSPECIFIED, NULL); 118 case 3: 119 address_space_stl_notdirty(&address_space_memory, 120 SMP_BOOT_REG + 0x20, 0, 121 MEMTXATTRS_UNSPECIFIED, NULL); 122 case 2: 123 address_space_stl_notdirty(&address_space_memory, 124 SMP_BOOT_REG + 0x10, 0, 125 MEMTXATTRS_UNSPECIFIED, NULL); 126 env->regs[15] = SMP_BOOT_ADDR; 127 break; 128 default: 129 break; 130 } 131 } 132 133 #define NUM_REGS 0x200 134 static void hb_regs_write(void *opaque, hwaddr offset, 135 uint64_t value, unsigned size) 136 { 137 uint32_t *regs = opaque; 138 139 if (offset == 0xf00) { 140 if (value == 1 || value == 2) { 141 qemu_system_reset_request(); 142 } else if (value == 3) { 143 qemu_system_shutdown_request(); 144 } 145 } 146 147 regs[offset/4] = value; 148 } 149 150 static uint64_t hb_regs_read(void *opaque, hwaddr offset, 151 unsigned size) 152 { 153 uint32_t *regs = opaque; 154 uint32_t value = regs[offset/4]; 155 156 if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) { 157 value |= 0x30000000; 158 } 159 160 return value; 161 } 162 163 static const MemoryRegionOps hb_mem_ops = { 164 .read = hb_regs_read, 165 .write = hb_regs_write, 166 .endianness = DEVICE_NATIVE_ENDIAN, 167 }; 168 169 #define TYPE_HIGHBANK_REGISTERS "highbank-regs" 170 #define HIGHBANK_REGISTERS(obj) \ 171 OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS) 172 173 typedef struct { 174 /*< private >*/ 175 SysBusDevice parent_obj; 176 /*< public >*/ 177 178 MemoryRegion iomem; 179 uint32_t regs[NUM_REGS]; 180 } HighbankRegsState; 181 182 static VMStateDescription vmstate_highbank_regs = { 183 .name = "highbank-regs", 184 .version_id = 0, 185 .minimum_version_id = 0, 186 .fields = (VMStateField[]) { 187 VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS), 188 VMSTATE_END_OF_LIST(), 189 }, 190 }; 191 192 static void highbank_regs_reset(DeviceState *dev) 193 { 194 HighbankRegsState *s = HIGHBANK_REGISTERS(dev); 195 196 s->regs[0x40] = 0x05F20121; 197 s->regs[0x41] = 0x2; 198 s->regs[0x42] = 0x05F30121; 199 s->regs[0x43] = 0x05F40121; 200 } 201 202 static int highbank_regs_init(SysBusDevice *dev) 203 { 204 HighbankRegsState *s = HIGHBANK_REGISTERS(dev); 205 206 memory_region_init_io(&s->iomem, OBJECT(s), &hb_mem_ops, s->regs, 207 "highbank_regs", 0x1000); 208 sysbus_init_mmio(dev, &s->iomem); 209 210 return 0; 211 } 212 213 static void highbank_regs_class_init(ObjectClass *klass, void *data) 214 { 215 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); 216 DeviceClass *dc = DEVICE_CLASS(klass); 217 218 sbc->init = highbank_regs_init; 219 dc->desc = "Calxeda Highbank registers"; 220 dc->vmsd = &vmstate_highbank_regs; 221 dc->reset = highbank_regs_reset; 222 } 223 224 static const TypeInfo highbank_regs_info = { 225 .name = TYPE_HIGHBANK_REGISTERS, 226 .parent = TYPE_SYS_BUS_DEVICE, 227 .instance_size = sizeof(HighbankRegsState), 228 .class_init = highbank_regs_class_init, 229 }; 230 231 static void highbank_regs_register_types(void) 232 { 233 type_register_static(&highbank_regs_info); 234 } 235 236 type_init(highbank_regs_register_types) 237 238 static struct arm_boot_info highbank_binfo; 239 240 enum cxmachines { 241 CALXEDA_HIGHBANK, 242 CALXEDA_MIDWAY, 243 }; 244 245 /* ram_size must be set to match the upper bound of memory in the 246 * device tree (linux/arch/arm/boot/dts/highbank.dts), which is 247 * normally 0xff900000 or -m 4089. When running this board on a 248 * 32-bit host, set the reg value of memory to 0xf7ff00000 in the 249 * device tree and pass -m 2047 to QEMU. 250 */ 251 static void calxeda_init(MachineState *machine, enum cxmachines machine_id) 252 { 253 ram_addr_t ram_size = machine->ram_size; 254 const char *cpu_model = machine->cpu_model; 255 const char *kernel_filename = machine->kernel_filename; 256 const char *kernel_cmdline = machine->kernel_cmdline; 257 const char *initrd_filename = machine->initrd_filename; 258 DeviceState *dev = NULL; 259 SysBusDevice *busdev; 260 qemu_irq pic[128]; 261 int n; 262 qemu_irq cpu_irq[4]; 263 qemu_irq cpu_fiq[4]; 264 MemoryRegion *sysram; 265 MemoryRegion *dram; 266 MemoryRegion *sysmem; 267 char *sysboot_filename; 268 269 switch (machine_id) { 270 case CALXEDA_HIGHBANK: 271 cpu_model = "cortex-a9"; 272 break; 273 case CALXEDA_MIDWAY: 274 cpu_model = "cortex-a15"; 275 break; 276 } 277 278 for (n = 0; n < smp_cpus; n++) { 279 ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 280 Object *cpuobj; 281 ARMCPU *cpu; 282 283 cpuobj = object_new(object_class_get_name(oc)); 284 cpu = ARM_CPU(cpuobj); 285 286 object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC, 287 "psci-conduit", &error_abort); 288 289 if (n) { 290 /* Secondary CPUs start in PSCI powered-down state */ 291 object_property_set_bool(cpuobj, true, 292 "start-powered-off", &error_abort); 293 } 294 295 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 296 object_property_set_int(cpuobj, MPCORE_PERIPHBASE, 297 "reset-cbar", &error_abort); 298 } 299 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 300 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ); 301 cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ); 302 } 303 304 sysmem = get_system_memory(); 305 dram = g_new(MemoryRegion, 1); 306 memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size); 307 /* SDRAM at address zero. */ 308 memory_region_add_subregion(sysmem, 0, dram); 309 310 sysram = g_new(MemoryRegion, 1); 311 memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000, 312 &error_fatal); 313 memory_region_add_subregion(sysmem, 0xfff88000, sysram); 314 if (bios_name != NULL) { 315 sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 316 if (sysboot_filename != NULL) { 317 if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) { 318 error_report("Unable to load %s", bios_name); 319 exit(1); 320 } 321 g_free(sysboot_filename); 322 } else { 323 error_report("Unable to find %s", bios_name); 324 exit(1); 325 } 326 } 327 328 switch (machine_id) { 329 case CALXEDA_HIGHBANK: 330 dev = qdev_create(NULL, "l2x0"); 331 qdev_init_nofail(dev); 332 busdev = SYS_BUS_DEVICE(dev); 333 sysbus_mmio_map(busdev, 0, 0xfff12000); 334 335 dev = qdev_create(NULL, "a9mpcore_priv"); 336 break; 337 case CALXEDA_MIDWAY: 338 dev = qdev_create(NULL, "a15mpcore_priv"); 339 break; 340 } 341 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 342 qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC); 343 qdev_init_nofail(dev); 344 busdev = SYS_BUS_DEVICE(dev); 345 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); 346 for (n = 0; n < smp_cpus; n++) { 347 sysbus_connect_irq(busdev, n, cpu_irq[n]); 348 sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]); 349 } 350 351 for (n = 0; n < 128; n++) { 352 pic[n] = qdev_get_gpio_in(dev, n); 353 } 354 355 dev = qdev_create(NULL, "sp804"); 356 qdev_prop_set_uint32(dev, "freq0", 150000000); 357 qdev_prop_set_uint32(dev, "freq1", 150000000); 358 qdev_init_nofail(dev); 359 busdev = SYS_BUS_DEVICE(dev); 360 sysbus_mmio_map(busdev, 0, 0xfff34000); 361 sysbus_connect_irq(busdev, 0, pic[18]); 362 sysbus_create_simple("pl011", 0xfff36000, pic[20]); 363 364 dev = qdev_create(NULL, "highbank-regs"); 365 qdev_init_nofail(dev); 366 busdev = SYS_BUS_DEVICE(dev); 367 sysbus_mmio_map(busdev, 0, 0xfff3c000); 368 369 sysbus_create_simple("pl061", 0xfff30000, pic[14]); 370 sysbus_create_simple("pl061", 0xfff31000, pic[15]); 371 sysbus_create_simple("pl061", 0xfff32000, pic[16]); 372 sysbus_create_simple("pl061", 0xfff33000, pic[17]); 373 sysbus_create_simple("pl031", 0xfff35000, pic[19]); 374 sysbus_create_simple("pl022", 0xfff39000, pic[23]); 375 376 sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]); 377 378 if (nd_table[0].used) { 379 qemu_check_nic_model(&nd_table[0], "xgmac"); 380 dev = qdev_create(NULL, "xgmac"); 381 qdev_set_nic_properties(dev, &nd_table[0]); 382 qdev_init_nofail(dev); 383 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000); 384 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]); 385 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]); 386 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]); 387 388 qemu_check_nic_model(&nd_table[1], "xgmac"); 389 dev = qdev_create(NULL, "xgmac"); 390 qdev_set_nic_properties(dev, &nd_table[1]); 391 qdev_init_nofail(dev); 392 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000); 393 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]); 394 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]); 395 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]); 396 } 397 398 highbank_binfo.ram_size = ram_size; 399 highbank_binfo.kernel_filename = kernel_filename; 400 highbank_binfo.kernel_cmdline = kernel_cmdline; 401 highbank_binfo.initrd_filename = initrd_filename; 402 /* highbank requires a dtb in order to boot, and the dtb will override 403 * the board ID. The following value is ignored, so set it to -1 to be 404 * clear that the value is meaningless. 405 */ 406 highbank_binfo.board_id = -1; 407 highbank_binfo.nb_cpus = smp_cpus; 408 highbank_binfo.loader_start = 0; 409 highbank_binfo.write_secondary_boot = hb_write_secondary; 410 highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary; 411 if (!kvm_enabled()) { 412 highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR; 413 highbank_binfo.write_board_setup = hb_write_board_setup; 414 highbank_binfo.secure_board_setup = true; 415 } else { 416 error_report("WARNING: cannot load built-in Monitor support " 417 "if KVM is enabled. Some guests (such as Linux) " 418 "may not boot."); 419 } 420 421 arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo); 422 } 423 424 static void highbank_init(MachineState *machine) 425 { 426 calxeda_init(machine, CALXEDA_HIGHBANK); 427 } 428 429 static void midway_init(MachineState *machine) 430 { 431 calxeda_init(machine, CALXEDA_MIDWAY); 432 } 433 434 static void highbank_class_init(ObjectClass *oc, void *data) 435 { 436 MachineClass *mc = MACHINE_CLASS(oc); 437 438 mc->desc = "Calxeda Highbank (ECX-1000)"; 439 mc->init = highbank_init; 440 mc->block_default_type = IF_SCSI; 441 mc->max_cpus = 4; 442 } 443 444 static const TypeInfo highbank_type = { 445 .name = MACHINE_TYPE_NAME("highbank"), 446 .parent = TYPE_MACHINE, 447 .class_init = highbank_class_init, 448 }; 449 450 static void midway_class_init(ObjectClass *oc, void *data) 451 { 452 MachineClass *mc = MACHINE_CLASS(oc); 453 454 mc->desc = "Calxeda Midway (ECX-2000)"; 455 mc->init = midway_init; 456 mc->block_default_type = IF_SCSI; 457 mc->max_cpus = 4; 458 } 459 460 static const TypeInfo midway_type = { 461 .name = MACHINE_TYPE_NAME("midway"), 462 .parent = TYPE_MACHINE, 463 .class_init = midway_class_init, 464 }; 465 466 static void calxeda_machines_init(void) 467 { 468 type_register_static(&highbank_type); 469 type_register_static(&midway_type); 470 } 471 472 machine_init(calxeda_machines_init) 473