1 /* 2 * Calxeda Highbank SoC emulation 3 * 4 * Copyright (c) 2010-2012 Calxeda 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "hw/sysbus.h" 23 #include "hw/arm/arm.h" 24 #include "hw/devices.h" 25 #include "hw/loader.h" 26 #include "net/net.h" 27 #include "sysemu/kvm.h" 28 #include "sysemu/sysemu.h" 29 #include "hw/boards.h" 30 #include "exec/address-spaces.h" 31 #include "qemu/error-report.h" 32 #include "hw/char/pl011.h" 33 #include "hw/ide/ahci.h" 34 #include "hw/cpu/a9mpcore.h" 35 #include "hw/cpu/a15mpcore.h" 36 #include "qemu/log.h" 37 38 #define SMP_BOOT_ADDR 0x100 39 #define SMP_BOOT_REG 0x40 40 #define MPCORE_PERIPHBASE 0xfff10000 41 42 #define MVBAR_ADDR 0x200 43 #define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t)) 44 45 #define NIRQ_GIC 160 46 47 /* Board init. */ 48 49 static void hb_write_board_setup(ARMCPU *cpu, 50 const struct arm_boot_info *info) 51 { 52 arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR); 53 } 54 55 static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 56 { 57 int n; 58 uint32_t smpboot[] = { 59 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */ 60 0xe210000f, /* ands r0, r0, #0x0f */ 61 0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */ 62 0xe0830200, /* add r0, r3, r0, lsl #4 */ 63 0xe59f2024, /* ldr r2, privbase */ 64 0xe3a01001, /* mov r1, #1 */ 65 0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */ 66 0xe3a010ff, /* mov r1, #0xff */ 67 0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */ 68 0xf57ff04f, /* dsb */ 69 0xe320f003, /* wfi */ 70 0xe5901000, /* ldr r1, [r0] */ 71 0xe1110001, /* tst r1, r1 */ 72 0x0afffffb, /* beq <wfi> */ 73 0xe12fff11, /* bx r1 */ 74 MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */ 75 }; 76 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 77 smpboot[n] = tswap32(smpboot[n]); 78 } 79 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR); 80 } 81 82 static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 83 { 84 CPUARMState *env = &cpu->env; 85 86 switch (info->nb_cpus) { 87 case 4: 88 address_space_stl_notdirty(&address_space_memory, 89 SMP_BOOT_REG + 0x30, 0, 90 MEMTXATTRS_UNSPECIFIED, NULL); 91 case 3: 92 address_space_stl_notdirty(&address_space_memory, 93 SMP_BOOT_REG + 0x20, 0, 94 MEMTXATTRS_UNSPECIFIED, NULL); 95 case 2: 96 address_space_stl_notdirty(&address_space_memory, 97 SMP_BOOT_REG + 0x10, 0, 98 MEMTXATTRS_UNSPECIFIED, NULL); 99 env->regs[15] = SMP_BOOT_ADDR; 100 break; 101 default: 102 break; 103 } 104 } 105 106 #define NUM_REGS 0x200 107 static void hb_regs_write(void *opaque, hwaddr offset, 108 uint64_t value, unsigned size) 109 { 110 uint32_t *regs = opaque; 111 112 if (offset == 0xf00) { 113 if (value == 1 || value == 2) { 114 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 115 } else if (value == 3) { 116 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 117 } 118 } 119 120 if (offset / 4 >= NUM_REGS) { 121 qemu_log_mask(LOG_GUEST_ERROR, 122 "highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset); 123 return; 124 } 125 regs[offset / 4] = value; 126 } 127 128 static uint64_t hb_regs_read(void *opaque, hwaddr offset, 129 unsigned size) 130 { 131 uint32_t value; 132 uint32_t *regs = opaque; 133 134 if (offset / 4 >= NUM_REGS) { 135 qemu_log_mask(LOG_GUEST_ERROR, 136 "highbank: bad read offset 0x%" HWADDR_PRIx "\n", offset); 137 return 0; 138 } 139 value = regs[offset / 4]; 140 141 if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) { 142 value |= 0x30000000; 143 } 144 145 return value; 146 } 147 148 static const MemoryRegionOps hb_mem_ops = { 149 .read = hb_regs_read, 150 .write = hb_regs_write, 151 .endianness = DEVICE_NATIVE_ENDIAN, 152 }; 153 154 #define TYPE_HIGHBANK_REGISTERS "highbank-regs" 155 #define HIGHBANK_REGISTERS(obj) \ 156 OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS) 157 158 typedef struct { 159 /*< private >*/ 160 SysBusDevice parent_obj; 161 /*< public >*/ 162 163 MemoryRegion iomem; 164 uint32_t regs[NUM_REGS]; 165 } HighbankRegsState; 166 167 static VMStateDescription vmstate_highbank_regs = { 168 .name = "highbank-regs", 169 .version_id = 0, 170 .minimum_version_id = 0, 171 .fields = (VMStateField[]) { 172 VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS), 173 VMSTATE_END_OF_LIST(), 174 }, 175 }; 176 177 static void highbank_regs_reset(DeviceState *dev) 178 { 179 HighbankRegsState *s = HIGHBANK_REGISTERS(dev); 180 181 s->regs[0x40] = 0x05F20121; 182 s->regs[0x41] = 0x2; 183 s->regs[0x42] = 0x05F30121; 184 s->regs[0x43] = 0x05F40121; 185 } 186 187 static void highbank_regs_init(Object *obj) 188 { 189 HighbankRegsState *s = HIGHBANK_REGISTERS(obj); 190 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 191 192 memory_region_init_io(&s->iomem, obj, &hb_mem_ops, s->regs, 193 "highbank_regs", 0x1000); 194 sysbus_init_mmio(dev, &s->iomem); 195 } 196 197 static void highbank_regs_class_init(ObjectClass *klass, void *data) 198 { 199 DeviceClass *dc = DEVICE_CLASS(klass); 200 201 dc->desc = "Calxeda Highbank registers"; 202 dc->vmsd = &vmstate_highbank_regs; 203 dc->reset = highbank_regs_reset; 204 } 205 206 static const TypeInfo highbank_regs_info = { 207 .name = TYPE_HIGHBANK_REGISTERS, 208 .parent = TYPE_SYS_BUS_DEVICE, 209 .instance_size = sizeof(HighbankRegsState), 210 .instance_init = highbank_regs_init, 211 .class_init = highbank_regs_class_init, 212 }; 213 214 static void highbank_regs_register_types(void) 215 { 216 type_register_static(&highbank_regs_info); 217 } 218 219 type_init(highbank_regs_register_types) 220 221 static struct arm_boot_info highbank_binfo; 222 223 enum cxmachines { 224 CALXEDA_HIGHBANK, 225 CALXEDA_MIDWAY, 226 }; 227 228 /* ram_size must be set to match the upper bound of memory in the 229 * device tree (linux/arch/arm/boot/dts/highbank.dts), which is 230 * normally 0xff900000 or -m 4089. When running this board on a 231 * 32-bit host, set the reg value of memory to 0xf7ff00000 in the 232 * device tree and pass -m 2047 to QEMU. 233 */ 234 static void calxeda_init(MachineState *machine, enum cxmachines machine_id) 235 { 236 ram_addr_t ram_size = machine->ram_size; 237 const char *kernel_filename = machine->kernel_filename; 238 const char *kernel_cmdline = machine->kernel_cmdline; 239 const char *initrd_filename = machine->initrd_filename; 240 DeviceState *dev = NULL; 241 SysBusDevice *busdev; 242 qemu_irq pic[128]; 243 int n; 244 qemu_irq cpu_irq[4]; 245 qemu_irq cpu_fiq[4]; 246 MemoryRegion *sysram; 247 MemoryRegion *dram; 248 MemoryRegion *sysmem; 249 char *sysboot_filename; 250 251 switch (machine_id) { 252 case CALXEDA_HIGHBANK: 253 machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 254 break; 255 case CALXEDA_MIDWAY: 256 machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 257 break; 258 default: 259 assert(0); 260 } 261 262 for (n = 0; n < smp_cpus; n++) { 263 Object *cpuobj; 264 ARMCPU *cpu; 265 266 cpuobj = object_new(machine->cpu_type); 267 cpu = ARM_CPU(cpuobj); 268 269 object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC, 270 "psci-conduit", &error_abort); 271 272 if (n) { 273 /* Secondary CPUs start in PSCI powered-down state */ 274 object_property_set_bool(cpuobj, true, 275 "start-powered-off", &error_abort); 276 } 277 278 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 279 object_property_set_int(cpuobj, MPCORE_PERIPHBASE, 280 "reset-cbar", &error_abort); 281 } 282 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 283 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ); 284 cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ); 285 } 286 287 sysmem = get_system_memory(); 288 dram = g_new(MemoryRegion, 1); 289 memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size); 290 /* SDRAM at address zero. */ 291 memory_region_add_subregion(sysmem, 0, dram); 292 293 sysram = g_new(MemoryRegion, 1); 294 memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000, 295 &error_fatal); 296 memory_region_add_subregion(sysmem, 0xfff88000, sysram); 297 if (bios_name != NULL) { 298 sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 299 if (sysboot_filename != NULL) { 300 if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) { 301 error_report("Unable to load %s", bios_name); 302 exit(1); 303 } 304 g_free(sysboot_filename); 305 } else { 306 error_report("Unable to find %s", bios_name); 307 exit(1); 308 } 309 } 310 311 switch (machine_id) { 312 case CALXEDA_HIGHBANK: 313 dev = qdev_create(NULL, "l2x0"); 314 qdev_init_nofail(dev); 315 busdev = SYS_BUS_DEVICE(dev); 316 sysbus_mmio_map(busdev, 0, 0xfff12000); 317 318 dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV); 319 break; 320 case CALXEDA_MIDWAY: 321 dev = qdev_create(NULL, TYPE_A15MPCORE_PRIV); 322 break; 323 } 324 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 325 qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC); 326 qdev_init_nofail(dev); 327 busdev = SYS_BUS_DEVICE(dev); 328 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); 329 for (n = 0; n < smp_cpus; n++) { 330 sysbus_connect_irq(busdev, n, cpu_irq[n]); 331 sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]); 332 } 333 334 for (n = 0; n < 128; n++) { 335 pic[n] = qdev_get_gpio_in(dev, n); 336 } 337 338 dev = qdev_create(NULL, "sp804"); 339 qdev_prop_set_uint32(dev, "freq0", 150000000); 340 qdev_prop_set_uint32(dev, "freq1", 150000000); 341 qdev_init_nofail(dev); 342 busdev = SYS_BUS_DEVICE(dev); 343 sysbus_mmio_map(busdev, 0, 0xfff34000); 344 sysbus_connect_irq(busdev, 0, pic[18]); 345 pl011_create(0xfff36000, pic[20], serial_hd(0)); 346 347 dev = qdev_create(NULL, TYPE_HIGHBANK_REGISTERS); 348 qdev_init_nofail(dev); 349 busdev = SYS_BUS_DEVICE(dev); 350 sysbus_mmio_map(busdev, 0, 0xfff3c000); 351 352 sysbus_create_simple("pl061", 0xfff30000, pic[14]); 353 sysbus_create_simple("pl061", 0xfff31000, pic[15]); 354 sysbus_create_simple("pl061", 0xfff32000, pic[16]); 355 sysbus_create_simple("pl061", 0xfff33000, pic[17]); 356 sysbus_create_simple("pl031", 0xfff35000, pic[19]); 357 sysbus_create_simple("pl022", 0xfff39000, pic[23]); 358 359 sysbus_create_simple(TYPE_SYSBUS_AHCI, 0xffe08000, pic[83]); 360 361 if (nd_table[0].used) { 362 qemu_check_nic_model(&nd_table[0], "xgmac"); 363 dev = qdev_create(NULL, "xgmac"); 364 qdev_set_nic_properties(dev, &nd_table[0]); 365 qdev_init_nofail(dev); 366 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000); 367 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]); 368 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]); 369 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]); 370 371 qemu_check_nic_model(&nd_table[1], "xgmac"); 372 dev = qdev_create(NULL, "xgmac"); 373 qdev_set_nic_properties(dev, &nd_table[1]); 374 qdev_init_nofail(dev); 375 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000); 376 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]); 377 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]); 378 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]); 379 } 380 381 /* TODO create and connect IDE devices for ide_drive_get() */ 382 383 highbank_binfo.ram_size = ram_size; 384 highbank_binfo.kernel_filename = kernel_filename; 385 highbank_binfo.kernel_cmdline = kernel_cmdline; 386 highbank_binfo.initrd_filename = initrd_filename; 387 /* highbank requires a dtb in order to boot, and the dtb will override 388 * the board ID. The following value is ignored, so set it to -1 to be 389 * clear that the value is meaningless. 390 */ 391 highbank_binfo.board_id = -1; 392 highbank_binfo.nb_cpus = smp_cpus; 393 highbank_binfo.loader_start = 0; 394 highbank_binfo.write_secondary_boot = hb_write_secondary; 395 highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary; 396 if (!kvm_enabled()) { 397 highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR; 398 highbank_binfo.write_board_setup = hb_write_board_setup; 399 highbank_binfo.secure_board_setup = true; 400 } else { 401 warn_report("cannot load built-in Monitor support " 402 "if KVM is enabled. Some guests (such as Linux) " 403 "may not boot."); 404 } 405 406 arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo); 407 } 408 409 static void highbank_init(MachineState *machine) 410 { 411 calxeda_init(machine, CALXEDA_HIGHBANK); 412 } 413 414 static void midway_init(MachineState *machine) 415 { 416 calxeda_init(machine, CALXEDA_MIDWAY); 417 } 418 419 static void highbank_class_init(ObjectClass *oc, void *data) 420 { 421 MachineClass *mc = MACHINE_CLASS(oc); 422 423 mc->desc = "Calxeda Highbank (ECX-1000)"; 424 mc->init = highbank_init; 425 mc->block_default_type = IF_IDE; 426 mc->units_per_default_bus = 1; 427 mc->max_cpus = 4; 428 mc->ignore_memory_transaction_failures = true; 429 } 430 431 static const TypeInfo highbank_type = { 432 .name = MACHINE_TYPE_NAME("highbank"), 433 .parent = TYPE_MACHINE, 434 .class_init = highbank_class_init, 435 }; 436 437 static void midway_class_init(ObjectClass *oc, void *data) 438 { 439 MachineClass *mc = MACHINE_CLASS(oc); 440 441 mc->desc = "Calxeda Midway (ECX-2000)"; 442 mc->init = midway_init; 443 mc->block_default_type = IF_IDE; 444 mc->units_per_default_bus = 1; 445 mc->max_cpus = 4; 446 mc->ignore_memory_transaction_failures = true; 447 } 448 449 static const TypeInfo midway_type = { 450 .name = MACHINE_TYPE_NAME("midway"), 451 .parent = TYPE_MACHINE, 452 .class_init = midway_class_init, 453 }; 454 455 static void calxeda_machines_init(void) 456 { 457 type_register_static(&highbank_type); 458 type_register_static(&midway_type); 459 } 460 461 type_init(calxeda_machines_init) 462