1 /* 2 * Calxeda Highbank SoC emulation 3 * 4 * Copyright (c) 2010-2012 Calxeda 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 */ 19 20 #include "hw/sysbus.h" 21 #include "hw/arm/arm.h" 22 #include "hw/devices.h" 23 #include "hw/loader.h" 24 #include "net/net.h" 25 #include "sysemu/sysemu.h" 26 #include "hw/boards.h" 27 #include "sysemu/block-backend.h" 28 #include "exec/address-spaces.h" 29 #include "qemu/error-report.h" 30 31 #define SMP_BOOT_ADDR 0x100 32 #define SMP_BOOT_REG 0x40 33 #define MPCORE_PERIPHBASE 0xfff10000 34 35 #define NIRQ_GIC 160 36 37 /* Board init. */ 38 39 static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 40 { 41 int n; 42 uint32_t smpboot[] = { 43 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */ 44 0xe210000f, /* ands r0, r0, #0x0f */ 45 0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */ 46 0xe0830200, /* add r0, r3, r0, lsl #4 */ 47 0xe59f2024, /* ldr r2, privbase */ 48 0xe3a01001, /* mov r1, #1 */ 49 0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */ 50 0xe3a010ff, /* mov r1, #0xff */ 51 0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */ 52 0xf57ff04f, /* dsb */ 53 0xe320f003, /* wfi */ 54 0xe5901000, /* ldr r1, [r0] */ 55 0xe1110001, /* tst r1, r1 */ 56 0x0afffffb, /* beq <wfi> */ 57 0xe12fff11, /* bx r1 */ 58 MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */ 59 }; 60 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 61 smpboot[n] = tswap32(smpboot[n]); 62 } 63 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR); 64 } 65 66 static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 67 { 68 CPUARMState *env = &cpu->env; 69 70 switch (info->nb_cpus) { 71 case 4: 72 stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x30, 0); 73 case 3: 74 stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x20, 0); 75 case 2: 76 stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x10, 0); 77 env->regs[15] = SMP_BOOT_ADDR; 78 break; 79 default: 80 break; 81 } 82 } 83 84 #define NUM_REGS 0x200 85 static void hb_regs_write(void *opaque, hwaddr offset, 86 uint64_t value, unsigned size) 87 { 88 uint32_t *regs = opaque; 89 90 if (offset == 0xf00) { 91 if (value == 1 || value == 2) { 92 qemu_system_reset_request(); 93 } else if (value == 3) { 94 qemu_system_shutdown_request(); 95 } 96 } 97 98 regs[offset/4] = value; 99 } 100 101 static uint64_t hb_regs_read(void *opaque, hwaddr offset, 102 unsigned size) 103 { 104 uint32_t *regs = opaque; 105 uint32_t value = regs[offset/4]; 106 107 if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) { 108 value |= 0x30000000; 109 } 110 111 return value; 112 } 113 114 static const MemoryRegionOps hb_mem_ops = { 115 .read = hb_regs_read, 116 .write = hb_regs_write, 117 .endianness = DEVICE_NATIVE_ENDIAN, 118 }; 119 120 #define TYPE_HIGHBANK_REGISTERS "highbank-regs" 121 #define HIGHBANK_REGISTERS(obj) \ 122 OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS) 123 124 typedef struct { 125 /*< private >*/ 126 SysBusDevice parent_obj; 127 /*< public >*/ 128 129 MemoryRegion iomem; 130 uint32_t regs[NUM_REGS]; 131 } HighbankRegsState; 132 133 static VMStateDescription vmstate_highbank_regs = { 134 .name = "highbank-regs", 135 .version_id = 0, 136 .minimum_version_id = 0, 137 .fields = (VMStateField[]) { 138 VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS), 139 VMSTATE_END_OF_LIST(), 140 }, 141 }; 142 143 static void highbank_regs_reset(DeviceState *dev) 144 { 145 HighbankRegsState *s = HIGHBANK_REGISTERS(dev); 146 147 s->regs[0x40] = 0x05F20121; 148 s->regs[0x41] = 0x2; 149 s->regs[0x42] = 0x05F30121; 150 s->regs[0x43] = 0x05F40121; 151 } 152 153 static int highbank_regs_init(SysBusDevice *dev) 154 { 155 HighbankRegsState *s = HIGHBANK_REGISTERS(dev); 156 157 memory_region_init_io(&s->iomem, OBJECT(s), &hb_mem_ops, s->regs, 158 "highbank_regs", 0x1000); 159 sysbus_init_mmio(dev, &s->iomem); 160 161 return 0; 162 } 163 164 static void highbank_regs_class_init(ObjectClass *klass, void *data) 165 { 166 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); 167 DeviceClass *dc = DEVICE_CLASS(klass); 168 169 sbc->init = highbank_regs_init; 170 dc->desc = "Calxeda Highbank registers"; 171 dc->vmsd = &vmstate_highbank_regs; 172 dc->reset = highbank_regs_reset; 173 } 174 175 static const TypeInfo highbank_regs_info = { 176 .name = TYPE_HIGHBANK_REGISTERS, 177 .parent = TYPE_SYS_BUS_DEVICE, 178 .instance_size = sizeof(HighbankRegsState), 179 .class_init = highbank_regs_class_init, 180 }; 181 182 static void highbank_regs_register_types(void) 183 { 184 type_register_static(&highbank_regs_info); 185 } 186 187 type_init(highbank_regs_register_types) 188 189 static struct arm_boot_info highbank_binfo; 190 191 enum cxmachines { 192 CALXEDA_HIGHBANK, 193 CALXEDA_MIDWAY, 194 }; 195 196 /* ram_size must be set to match the upper bound of memory in the 197 * device tree (linux/arch/arm/boot/dts/highbank.dts), which is 198 * normally 0xff900000 or -m 4089. When running this board on a 199 * 32-bit host, set the reg value of memory to 0xf7ff00000 in the 200 * device tree and pass -m 2047 to QEMU. 201 */ 202 static void calxeda_init(MachineState *machine, enum cxmachines machine_id) 203 { 204 ram_addr_t ram_size = machine->ram_size; 205 const char *cpu_model = machine->cpu_model; 206 const char *kernel_filename = machine->kernel_filename; 207 const char *kernel_cmdline = machine->kernel_cmdline; 208 const char *initrd_filename = machine->initrd_filename; 209 DeviceState *dev = NULL; 210 SysBusDevice *busdev; 211 qemu_irq pic[128]; 212 int n; 213 qemu_irq cpu_irq[4]; 214 MemoryRegion *sysram; 215 MemoryRegion *dram; 216 MemoryRegion *sysmem; 217 char *sysboot_filename; 218 219 if (!cpu_model) { 220 switch (machine_id) { 221 case CALXEDA_HIGHBANK: 222 cpu_model = "cortex-a9"; 223 break; 224 case CALXEDA_MIDWAY: 225 cpu_model = "cortex-a15"; 226 break; 227 } 228 } 229 230 for (n = 0; n < smp_cpus; n++) { 231 ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 232 Object *cpuobj; 233 ARMCPU *cpu; 234 Error *err = NULL; 235 236 if (!oc) { 237 error_report("Unable to find CPU definition"); 238 exit(1); 239 } 240 241 cpuobj = object_new(object_class_get_name(oc)); 242 cpu = ARM_CPU(cpuobj); 243 244 /* By default A9 and A15 CPUs have EL3 enabled. This board does not 245 * currently support EL3 so the CPU EL3 property is disabled before 246 * realization. 247 */ 248 if (object_property_find(cpuobj, "has_el3", NULL)) { 249 object_property_set_bool(cpuobj, false, "has_el3", &err); 250 if (err) { 251 error_report_err(err); 252 exit(1); 253 } 254 } 255 256 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 257 object_property_set_int(cpuobj, MPCORE_PERIPHBASE, 258 "reset-cbar", &error_abort); 259 } 260 object_property_set_bool(cpuobj, true, "realized", &err); 261 if (err) { 262 error_report_err(err); 263 exit(1); 264 } 265 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ); 266 } 267 268 sysmem = get_system_memory(); 269 dram = g_new(MemoryRegion, 1); 270 memory_region_init_ram(dram, NULL, "highbank.dram", ram_size, &error_abort); 271 /* SDRAM at address zero. */ 272 memory_region_add_subregion(sysmem, 0, dram); 273 274 sysram = g_new(MemoryRegion, 1); 275 memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000, 276 &error_abort); 277 memory_region_add_subregion(sysmem, 0xfff88000, sysram); 278 if (bios_name != NULL) { 279 sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 280 if (sysboot_filename != NULL) { 281 uint32_t filesize = get_image_size(sysboot_filename); 282 if (load_image_targphys("sysram.bin", 0xfff88000, filesize) < 0) { 283 hw_error("Unable to load %s\n", bios_name); 284 } 285 } else { 286 hw_error("Unable to find %s\n", bios_name); 287 } 288 } 289 290 switch (machine_id) { 291 case CALXEDA_HIGHBANK: 292 dev = qdev_create(NULL, "l2x0"); 293 qdev_init_nofail(dev); 294 busdev = SYS_BUS_DEVICE(dev); 295 sysbus_mmio_map(busdev, 0, 0xfff12000); 296 297 dev = qdev_create(NULL, "a9mpcore_priv"); 298 break; 299 case CALXEDA_MIDWAY: 300 dev = qdev_create(NULL, "a15mpcore_priv"); 301 break; 302 } 303 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 304 qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC); 305 qdev_init_nofail(dev); 306 busdev = SYS_BUS_DEVICE(dev); 307 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); 308 for (n = 0; n < smp_cpus; n++) { 309 sysbus_connect_irq(busdev, n, cpu_irq[n]); 310 } 311 312 for (n = 0; n < 128; n++) { 313 pic[n] = qdev_get_gpio_in(dev, n); 314 } 315 316 dev = qdev_create(NULL, "sp804"); 317 qdev_prop_set_uint32(dev, "freq0", 150000000); 318 qdev_prop_set_uint32(dev, "freq1", 150000000); 319 qdev_init_nofail(dev); 320 busdev = SYS_BUS_DEVICE(dev); 321 sysbus_mmio_map(busdev, 0, 0xfff34000); 322 sysbus_connect_irq(busdev, 0, pic[18]); 323 sysbus_create_simple("pl011", 0xfff36000, pic[20]); 324 325 dev = qdev_create(NULL, "highbank-regs"); 326 qdev_init_nofail(dev); 327 busdev = SYS_BUS_DEVICE(dev); 328 sysbus_mmio_map(busdev, 0, 0xfff3c000); 329 330 sysbus_create_simple("pl061", 0xfff30000, pic[14]); 331 sysbus_create_simple("pl061", 0xfff31000, pic[15]); 332 sysbus_create_simple("pl061", 0xfff32000, pic[16]); 333 sysbus_create_simple("pl061", 0xfff33000, pic[17]); 334 sysbus_create_simple("pl031", 0xfff35000, pic[19]); 335 sysbus_create_simple("pl022", 0xfff39000, pic[23]); 336 337 sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]); 338 339 if (nd_table[0].used) { 340 qemu_check_nic_model(&nd_table[0], "xgmac"); 341 dev = qdev_create(NULL, "xgmac"); 342 qdev_set_nic_properties(dev, &nd_table[0]); 343 qdev_init_nofail(dev); 344 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000); 345 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]); 346 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]); 347 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]); 348 349 qemu_check_nic_model(&nd_table[1], "xgmac"); 350 dev = qdev_create(NULL, "xgmac"); 351 qdev_set_nic_properties(dev, &nd_table[1]); 352 qdev_init_nofail(dev); 353 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000); 354 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]); 355 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]); 356 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]); 357 } 358 359 highbank_binfo.ram_size = ram_size; 360 highbank_binfo.kernel_filename = kernel_filename; 361 highbank_binfo.kernel_cmdline = kernel_cmdline; 362 highbank_binfo.initrd_filename = initrd_filename; 363 /* highbank requires a dtb in order to boot, and the dtb will override 364 * the board ID. The following value is ignored, so set it to -1 to be 365 * clear that the value is meaningless. 366 */ 367 highbank_binfo.board_id = -1; 368 highbank_binfo.nb_cpus = smp_cpus; 369 highbank_binfo.loader_start = 0; 370 highbank_binfo.write_secondary_boot = hb_write_secondary; 371 highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary; 372 arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo); 373 } 374 375 static void highbank_init(MachineState *machine) 376 { 377 calxeda_init(machine, CALXEDA_HIGHBANK); 378 } 379 380 static void midway_init(MachineState *machine) 381 { 382 calxeda_init(machine, CALXEDA_MIDWAY); 383 } 384 385 static QEMUMachine highbank_machine = { 386 .name = "highbank", 387 .desc = "Calxeda Highbank (ECX-1000)", 388 .init = highbank_init, 389 .block_default_type = IF_SCSI, 390 .max_cpus = 4, 391 }; 392 393 static QEMUMachine midway_machine = { 394 .name = "midway", 395 .desc = "Calxeda Midway (ECX-2000)", 396 .init = midway_init, 397 .block_default_type = IF_SCSI, 398 .max_cpus = 4, 399 }; 400 401 static void calxeda_machines_init(void) 402 { 403 qemu_register_machine(&highbank_machine); 404 qemu_register_machine(&midway_machine); 405 } 406 407 machine_init(calxeda_machines_init); 408