1 /* 2 * Calxeda Highbank SoC emulation 3 * 4 * Copyright (c) 2010-2012 Calxeda 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qapi/error.h" 23 #include "hw/sysbus.h" 24 #include "migration/vmstate.h" 25 #include "hw/arm/boot.h" 26 #include "hw/loader.h" 27 #include "net/net.h" 28 #include "sysemu/runstate.h" 29 #include "sysemu/sysemu.h" 30 #include "hw/boards.h" 31 #include "qemu/error-report.h" 32 #include "hw/char/pl011.h" 33 #include "hw/ide/ahci-sysbus.h" 34 #include "hw/cpu/a9mpcore.h" 35 #include "hw/cpu/a15mpcore.h" 36 #include "qemu/log.h" 37 #include "qom/object.h" 38 #include "cpu.h" 39 #include "target/arm/cpu-qom.h" 40 41 #define SMP_BOOT_ADDR 0x100 42 #define SMP_BOOT_REG 0x40 43 #define MPCORE_PERIPHBASE 0xfff10000 44 45 #define MVBAR_ADDR 0x200 46 #define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t)) 47 48 #define NIRQ_GIC 160 49 50 /* Board init. */ 51 52 #define NUM_REGS 0x200 53 static void hb_regs_write(void *opaque, hwaddr offset, 54 uint64_t value, unsigned size) 55 { 56 uint32_t *regs = opaque; 57 58 if (offset == 0xf00) { 59 if (value == 1 || value == 2) { 60 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 61 } else if (value == 3) { 62 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 63 } 64 } 65 66 if (offset / 4 >= NUM_REGS) { 67 qemu_log_mask(LOG_GUEST_ERROR, 68 "highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset); 69 return; 70 } 71 regs[offset / 4] = value; 72 } 73 74 static uint64_t hb_regs_read(void *opaque, hwaddr offset, 75 unsigned size) 76 { 77 uint32_t value; 78 uint32_t *regs = opaque; 79 80 if (offset / 4 >= NUM_REGS) { 81 qemu_log_mask(LOG_GUEST_ERROR, 82 "highbank: bad read offset 0x%" HWADDR_PRIx "\n", offset); 83 return 0; 84 } 85 value = regs[offset / 4]; 86 87 if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) { 88 value |= 0x30000000; 89 } 90 91 return value; 92 } 93 94 static const MemoryRegionOps hb_mem_ops = { 95 .read = hb_regs_read, 96 .write = hb_regs_write, 97 .endianness = DEVICE_NATIVE_ENDIAN, 98 }; 99 100 #define TYPE_HIGHBANK_REGISTERS "highbank-regs" 101 OBJECT_DECLARE_SIMPLE_TYPE(HighbankRegsState, HIGHBANK_REGISTERS) 102 103 struct HighbankRegsState { 104 /*< private >*/ 105 SysBusDevice parent_obj; 106 /*< public >*/ 107 108 MemoryRegion iomem; 109 uint32_t regs[NUM_REGS]; 110 }; 111 112 static const VMStateDescription vmstate_highbank_regs = { 113 .name = "highbank-regs", 114 .version_id = 0, 115 .minimum_version_id = 0, 116 .fields = (const VMStateField[]) { 117 VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS), 118 VMSTATE_END_OF_LIST(), 119 }, 120 }; 121 122 static void highbank_regs_reset(DeviceState *dev) 123 { 124 HighbankRegsState *s = HIGHBANK_REGISTERS(dev); 125 126 s->regs[0x40] = 0x05F20121; 127 s->regs[0x41] = 0x2; 128 s->regs[0x42] = 0x05F30121; 129 s->regs[0x43] = 0x05F40121; 130 } 131 132 static void highbank_regs_init(Object *obj) 133 { 134 HighbankRegsState *s = HIGHBANK_REGISTERS(obj); 135 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 136 137 memory_region_init_io(&s->iomem, obj, &hb_mem_ops, s->regs, 138 "highbank_regs", 0x1000); 139 sysbus_init_mmio(dev, &s->iomem); 140 } 141 142 static void highbank_regs_class_init(ObjectClass *klass, void *data) 143 { 144 DeviceClass *dc = DEVICE_CLASS(klass); 145 146 dc->desc = "Calxeda Highbank registers"; 147 dc->vmsd = &vmstate_highbank_regs; 148 dc->reset = highbank_regs_reset; 149 } 150 151 static const TypeInfo highbank_regs_info = { 152 .name = TYPE_HIGHBANK_REGISTERS, 153 .parent = TYPE_SYS_BUS_DEVICE, 154 .instance_size = sizeof(HighbankRegsState), 155 .instance_init = highbank_regs_init, 156 .class_init = highbank_regs_class_init, 157 }; 158 159 static void highbank_regs_register_types(void) 160 { 161 type_register_static(&highbank_regs_info); 162 } 163 164 type_init(highbank_regs_register_types) 165 166 static struct arm_boot_info highbank_binfo; 167 168 enum cxmachines { 169 CALXEDA_HIGHBANK, 170 CALXEDA_MIDWAY, 171 }; 172 173 /* ram_size must be set to match the upper bound of memory in the 174 * device tree (linux/arch/arm/boot/dts/highbank.dts), which is 175 * normally 0xff900000 or -m 4089. When running this board on a 176 * 32-bit host, set the reg value of memory to 0xf7ff00000 in the 177 * device tree and pass -m 2047 to QEMU. 178 */ 179 static void calxeda_init(MachineState *machine, enum cxmachines machine_id) 180 { 181 DeviceState *dev = NULL; 182 SysBusDevice *busdev; 183 qemu_irq pic[128]; 184 int n; 185 unsigned int smp_cpus = machine->smp.cpus; 186 qemu_irq cpu_irq[4]; 187 qemu_irq cpu_fiq[4]; 188 qemu_irq cpu_virq[4]; 189 qemu_irq cpu_vfiq[4]; 190 MemoryRegion *sysram; 191 MemoryRegion *sysmem; 192 char *sysboot_filename; 193 194 switch (machine_id) { 195 case CALXEDA_HIGHBANK: 196 machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 197 break; 198 case CALXEDA_MIDWAY: 199 machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 200 break; 201 default: 202 assert(0); 203 } 204 205 for (n = 0; n < smp_cpus; n++) { 206 Object *cpuobj; 207 ARMCPU *cpu; 208 209 cpuobj = object_new(machine->cpu_type); 210 cpu = ARM_CPU(cpuobj); 211 212 object_property_add_child(OBJECT(machine), "cpu[*]", cpuobj); 213 object_property_set_int(cpuobj, "psci-conduit", QEMU_PSCI_CONDUIT_SMC, 214 &error_abort); 215 216 if (object_property_find(cpuobj, "reset-cbar")) { 217 object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE, 218 &error_abort); 219 } 220 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 221 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ); 222 cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ); 223 cpu_virq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VIRQ); 224 cpu_vfiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VFIQ); 225 } 226 227 sysmem = get_system_memory(); 228 /* SDRAM at address zero. */ 229 memory_region_add_subregion(sysmem, 0, machine->ram); 230 231 sysram = g_new(MemoryRegion, 1); 232 memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000, 233 &error_fatal); 234 memory_region_add_subregion(sysmem, 0xfff88000, sysram); 235 if (machine->firmware != NULL) { 236 sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware); 237 if (sysboot_filename != NULL) { 238 if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) { 239 error_report("Unable to load %s", machine->firmware); 240 exit(1); 241 } 242 g_free(sysboot_filename); 243 } else { 244 error_report("Unable to find %s", machine->firmware); 245 exit(1); 246 } 247 } 248 249 switch (machine_id) { 250 case CALXEDA_HIGHBANK: 251 dev = qdev_new("l2x0"); 252 busdev = SYS_BUS_DEVICE(dev); 253 sysbus_realize_and_unref(busdev, &error_fatal); 254 sysbus_mmio_map(busdev, 0, 0xfff12000); 255 256 dev = qdev_new(TYPE_A9MPCORE_PRIV); 257 break; 258 case CALXEDA_MIDWAY: 259 dev = qdev_new(TYPE_A15MPCORE_PRIV); 260 break; 261 } 262 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 263 qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC); 264 busdev = SYS_BUS_DEVICE(dev); 265 sysbus_realize_and_unref(busdev, &error_fatal); 266 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); 267 for (n = 0; n < smp_cpus; n++) { 268 sysbus_connect_irq(busdev, n, cpu_irq[n]); 269 sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]); 270 sysbus_connect_irq(busdev, n + 2 * smp_cpus, cpu_virq[n]); 271 sysbus_connect_irq(busdev, n + 3 * smp_cpus, cpu_vfiq[n]); 272 } 273 274 for (n = 0; n < 128; n++) { 275 pic[n] = qdev_get_gpio_in(dev, n); 276 } 277 278 dev = qdev_new("sp804"); 279 qdev_prop_set_uint32(dev, "freq0", 150000000); 280 qdev_prop_set_uint32(dev, "freq1", 150000000); 281 busdev = SYS_BUS_DEVICE(dev); 282 sysbus_realize_and_unref(busdev, &error_fatal); 283 sysbus_mmio_map(busdev, 0, 0xfff34000); 284 sysbus_connect_irq(busdev, 0, pic[18]); 285 pl011_create(0xfff36000, pic[20], serial_hd(0)); 286 287 dev = qdev_new(TYPE_HIGHBANK_REGISTERS); 288 busdev = SYS_BUS_DEVICE(dev); 289 sysbus_realize_and_unref(busdev, &error_fatal); 290 sysbus_mmio_map(busdev, 0, 0xfff3c000); 291 292 sysbus_create_simple("pl061", 0xfff30000, pic[14]); 293 sysbus_create_simple("pl061", 0xfff31000, pic[15]); 294 sysbus_create_simple("pl061", 0xfff32000, pic[16]); 295 sysbus_create_simple("pl061", 0xfff33000, pic[17]); 296 sysbus_create_simple("pl031", 0xfff35000, pic[19]); 297 sysbus_create_simple("pl022", 0xfff39000, pic[23]); 298 299 sysbus_create_simple(TYPE_SYSBUS_AHCI, 0xffe08000, pic[83]); 300 301 dev = qemu_create_nic_device("xgmac", true, NULL); 302 if (dev) { 303 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 304 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000); 305 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]); 306 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]); 307 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]); 308 } 309 310 dev = qemu_create_nic_device("xgmac", true, NULL); 311 if (dev) { 312 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 313 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000); 314 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]); 315 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]); 316 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]); 317 } 318 319 /* TODO create and connect IDE devices for ide_drive_get() */ 320 321 highbank_binfo.ram_size = machine->ram_size; 322 /* highbank requires a dtb in order to boot, and the dtb will override 323 * the board ID. The following value is ignored, so set it to -1 to be 324 * clear that the value is meaningless. 325 */ 326 highbank_binfo.board_id = -1; 327 highbank_binfo.loader_start = 0; 328 highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR; 329 highbank_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC; 330 331 arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo); 332 } 333 334 static void highbank_init(MachineState *machine) 335 { 336 calxeda_init(machine, CALXEDA_HIGHBANK); 337 } 338 339 static void midway_init(MachineState *machine) 340 { 341 calxeda_init(machine, CALXEDA_MIDWAY); 342 } 343 344 static void highbank_class_init(ObjectClass *oc, void *data) 345 { 346 static const char * const valid_cpu_types[] = { 347 ARM_CPU_TYPE_NAME("cortex-a9"), 348 NULL 349 }; 350 MachineClass *mc = MACHINE_CLASS(oc); 351 352 mc->desc = "Calxeda Highbank (ECX-1000)"; 353 mc->init = highbank_init; 354 mc->valid_cpu_types = valid_cpu_types; 355 mc->block_default_type = IF_IDE; 356 mc->units_per_default_bus = 1; 357 mc->max_cpus = 4; 358 mc->ignore_memory_transaction_failures = true; 359 mc->default_ram_id = "highbank.dram"; 360 } 361 362 static const TypeInfo highbank_type = { 363 .name = MACHINE_TYPE_NAME("highbank"), 364 .parent = TYPE_MACHINE, 365 .class_init = highbank_class_init, 366 }; 367 368 static void midway_class_init(ObjectClass *oc, void *data) 369 { 370 static const char * const valid_cpu_types[] = { 371 ARM_CPU_TYPE_NAME("cortex-a15"), 372 NULL 373 }; 374 MachineClass *mc = MACHINE_CLASS(oc); 375 376 mc->desc = "Calxeda Midway (ECX-2000)"; 377 mc->init = midway_init; 378 mc->valid_cpu_types = valid_cpu_types; 379 mc->block_default_type = IF_IDE; 380 mc->units_per_default_bus = 1; 381 mc->max_cpus = 4; 382 mc->ignore_memory_transaction_failures = true; 383 mc->default_ram_id = "highbank.dram"; 384 } 385 386 static const TypeInfo midway_type = { 387 .name = MACHINE_TYPE_NAME("midway"), 388 .parent = TYPE_MACHINE, 389 .class_init = midway_class_init, 390 }; 391 392 static void calxeda_machines_init(void) 393 { 394 type_register_static(&highbank_type); 395 type_register_static(&midway_type); 396 } 397 398 type_init(calxeda_machines_init) 399