1 /* 2 * Calxeda Highbank SoC emulation 3 * 4 * Copyright (c) 2010-2012 Calxeda 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 */ 19 20 #include "hw/sysbus.h" 21 #include "hw/arm/arm.h" 22 #include "hw/devices.h" 23 #include "hw/loader.h" 24 #include "net/net.h" 25 #include "sysemu/sysemu.h" 26 #include "hw/boards.h" 27 #include "sysemu/blockdev.h" 28 #include "exec/address-spaces.h" 29 #include "qemu/error-report.h" 30 31 #define SMP_BOOT_ADDR 0x100 32 #define SMP_BOOT_REG 0x40 33 #define MPCORE_PERIPHBASE 0xfff10000 34 35 #define NIRQ_GIC 160 36 37 /* Board init. */ 38 39 static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 40 { 41 int n; 42 uint32_t smpboot[] = { 43 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */ 44 0xe210000f, /* ands r0, r0, #0x0f */ 45 0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */ 46 0xe0830200, /* add r0, r3, r0, lsl #4 */ 47 0xe59f2024, /* ldr r2, privbase */ 48 0xe3a01001, /* mov r1, #1 */ 49 0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */ 50 0xe3a010ff, /* mov r1, #0xff */ 51 0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */ 52 0xf57ff04f, /* dsb */ 53 0xe320f003, /* wfi */ 54 0xe5901000, /* ldr r1, [r0] */ 55 0xe1110001, /* tst r1, r1 */ 56 0x0afffffb, /* beq <wfi> */ 57 0xe12fff11, /* bx r1 */ 58 MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */ 59 }; 60 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 61 smpboot[n] = tswap32(smpboot[n]); 62 } 63 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR); 64 } 65 66 static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 67 { 68 CPUARMState *env = &cpu->env; 69 70 switch (info->nb_cpus) { 71 case 4: 72 stl_phys_notdirty(SMP_BOOT_REG + 0x30, 0); 73 case 3: 74 stl_phys_notdirty(SMP_BOOT_REG + 0x20, 0); 75 case 2: 76 stl_phys_notdirty(SMP_BOOT_REG + 0x10, 0); 77 env->regs[15] = SMP_BOOT_ADDR; 78 break; 79 default: 80 break; 81 } 82 } 83 84 #define NUM_REGS 0x200 85 static void hb_regs_write(void *opaque, hwaddr offset, 86 uint64_t value, unsigned size) 87 { 88 uint32_t *regs = opaque; 89 90 if (offset == 0xf00) { 91 if (value == 1 || value == 2) { 92 qemu_system_reset_request(); 93 } else if (value == 3) { 94 qemu_system_shutdown_request(); 95 } 96 } 97 98 regs[offset/4] = value; 99 } 100 101 static uint64_t hb_regs_read(void *opaque, hwaddr offset, 102 unsigned size) 103 { 104 uint32_t *regs = opaque; 105 uint32_t value = regs[offset/4]; 106 107 if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) { 108 value |= 0x30000000; 109 } 110 111 return value; 112 } 113 114 static const MemoryRegionOps hb_mem_ops = { 115 .read = hb_regs_read, 116 .write = hb_regs_write, 117 .endianness = DEVICE_NATIVE_ENDIAN, 118 }; 119 120 #define TYPE_HIGHBANK_REGISTERS "highbank-regs" 121 #define HIGHBANK_REGISTERS(obj) \ 122 OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS) 123 124 typedef struct { 125 /*< private >*/ 126 SysBusDevice parent_obj; 127 /*< public >*/ 128 129 MemoryRegion *iomem; 130 uint32_t regs[NUM_REGS]; 131 } HighbankRegsState; 132 133 static VMStateDescription vmstate_highbank_regs = { 134 .name = "highbank-regs", 135 .version_id = 0, 136 .minimum_version_id = 0, 137 .minimum_version_id_old = 0, 138 .fields = (VMStateField[]) { 139 VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS), 140 VMSTATE_END_OF_LIST(), 141 }, 142 }; 143 144 static void highbank_regs_reset(DeviceState *dev) 145 { 146 HighbankRegsState *s = HIGHBANK_REGISTERS(dev); 147 148 s->regs[0x40] = 0x05F20121; 149 s->regs[0x41] = 0x2; 150 s->regs[0x42] = 0x05F30121; 151 s->regs[0x43] = 0x05F40121; 152 } 153 154 static int highbank_regs_init(SysBusDevice *dev) 155 { 156 HighbankRegsState *s = HIGHBANK_REGISTERS(dev); 157 158 s->iomem = g_new(MemoryRegion, 1); 159 memory_region_init_io(s->iomem, OBJECT(s), &hb_mem_ops, s->regs, 160 "highbank_regs", 0x1000); 161 sysbus_init_mmio(dev, s->iomem); 162 163 return 0; 164 } 165 166 static void highbank_regs_class_init(ObjectClass *klass, void *data) 167 { 168 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); 169 DeviceClass *dc = DEVICE_CLASS(klass); 170 171 sbc->init = highbank_regs_init; 172 dc->desc = "Calxeda Highbank registers"; 173 dc->vmsd = &vmstate_highbank_regs; 174 dc->reset = highbank_regs_reset; 175 } 176 177 static const TypeInfo highbank_regs_info = { 178 .name = TYPE_HIGHBANK_REGISTERS, 179 .parent = TYPE_SYS_BUS_DEVICE, 180 .instance_size = sizeof(HighbankRegsState), 181 .class_init = highbank_regs_class_init, 182 }; 183 184 static void highbank_regs_register_types(void) 185 { 186 type_register_static(&highbank_regs_info); 187 } 188 189 type_init(highbank_regs_register_types) 190 191 static struct arm_boot_info highbank_binfo; 192 193 enum cxmachines { 194 CALXEDA_HIGHBANK, 195 CALXEDA_MIDWAY, 196 }; 197 198 /* ram_size must be set to match the upper bound of memory in the 199 * device tree (linux/arch/arm/boot/dts/highbank.dts), which is 200 * normally 0xff900000 or -m 4089. When running this board on a 201 * 32-bit host, set the reg value of memory to 0xf7ff00000 in the 202 * device tree and pass -m 2047 to QEMU. 203 */ 204 static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine) 205 { 206 ram_addr_t ram_size = args->ram_size; 207 const char *cpu_model = args->cpu_model; 208 const char *kernel_filename = args->kernel_filename; 209 const char *kernel_cmdline = args->kernel_cmdline; 210 const char *initrd_filename = args->initrd_filename; 211 DeviceState *dev = NULL; 212 SysBusDevice *busdev; 213 qemu_irq pic[128]; 214 int n; 215 qemu_irq cpu_irq[4]; 216 MemoryRegion *sysram; 217 MemoryRegion *dram; 218 MemoryRegion *sysmem; 219 char *sysboot_filename; 220 221 if (!cpu_model) { 222 switch (machine) { 223 case CALXEDA_HIGHBANK: 224 cpu_model = "cortex-a9"; 225 break; 226 case CALXEDA_MIDWAY: 227 cpu_model = "cortex-a15"; 228 break; 229 } 230 } 231 232 for (n = 0; n < smp_cpus; n++) { 233 ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 234 ARMCPU *cpu; 235 Error *err = NULL; 236 237 cpu = ARM_CPU(object_new(object_class_get_name(oc))); 238 239 object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", 240 &err); 241 if (err) { 242 error_report("%s", error_get_pretty(err)); 243 exit(1); 244 } 245 object_property_set_bool(OBJECT(cpu), true, "realized", &err); 246 if (err) { 247 error_report("%s", error_get_pretty(err)); 248 exit(1); 249 } 250 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ); 251 } 252 253 sysmem = get_system_memory(); 254 dram = g_new(MemoryRegion, 1); 255 memory_region_init_ram(dram, NULL, "highbank.dram", ram_size); 256 /* SDRAM at address zero. */ 257 memory_region_add_subregion(sysmem, 0, dram); 258 259 sysram = g_new(MemoryRegion, 1); 260 memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000); 261 memory_region_add_subregion(sysmem, 0xfff88000, sysram); 262 if (bios_name != NULL) { 263 sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 264 if (sysboot_filename != NULL) { 265 uint32_t filesize = get_image_size(sysboot_filename); 266 if (load_image_targphys("sysram.bin", 0xfff88000, filesize) < 0) { 267 hw_error("Unable to load %s\n", bios_name); 268 } 269 } else { 270 hw_error("Unable to find %s\n", bios_name); 271 } 272 } 273 274 switch (machine) { 275 case CALXEDA_HIGHBANK: 276 dev = qdev_create(NULL, "l2x0"); 277 qdev_init_nofail(dev); 278 busdev = SYS_BUS_DEVICE(dev); 279 sysbus_mmio_map(busdev, 0, 0xfff12000); 280 281 dev = qdev_create(NULL, "a9mpcore_priv"); 282 break; 283 case CALXEDA_MIDWAY: 284 dev = qdev_create(NULL, "a15mpcore_priv"); 285 break; 286 } 287 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 288 qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC); 289 qdev_init_nofail(dev); 290 busdev = SYS_BUS_DEVICE(dev); 291 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); 292 for (n = 0; n < smp_cpus; n++) { 293 sysbus_connect_irq(busdev, n, cpu_irq[n]); 294 } 295 296 for (n = 0; n < 128; n++) { 297 pic[n] = qdev_get_gpio_in(dev, n); 298 } 299 300 dev = qdev_create(NULL, "sp804"); 301 qdev_prop_set_uint32(dev, "freq0", 150000000); 302 qdev_prop_set_uint32(dev, "freq1", 150000000); 303 qdev_init_nofail(dev); 304 busdev = SYS_BUS_DEVICE(dev); 305 sysbus_mmio_map(busdev, 0, 0xfff34000); 306 sysbus_connect_irq(busdev, 0, pic[18]); 307 sysbus_create_simple("pl011", 0xfff36000, pic[20]); 308 309 dev = qdev_create(NULL, "highbank-regs"); 310 qdev_init_nofail(dev); 311 busdev = SYS_BUS_DEVICE(dev); 312 sysbus_mmio_map(busdev, 0, 0xfff3c000); 313 314 sysbus_create_simple("pl061", 0xfff30000, pic[14]); 315 sysbus_create_simple("pl061", 0xfff31000, pic[15]); 316 sysbus_create_simple("pl061", 0xfff32000, pic[16]); 317 sysbus_create_simple("pl061", 0xfff33000, pic[17]); 318 sysbus_create_simple("pl031", 0xfff35000, pic[19]); 319 sysbus_create_simple("pl022", 0xfff39000, pic[23]); 320 321 sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]); 322 323 if (nd_table[0].used) { 324 qemu_check_nic_model(&nd_table[0], "xgmac"); 325 dev = qdev_create(NULL, "xgmac"); 326 qdev_set_nic_properties(dev, &nd_table[0]); 327 qdev_init_nofail(dev); 328 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000); 329 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]); 330 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]); 331 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]); 332 333 qemu_check_nic_model(&nd_table[1], "xgmac"); 334 dev = qdev_create(NULL, "xgmac"); 335 qdev_set_nic_properties(dev, &nd_table[1]); 336 qdev_init_nofail(dev); 337 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000); 338 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]); 339 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]); 340 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]); 341 } 342 343 highbank_binfo.ram_size = ram_size; 344 highbank_binfo.kernel_filename = kernel_filename; 345 highbank_binfo.kernel_cmdline = kernel_cmdline; 346 highbank_binfo.initrd_filename = initrd_filename; 347 /* highbank requires a dtb in order to boot, and the dtb will override 348 * the board ID. The following value is ignored, so set it to -1 to be 349 * clear that the value is meaningless. 350 */ 351 highbank_binfo.board_id = -1; 352 highbank_binfo.nb_cpus = smp_cpus; 353 highbank_binfo.loader_start = 0; 354 highbank_binfo.write_secondary_boot = hb_write_secondary; 355 highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary; 356 arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo); 357 } 358 359 static void highbank_init(QEMUMachineInitArgs *args) 360 { 361 calxeda_init(args, CALXEDA_HIGHBANK); 362 } 363 364 static void midway_init(QEMUMachineInitArgs *args) 365 { 366 calxeda_init(args, CALXEDA_MIDWAY); 367 } 368 369 static QEMUMachine highbank_machine = { 370 .name = "highbank", 371 .desc = "Calxeda Highbank (ECX-1000)", 372 .init = highbank_init, 373 .block_default_type = IF_SCSI, 374 .max_cpus = 4, 375 }; 376 377 static QEMUMachine midway_machine = { 378 .name = "midway", 379 .desc = "Calxeda Midway (ECX-2000)", 380 .init = midway_init, 381 .block_default_type = IF_SCSI, 382 .max_cpus = 4, 383 }; 384 385 static void calxeda_machines_init(void) 386 { 387 qemu_register_machine(&highbank_machine); 388 qemu_register_machine(&midway_machine); 389 } 390 391 machine_init(calxeda_machines_init); 392