1 /* 2 * Calxeda Highbank SoC emulation 3 * 4 * Copyright (c) 2010-2012 Calxeda 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "hw/sysbus.h" 23 #include "hw/arm/arm.h" 24 #include "hw/devices.h" 25 #include "hw/loader.h" 26 #include "net/net.h" 27 #include "sysemu/kvm.h" 28 #include "sysemu/sysemu.h" 29 #include "hw/boards.h" 30 #include "sysemu/block-backend.h" 31 #include "exec/address-spaces.h" 32 #include "qemu/error-report.h" 33 34 #define SMP_BOOT_ADDR 0x100 35 #define SMP_BOOT_REG 0x40 36 #define MPCORE_PERIPHBASE 0xfff10000 37 38 #define MVBAR_ADDR 0x200 39 #define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t)) 40 41 #define NIRQ_GIC 160 42 43 /* Board init. */ 44 45 static void hb_write_board_setup(ARMCPU *cpu, 46 const struct arm_boot_info *info) 47 { 48 arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR); 49 } 50 51 static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 52 { 53 int n; 54 uint32_t smpboot[] = { 55 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */ 56 0xe210000f, /* ands r0, r0, #0x0f */ 57 0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */ 58 0xe0830200, /* add r0, r3, r0, lsl #4 */ 59 0xe59f2024, /* ldr r2, privbase */ 60 0xe3a01001, /* mov r1, #1 */ 61 0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */ 62 0xe3a010ff, /* mov r1, #0xff */ 63 0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */ 64 0xf57ff04f, /* dsb */ 65 0xe320f003, /* wfi */ 66 0xe5901000, /* ldr r1, [r0] */ 67 0xe1110001, /* tst r1, r1 */ 68 0x0afffffb, /* beq <wfi> */ 69 0xe12fff11, /* bx r1 */ 70 MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */ 71 }; 72 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 73 smpboot[n] = tswap32(smpboot[n]); 74 } 75 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR); 76 } 77 78 static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 79 { 80 CPUARMState *env = &cpu->env; 81 82 switch (info->nb_cpus) { 83 case 4: 84 address_space_stl_notdirty(&address_space_memory, 85 SMP_BOOT_REG + 0x30, 0, 86 MEMTXATTRS_UNSPECIFIED, NULL); 87 case 3: 88 address_space_stl_notdirty(&address_space_memory, 89 SMP_BOOT_REG + 0x20, 0, 90 MEMTXATTRS_UNSPECIFIED, NULL); 91 case 2: 92 address_space_stl_notdirty(&address_space_memory, 93 SMP_BOOT_REG + 0x10, 0, 94 MEMTXATTRS_UNSPECIFIED, NULL); 95 env->regs[15] = SMP_BOOT_ADDR; 96 break; 97 default: 98 break; 99 } 100 } 101 102 #define NUM_REGS 0x200 103 static void hb_regs_write(void *opaque, hwaddr offset, 104 uint64_t value, unsigned size) 105 { 106 uint32_t *regs = opaque; 107 108 if (offset == 0xf00) { 109 if (value == 1 || value == 2) { 110 qemu_system_reset_request(); 111 } else if (value == 3) { 112 qemu_system_shutdown_request(); 113 } 114 } 115 116 regs[offset/4] = value; 117 } 118 119 static uint64_t hb_regs_read(void *opaque, hwaddr offset, 120 unsigned size) 121 { 122 uint32_t *regs = opaque; 123 uint32_t value = regs[offset/4]; 124 125 if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) { 126 value |= 0x30000000; 127 } 128 129 return value; 130 } 131 132 static const MemoryRegionOps hb_mem_ops = { 133 .read = hb_regs_read, 134 .write = hb_regs_write, 135 .endianness = DEVICE_NATIVE_ENDIAN, 136 }; 137 138 #define TYPE_HIGHBANK_REGISTERS "highbank-regs" 139 #define HIGHBANK_REGISTERS(obj) \ 140 OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS) 141 142 typedef struct { 143 /*< private >*/ 144 SysBusDevice parent_obj; 145 /*< public >*/ 146 147 MemoryRegion iomem; 148 uint32_t regs[NUM_REGS]; 149 } HighbankRegsState; 150 151 static VMStateDescription vmstate_highbank_regs = { 152 .name = "highbank-regs", 153 .version_id = 0, 154 .minimum_version_id = 0, 155 .fields = (VMStateField[]) { 156 VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS), 157 VMSTATE_END_OF_LIST(), 158 }, 159 }; 160 161 static void highbank_regs_reset(DeviceState *dev) 162 { 163 HighbankRegsState *s = HIGHBANK_REGISTERS(dev); 164 165 s->regs[0x40] = 0x05F20121; 166 s->regs[0x41] = 0x2; 167 s->regs[0x42] = 0x05F30121; 168 s->regs[0x43] = 0x05F40121; 169 } 170 171 static int highbank_regs_init(SysBusDevice *dev) 172 { 173 HighbankRegsState *s = HIGHBANK_REGISTERS(dev); 174 175 memory_region_init_io(&s->iomem, OBJECT(s), &hb_mem_ops, s->regs, 176 "highbank_regs", 0x1000); 177 sysbus_init_mmio(dev, &s->iomem); 178 179 return 0; 180 } 181 182 static void highbank_regs_class_init(ObjectClass *klass, void *data) 183 { 184 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); 185 DeviceClass *dc = DEVICE_CLASS(klass); 186 187 sbc->init = highbank_regs_init; 188 dc->desc = "Calxeda Highbank registers"; 189 dc->vmsd = &vmstate_highbank_regs; 190 dc->reset = highbank_regs_reset; 191 } 192 193 static const TypeInfo highbank_regs_info = { 194 .name = TYPE_HIGHBANK_REGISTERS, 195 .parent = TYPE_SYS_BUS_DEVICE, 196 .instance_size = sizeof(HighbankRegsState), 197 .class_init = highbank_regs_class_init, 198 }; 199 200 static void highbank_regs_register_types(void) 201 { 202 type_register_static(&highbank_regs_info); 203 } 204 205 type_init(highbank_regs_register_types) 206 207 static struct arm_boot_info highbank_binfo; 208 209 enum cxmachines { 210 CALXEDA_HIGHBANK, 211 CALXEDA_MIDWAY, 212 }; 213 214 /* ram_size must be set to match the upper bound of memory in the 215 * device tree (linux/arch/arm/boot/dts/highbank.dts), which is 216 * normally 0xff900000 or -m 4089. When running this board on a 217 * 32-bit host, set the reg value of memory to 0xf7ff00000 in the 218 * device tree and pass -m 2047 to QEMU. 219 */ 220 static void calxeda_init(MachineState *machine, enum cxmachines machine_id) 221 { 222 ram_addr_t ram_size = machine->ram_size; 223 const char *cpu_model = machine->cpu_model; 224 const char *kernel_filename = machine->kernel_filename; 225 const char *kernel_cmdline = machine->kernel_cmdline; 226 const char *initrd_filename = machine->initrd_filename; 227 DeviceState *dev = NULL; 228 SysBusDevice *busdev; 229 qemu_irq pic[128]; 230 int n; 231 qemu_irq cpu_irq[4]; 232 qemu_irq cpu_fiq[4]; 233 MemoryRegion *sysram; 234 MemoryRegion *dram; 235 MemoryRegion *sysmem; 236 char *sysboot_filename; 237 238 switch (machine_id) { 239 case CALXEDA_HIGHBANK: 240 cpu_model = "cortex-a9"; 241 break; 242 case CALXEDA_MIDWAY: 243 cpu_model = "cortex-a15"; 244 break; 245 } 246 247 for (n = 0; n < smp_cpus; n++) { 248 ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 249 Object *cpuobj; 250 ARMCPU *cpu; 251 252 cpuobj = object_new(object_class_get_name(oc)); 253 cpu = ARM_CPU(cpuobj); 254 255 object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC, 256 "psci-conduit", &error_abort); 257 258 if (n) { 259 /* Secondary CPUs start in PSCI powered-down state */ 260 object_property_set_bool(cpuobj, true, 261 "start-powered-off", &error_abort); 262 } 263 264 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 265 object_property_set_int(cpuobj, MPCORE_PERIPHBASE, 266 "reset-cbar", &error_abort); 267 } 268 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 269 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ); 270 cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ); 271 } 272 273 sysmem = get_system_memory(); 274 dram = g_new(MemoryRegion, 1); 275 memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size); 276 /* SDRAM at address zero. */ 277 memory_region_add_subregion(sysmem, 0, dram); 278 279 sysram = g_new(MemoryRegion, 1); 280 memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000, 281 &error_fatal); 282 memory_region_add_subregion(sysmem, 0xfff88000, sysram); 283 if (bios_name != NULL) { 284 sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 285 if (sysboot_filename != NULL) { 286 if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) { 287 error_report("Unable to load %s", bios_name); 288 exit(1); 289 } 290 g_free(sysboot_filename); 291 } else { 292 error_report("Unable to find %s", bios_name); 293 exit(1); 294 } 295 } 296 297 switch (machine_id) { 298 case CALXEDA_HIGHBANK: 299 dev = qdev_create(NULL, "l2x0"); 300 qdev_init_nofail(dev); 301 busdev = SYS_BUS_DEVICE(dev); 302 sysbus_mmio_map(busdev, 0, 0xfff12000); 303 304 dev = qdev_create(NULL, "a9mpcore_priv"); 305 break; 306 case CALXEDA_MIDWAY: 307 dev = qdev_create(NULL, "a15mpcore_priv"); 308 break; 309 } 310 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 311 qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC); 312 qdev_init_nofail(dev); 313 busdev = SYS_BUS_DEVICE(dev); 314 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); 315 for (n = 0; n < smp_cpus; n++) { 316 sysbus_connect_irq(busdev, n, cpu_irq[n]); 317 sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]); 318 } 319 320 for (n = 0; n < 128; n++) { 321 pic[n] = qdev_get_gpio_in(dev, n); 322 } 323 324 dev = qdev_create(NULL, "sp804"); 325 qdev_prop_set_uint32(dev, "freq0", 150000000); 326 qdev_prop_set_uint32(dev, "freq1", 150000000); 327 qdev_init_nofail(dev); 328 busdev = SYS_BUS_DEVICE(dev); 329 sysbus_mmio_map(busdev, 0, 0xfff34000); 330 sysbus_connect_irq(busdev, 0, pic[18]); 331 sysbus_create_simple("pl011", 0xfff36000, pic[20]); 332 333 dev = qdev_create(NULL, "highbank-regs"); 334 qdev_init_nofail(dev); 335 busdev = SYS_BUS_DEVICE(dev); 336 sysbus_mmio_map(busdev, 0, 0xfff3c000); 337 338 sysbus_create_simple("pl061", 0xfff30000, pic[14]); 339 sysbus_create_simple("pl061", 0xfff31000, pic[15]); 340 sysbus_create_simple("pl061", 0xfff32000, pic[16]); 341 sysbus_create_simple("pl061", 0xfff33000, pic[17]); 342 sysbus_create_simple("pl031", 0xfff35000, pic[19]); 343 sysbus_create_simple("pl022", 0xfff39000, pic[23]); 344 345 sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]); 346 347 if (nd_table[0].used) { 348 qemu_check_nic_model(&nd_table[0], "xgmac"); 349 dev = qdev_create(NULL, "xgmac"); 350 qdev_set_nic_properties(dev, &nd_table[0]); 351 qdev_init_nofail(dev); 352 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000); 353 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]); 354 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]); 355 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]); 356 357 qemu_check_nic_model(&nd_table[1], "xgmac"); 358 dev = qdev_create(NULL, "xgmac"); 359 qdev_set_nic_properties(dev, &nd_table[1]); 360 qdev_init_nofail(dev); 361 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000); 362 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]); 363 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]); 364 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]); 365 } 366 367 highbank_binfo.ram_size = ram_size; 368 highbank_binfo.kernel_filename = kernel_filename; 369 highbank_binfo.kernel_cmdline = kernel_cmdline; 370 highbank_binfo.initrd_filename = initrd_filename; 371 /* highbank requires a dtb in order to boot, and the dtb will override 372 * the board ID. The following value is ignored, so set it to -1 to be 373 * clear that the value is meaningless. 374 */ 375 highbank_binfo.board_id = -1; 376 highbank_binfo.nb_cpus = smp_cpus; 377 highbank_binfo.loader_start = 0; 378 highbank_binfo.write_secondary_boot = hb_write_secondary; 379 highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary; 380 if (!kvm_enabled()) { 381 highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR; 382 highbank_binfo.write_board_setup = hb_write_board_setup; 383 highbank_binfo.secure_board_setup = true; 384 } else { 385 error_report("WARNING: cannot load built-in Monitor support " 386 "if KVM is enabled. Some guests (such as Linux) " 387 "may not boot."); 388 } 389 390 arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo); 391 } 392 393 static void highbank_init(MachineState *machine) 394 { 395 calxeda_init(machine, CALXEDA_HIGHBANK); 396 } 397 398 static void midway_init(MachineState *machine) 399 { 400 calxeda_init(machine, CALXEDA_MIDWAY); 401 } 402 403 static void highbank_class_init(ObjectClass *oc, void *data) 404 { 405 MachineClass *mc = MACHINE_CLASS(oc); 406 407 mc->desc = "Calxeda Highbank (ECX-1000)"; 408 mc->init = highbank_init; 409 mc->block_default_type = IF_SCSI; 410 mc->max_cpus = 4; 411 } 412 413 static const TypeInfo highbank_type = { 414 .name = MACHINE_TYPE_NAME("highbank"), 415 .parent = TYPE_MACHINE, 416 .class_init = highbank_class_init, 417 }; 418 419 static void midway_class_init(ObjectClass *oc, void *data) 420 { 421 MachineClass *mc = MACHINE_CLASS(oc); 422 423 mc->desc = "Calxeda Midway (ECX-2000)"; 424 mc->init = midway_init; 425 mc->block_default_type = IF_SCSI; 426 mc->max_cpus = 4; 427 } 428 429 static const TypeInfo midway_type = { 430 .name = MACHINE_TYPE_NAME("midway"), 431 .parent = TYPE_MACHINE, 432 .class_init = midway_class_init, 433 }; 434 435 static void calxeda_machines_init(void) 436 { 437 type_register_static(&highbank_type); 438 type_register_static(&midway_type); 439 } 440 441 type_init(calxeda_machines_init) 442