1 /* 2 * Calxeda Highbank SoC emulation 3 * 4 * Copyright (c) 2010-2012 Calxeda 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "hw/sysbus.h" 23 #include "hw/arm/arm.h" 24 #include "hw/devices.h" 25 #include "hw/loader.h" 26 #include "net/net.h" 27 #include "sysemu/kvm.h" 28 #include "sysemu/sysemu.h" 29 #include "hw/boards.h" 30 #include "sysemu/block-backend.h" 31 #include "exec/address-spaces.h" 32 #include "qemu/error-report.h" 33 #include "hw/char/pl011.h" 34 35 #define SMP_BOOT_ADDR 0x100 36 #define SMP_BOOT_REG 0x40 37 #define MPCORE_PERIPHBASE 0xfff10000 38 39 #define MVBAR_ADDR 0x200 40 #define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t)) 41 42 #define NIRQ_GIC 160 43 44 /* Board init. */ 45 46 static void hb_write_board_setup(ARMCPU *cpu, 47 const struct arm_boot_info *info) 48 { 49 arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR); 50 } 51 52 static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 53 { 54 int n; 55 uint32_t smpboot[] = { 56 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */ 57 0xe210000f, /* ands r0, r0, #0x0f */ 58 0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */ 59 0xe0830200, /* add r0, r3, r0, lsl #4 */ 60 0xe59f2024, /* ldr r2, privbase */ 61 0xe3a01001, /* mov r1, #1 */ 62 0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */ 63 0xe3a010ff, /* mov r1, #0xff */ 64 0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */ 65 0xf57ff04f, /* dsb */ 66 0xe320f003, /* wfi */ 67 0xe5901000, /* ldr r1, [r0] */ 68 0xe1110001, /* tst r1, r1 */ 69 0x0afffffb, /* beq <wfi> */ 70 0xe12fff11, /* bx r1 */ 71 MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */ 72 }; 73 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { 74 smpboot[n] = tswap32(smpboot[n]); 75 } 76 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR); 77 } 78 79 static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 80 { 81 CPUARMState *env = &cpu->env; 82 83 switch (info->nb_cpus) { 84 case 4: 85 address_space_stl_notdirty(&address_space_memory, 86 SMP_BOOT_REG + 0x30, 0, 87 MEMTXATTRS_UNSPECIFIED, NULL); 88 case 3: 89 address_space_stl_notdirty(&address_space_memory, 90 SMP_BOOT_REG + 0x20, 0, 91 MEMTXATTRS_UNSPECIFIED, NULL); 92 case 2: 93 address_space_stl_notdirty(&address_space_memory, 94 SMP_BOOT_REG + 0x10, 0, 95 MEMTXATTRS_UNSPECIFIED, NULL); 96 env->regs[15] = SMP_BOOT_ADDR; 97 break; 98 default: 99 break; 100 } 101 } 102 103 #define NUM_REGS 0x200 104 static void hb_regs_write(void *opaque, hwaddr offset, 105 uint64_t value, unsigned size) 106 { 107 uint32_t *regs = opaque; 108 109 if (offset == 0xf00) { 110 if (value == 1 || value == 2) { 111 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 112 } else if (value == 3) { 113 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 114 } 115 } 116 117 regs[offset/4] = value; 118 } 119 120 static uint64_t hb_regs_read(void *opaque, hwaddr offset, 121 unsigned size) 122 { 123 uint32_t *regs = opaque; 124 uint32_t value = regs[offset/4]; 125 126 if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) { 127 value |= 0x30000000; 128 } 129 130 return value; 131 } 132 133 static const MemoryRegionOps hb_mem_ops = { 134 .read = hb_regs_read, 135 .write = hb_regs_write, 136 .endianness = DEVICE_NATIVE_ENDIAN, 137 }; 138 139 #define TYPE_HIGHBANK_REGISTERS "highbank-regs" 140 #define HIGHBANK_REGISTERS(obj) \ 141 OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS) 142 143 typedef struct { 144 /*< private >*/ 145 SysBusDevice parent_obj; 146 /*< public >*/ 147 148 MemoryRegion iomem; 149 uint32_t regs[NUM_REGS]; 150 } HighbankRegsState; 151 152 static VMStateDescription vmstate_highbank_regs = { 153 .name = "highbank-regs", 154 .version_id = 0, 155 .minimum_version_id = 0, 156 .fields = (VMStateField[]) { 157 VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS), 158 VMSTATE_END_OF_LIST(), 159 }, 160 }; 161 162 static void highbank_regs_reset(DeviceState *dev) 163 { 164 HighbankRegsState *s = HIGHBANK_REGISTERS(dev); 165 166 s->regs[0x40] = 0x05F20121; 167 s->regs[0x41] = 0x2; 168 s->regs[0x42] = 0x05F30121; 169 s->regs[0x43] = 0x05F40121; 170 } 171 172 static void highbank_regs_init(Object *obj) 173 { 174 HighbankRegsState *s = HIGHBANK_REGISTERS(obj); 175 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 176 177 memory_region_init_io(&s->iomem, obj, &hb_mem_ops, s->regs, 178 "highbank_regs", 0x1000); 179 sysbus_init_mmio(dev, &s->iomem); 180 } 181 182 static void highbank_regs_class_init(ObjectClass *klass, void *data) 183 { 184 DeviceClass *dc = DEVICE_CLASS(klass); 185 186 dc->desc = "Calxeda Highbank registers"; 187 dc->vmsd = &vmstate_highbank_regs; 188 dc->reset = highbank_regs_reset; 189 } 190 191 static const TypeInfo highbank_regs_info = { 192 .name = TYPE_HIGHBANK_REGISTERS, 193 .parent = TYPE_SYS_BUS_DEVICE, 194 .instance_size = sizeof(HighbankRegsState), 195 .instance_init = highbank_regs_init, 196 .class_init = highbank_regs_class_init, 197 }; 198 199 static void highbank_regs_register_types(void) 200 { 201 type_register_static(&highbank_regs_info); 202 } 203 204 type_init(highbank_regs_register_types) 205 206 static struct arm_boot_info highbank_binfo; 207 208 enum cxmachines { 209 CALXEDA_HIGHBANK, 210 CALXEDA_MIDWAY, 211 }; 212 213 /* ram_size must be set to match the upper bound of memory in the 214 * device tree (linux/arch/arm/boot/dts/highbank.dts), which is 215 * normally 0xff900000 or -m 4089. When running this board on a 216 * 32-bit host, set the reg value of memory to 0xf7ff00000 in the 217 * device tree and pass -m 2047 to QEMU. 218 */ 219 static void calxeda_init(MachineState *machine, enum cxmachines machine_id) 220 { 221 ram_addr_t ram_size = machine->ram_size; 222 const char *cpu_model = machine->cpu_model; 223 const char *kernel_filename = machine->kernel_filename; 224 const char *kernel_cmdline = machine->kernel_cmdline; 225 const char *initrd_filename = machine->initrd_filename; 226 DeviceState *dev = NULL; 227 SysBusDevice *busdev; 228 qemu_irq pic[128]; 229 int n; 230 qemu_irq cpu_irq[4]; 231 qemu_irq cpu_fiq[4]; 232 MemoryRegion *sysram; 233 MemoryRegion *dram; 234 MemoryRegion *sysmem; 235 char *sysboot_filename; 236 237 switch (machine_id) { 238 case CALXEDA_HIGHBANK: 239 cpu_model = "cortex-a9"; 240 break; 241 case CALXEDA_MIDWAY: 242 cpu_model = "cortex-a15"; 243 break; 244 } 245 246 for (n = 0; n < smp_cpus; n++) { 247 ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 248 Object *cpuobj; 249 ARMCPU *cpu; 250 251 cpuobj = object_new(object_class_get_name(oc)); 252 cpu = ARM_CPU(cpuobj); 253 254 object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC, 255 "psci-conduit", &error_abort); 256 257 if (n) { 258 /* Secondary CPUs start in PSCI powered-down state */ 259 object_property_set_bool(cpuobj, true, 260 "start-powered-off", &error_abort); 261 } 262 263 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 264 object_property_set_int(cpuobj, MPCORE_PERIPHBASE, 265 "reset-cbar", &error_abort); 266 } 267 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 268 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ); 269 cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ); 270 } 271 272 sysmem = get_system_memory(); 273 dram = g_new(MemoryRegion, 1); 274 memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size); 275 /* SDRAM at address zero. */ 276 memory_region_add_subregion(sysmem, 0, dram); 277 278 sysram = g_new(MemoryRegion, 1); 279 memory_region_init_ram_nomigrate(sysram, NULL, "highbank.sysram", 0x8000, 280 &error_fatal); 281 memory_region_add_subregion(sysmem, 0xfff88000, sysram); 282 if (bios_name != NULL) { 283 sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 284 if (sysboot_filename != NULL) { 285 if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) { 286 error_report("Unable to load %s", bios_name); 287 exit(1); 288 } 289 g_free(sysboot_filename); 290 } else { 291 error_report("Unable to find %s", bios_name); 292 exit(1); 293 } 294 } 295 296 switch (machine_id) { 297 case CALXEDA_HIGHBANK: 298 dev = qdev_create(NULL, "l2x0"); 299 qdev_init_nofail(dev); 300 busdev = SYS_BUS_DEVICE(dev); 301 sysbus_mmio_map(busdev, 0, 0xfff12000); 302 303 dev = qdev_create(NULL, "a9mpcore_priv"); 304 break; 305 case CALXEDA_MIDWAY: 306 dev = qdev_create(NULL, "a15mpcore_priv"); 307 break; 308 } 309 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 310 qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC); 311 qdev_init_nofail(dev); 312 busdev = SYS_BUS_DEVICE(dev); 313 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); 314 for (n = 0; n < smp_cpus; n++) { 315 sysbus_connect_irq(busdev, n, cpu_irq[n]); 316 sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]); 317 } 318 319 for (n = 0; n < 128; n++) { 320 pic[n] = qdev_get_gpio_in(dev, n); 321 } 322 323 dev = qdev_create(NULL, "sp804"); 324 qdev_prop_set_uint32(dev, "freq0", 150000000); 325 qdev_prop_set_uint32(dev, "freq1", 150000000); 326 qdev_init_nofail(dev); 327 busdev = SYS_BUS_DEVICE(dev); 328 sysbus_mmio_map(busdev, 0, 0xfff34000); 329 sysbus_connect_irq(busdev, 0, pic[18]); 330 pl011_create(0xfff36000, pic[20], serial_hds[0]); 331 332 dev = qdev_create(NULL, "highbank-regs"); 333 qdev_init_nofail(dev); 334 busdev = SYS_BUS_DEVICE(dev); 335 sysbus_mmio_map(busdev, 0, 0xfff3c000); 336 337 sysbus_create_simple("pl061", 0xfff30000, pic[14]); 338 sysbus_create_simple("pl061", 0xfff31000, pic[15]); 339 sysbus_create_simple("pl061", 0xfff32000, pic[16]); 340 sysbus_create_simple("pl061", 0xfff33000, pic[17]); 341 sysbus_create_simple("pl031", 0xfff35000, pic[19]); 342 sysbus_create_simple("pl022", 0xfff39000, pic[23]); 343 344 sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]); 345 346 if (nd_table[0].used) { 347 qemu_check_nic_model(&nd_table[0], "xgmac"); 348 dev = qdev_create(NULL, "xgmac"); 349 qdev_set_nic_properties(dev, &nd_table[0]); 350 qdev_init_nofail(dev); 351 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000); 352 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]); 353 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]); 354 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]); 355 356 qemu_check_nic_model(&nd_table[1], "xgmac"); 357 dev = qdev_create(NULL, "xgmac"); 358 qdev_set_nic_properties(dev, &nd_table[1]); 359 qdev_init_nofail(dev); 360 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000); 361 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]); 362 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]); 363 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]); 364 } 365 366 /* TODO create and connect IDE devices for ide_drive_get() */ 367 368 highbank_binfo.ram_size = ram_size; 369 highbank_binfo.kernel_filename = kernel_filename; 370 highbank_binfo.kernel_cmdline = kernel_cmdline; 371 highbank_binfo.initrd_filename = initrd_filename; 372 /* highbank requires a dtb in order to boot, and the dtb will override 373 * the board ID. The following value is ignored, so set it to -1 to be 374 * clear that the value is meaningless. 375 */ 376 highbank_binfo.board_id = -1; 377 highbank_binfo.nb_cpus = smp_cpus; 378 highbank_binfo.loader_start = 0; 379 highbank_binfo.write_secondary_boot = hb_write_secondary; 380 highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary; 381 if (!kvm_enabled()) { 382 highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR; 383 highbank_binfo.write_board_setup = hb_write_board_setup; 384 highbank_binfo.secure_board_setup = true; 385 } else { 386 warn_report("cannot load built-in Monitor support " 387 "if KVM is enabled. Some guests (such as Linux) " 388 "may not boot."); 389 } 390 391 arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo); 392 } 393 394 static void highbank_init(MachineState *machine) 395 { 396 calxeda_init(machine, CALXEDA_HIGHBANK); 397 } 398 399 static void midway_init(MachineState *machine) 400 { 401 calxeda_init(machine, CALXEDA_MIDWAY); 402 } 403 404 static void highbank_class_init(ObjectClass *oc, void *data) 405 { 406 MachineClass *mc = MACHINE_CLASS(oc); 407 408 mc->desc = "Calxeda Highbank (ECX-1000)"; 409 mc->init = highbank_init; 410 mc->block_default_type = IF_IDE; 411 mc->units_per_default_bus = 1; 412 mc->max_cpus = 4; 413 } 414 415 static const TypeInfo highbank_type = { 416 .name = MACHINE_TYPE_NAME("highbank"), 417 .parent = TYPE_MACHINE, 418 .class_init = highbank_class_init, 419 }; 420 421 static void midway_class_init(ObjectClass *oc, void *data) 422 { 423 MachineClass *mc = MACHINE_CLASS(oc); 424 425 mc->desc = "Calxeda Midway (ECX-2000)"; 426 mc->init = midway_init; 427 mc->block_default_type = IF_IDE; 428 mc->units_per_default_bus = 1; 429 mc->max_cpus = 4; 430 } 431 432 static const TypeInfo midway_type = { 433 .name = MACHINE_TYPE_NAME("midway"), 434 .parent = TYPE_MACHINE, 435 .class_init = midway_class_init, 436 }; 437 438 static void calxeda_machines_init(void) 439 { 440 type_register_static(&highbank_type); 441 type_register_static(&midway_type); 442 } 443 444 type_init(calxeda_machines_init) 445