1 /* 2 * i.MX 8M Plus SoC Implementation 3 * 4 * Based on hw/arm/fsl-imx6.c 5 * 6 * Copyright (c) 2024, Bernhard Beschow <shentey@gmail.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0-or-later 9 */ 10 11 #include "qemu/osdep.h" 12 #include "exec/address-spaces.h" 13 #include "hw/arm/bsa.h" 14 #include "hw/arm/fsl-imx8mp.h" 15 #include "hw/intc/arm_gicv3.h" 16 #include "hw/misc/unimp.h" 17 #include "hw/boards.h" 18 #include "system/system.h" 19 #include "target/arm/cpu-qom.h" 20 #include "qapi/error.h" 21 #include "qobject/qlist.h" 22 23 static const struct { 24 hwaddr addr; 25 size_t size; 26 const char *name; 27 } fsl_imx8mp_memmap[] = { 28 [FSL_IMX8MP_RAM] = { FSL_IMX8MP_RAM_START, FSL_IMX8MP_RAM_SIZE_MAX, "ram" }, 29 [FSL_IMX8MP_DDR_PHY_BROADCAST] = { 0x3dc00000, 4 * MiB, "ddr_phy_broadcast" }, 30 [FSL_IMX8MP_DDR_PERF_MON] = { 0x3d800000, 4 * MiB, "ddr_perf_mon" }, 31 [FSL_IMX8MP_DDR_CTL] = { 0x3d400000, 4 * MiB, "ddr_ctl" }, 32 [FSL_IMX8MP_DDR_BLK_CTRL] = { 0x3d000000, 1 * MiB, "ddr_blk_ctrl" }, 33 [FSL_IMX8MP_DDR_PHY] = { 0x3c000000, 16 * MiB, "ddr_phy" }, 34 [FSL_IMX8MP_AUDIO_DSP] = { 0x3b000000, 16 * MiB, "audio_dsp" }, 35 [FSL_IMX8MP_GIC_DIST] = { 0x38800000, 512 * KiB, "gic_dist" }, 36 [FSL_IMX8MP_GIC_REDIST] = { 0x38880000, 512 * KiB, "gic_redist" }, 37 [FSL_IMX8MP_NPU] = { 0x38500000, 2 * MiB, "npu" }, 38 [FSL_IMX8MP_VPU] = { 0x38340000, 2 * MiB, "vpu" }, 39 [FSL_IMX8MP_VPU_BLK_CTRL] = { 0x38330000, 2 * MiB, "vpu_blk_ctrl" }, 40 [FSL_IMX8MP_VPU_VC8000E_ENCODER] = { 0x38320000, 2 * MiB, "vpu_vc8000e_encoder" }, 41 [FSL_IMX8MP_VPU_G2_DECODER] = { 0x38310000, 2 * MiB, "vpu_g2_decoder" }, 42 [FSL_IMX8MP_VPU_G1_DECODER] = { 0x38300000, 2 * MiB, "vpu_g1_decoder" }, 43 [FSL_IMX8MP_USB2] = { 0x38200000, 1 * MiB, "usb2" }, 44 [FSL_IMX8MP_USB1] = { 0x38100000, 1 * MiB, "usb1" }, 45 [FSL_IMX8MP_GPU2D] = { 0x38008000, 32 * KiB, "gpu2d" }, 46 [FSL_IMX8MP_GPU3D] = { 0x38000000, 32 * KiB, "gpu3d" }, 47 [FSL_IMX8MP_QSPI1_RX_BUFFER] = { 0x34000000, 32 * MiB, "qspi1_rx_buffer" }, 48 [FSL_IMX8MP_PCIE1] = { 0x33800000, 4 * MiB, "pcie1" }, 49 [FSL_IMX8MP_QSPI1_TX_BUFFER] = { 0x33008000, 32 * KiB, "qspi1_tx_buffer" }, 50 [FSL_IMX8MP_APBH_DMA] = { 0x33000000, 32 * KiB, "apbh_dma" }, 51 52 /* AIPS-5 Begin */ 53 [FSL_IMX8MP_MU_3_B] = { 0x30e90000, 64 * KiB, "mu_3_b" }, 54 [FSL_IMX8MP_MU_3_A] = { 0x30e80000, 64 * KiB, "mu_3_a" }, 55 [FSL_IMX8MP_MU_2_B] = { 0x30e70000, 64 * KiB, "mu_2_b" }, 56 [FSL_IMX8MP_MU_2_A] = { 0x30e60000, 64 * KiB, "mu_2_a" }, 57 [FSL_IMX8MP_EDMA_CHANNELS] = { 0x30e40000, 128 * KiB, "edma_channels" }, 58 [FSL_IMX8MP_EDMA_MANAGEMENT_PAGE] = { 0x30e30000, 64 * KiB, "edma_management_page" }, 59 [FSL_IMX8MP_AUDIO_BLK_CTRL] = { 0x30e20000, 64 * KiB, "audio_blk_ctrl" }, 60 [FSL_IMX8MP_SDMA2] = { 0x30e10000, 64 * KiB, "sdma2" }, 61 [FSL_IMX8MP_SDMA3] = { 0x30e00000, 64 * KiB, "sdma3" }, 62 [FSL_IMX8MP_AIPS5_CONFIGURATION] = { 0x30df0000, 64 * KiB, "aips5_configuration" }, 63 [FSL_IMX8MP_SPBA2] = { 0x30cf0000, 64 * KiB, "spba2" }, 64 [FSL_IMX8MP_AUDIO_XCVR_RX] = { 0x30cc0000, 64 * KiB, "audio_xcvr_rx" }, 65 [FSL_IMX8MP_HDMI_TX_AUDLNK_MSTR] = { 0x30cb0000, 64 * KiB, "hdmi_tx_audlnk_mstr" }, 66 [FSL_IMX8MP_PDM] = { 0x30ca0000, 64 * KiB, "pdm" }, 67 [FSL_IMX8MP_ASRC] = { 0x30c90000, 64 * KiB, "asrc" }, 68 [FSL_IMX8MP_SAI7] = { 0x30c80000, 64 * KiB, "sai7" }, 69 [FSL_IMX8MP_SAI6] = { 0x30c60000, 64 * KiB, "sai6" }, 70 [FSL_IMX8MP_SAI5] = { 0x30c50000, 64 * KiB, "sai5" }, 71 [FSL_IMX8MP_SAI3] = { 0x30c30000, 64 * KiB, "sai3" }, 72 [FSL_IMX8MP_SAI2] = { 0x30c20000, 64 * KiB, "sai2" }, 73 [FSL_IMX8MP_SAI1] = { 0x30c10000, 64 * KiB, "sai1" }, 74 /* AIPS-5 End */ 75 76 /* AIPS-4 Begin */ 77 [FSL_IMX8MP_HDMI_TX] = { 0x32fc0000, 128 * KiB, "hdmi_tx" }, 78 [FSL_IMX8MP_TZASC] = { 0x32f80000, 64 * KiB, "tzasc" }, 79 [FSL_IMX8MP_HSIO_BLK_CTL] = { 0x32f10000, 64 * KiB, "hsio_blk_ctl" }, 80 [FSL_IMX8MP_PCIE_PHY1] = { 0x32f00000, 64 * KiB, "pcie_phy1" }, 81 [FSL_IMX8MP_MEDIA_BLK_CTL] = { 0x32ec0000, 64 * KiB, "media_blk_ctl" }, 82 [FSL_IMX8MP_LCDIF2] = { 0x32e90000, 64 * KiB, "lcdif2" }, 83 [FSL_IMX8MP_LCDIF1] = { 0x32e80000, 64 * KiB, "lcdif1" }, 84 [FSL_IMX8MP_MIPI_DSI1] = { 0x32e60000, 64 * KiB, "mipi_dsi1" }, 85 [FSL_IMX8MP_MIPI_CSI2] = { 0x32e50000, 64 * KiB, "mipi_csi2" }, 86 [FSL_IMX8MP_MIPI_CSI1] = { 0x32e40000, 64 * KiB, "mipi_csi1" }, 87 [FSL_IMX8MP_IPS_DEWARP] = { 0x32e30000, 64 * KiB, "ips_dewarp" }, 88 [FSL_IMX8MP_ISP2] = { 0x32e20000, 64 * KiB, "isp2" }, 89 [FSL_IMX8MP_ISP1] = { 0x32e10000, 64 * KiB, "isp1" }, 90 [FSL_IMX8MP_ISI] = { 0x32e00000, 64 * KiB, "isi" }, 91 [FSL_IMX8MP_AIPS4_CONFIGURATION] = { 0x32df0000, 64 * KiB, "aips4_configuration" }, 92 /* AIPS-4 End */ 93 94 [FSL_IMX8MP_INTERCONNECT] = { 0x32700000, 1 * MiB, "interconnect" }, 95 96 /* AIPS-3 Begin */ 97 [FSL_IMX8MP_ENET2_TSN] = { 0x30bf0000, 64 * KiB, "enet2_tsn" }, 98 [FSL_IMX8MP_ENET1] = { 0x30be0000, 64 * KiB, "enet1" }, 99 [FSL_IMX8MP_SDMA1] = { 0x30bd0000, 64 * KiB, "sdma1" }, 100 [FSL_IMX8MP_QSPI] = { 0x30bb0000, 64 * KiB, "qspi" }, 101 [FSL_IMX8MP_USDHC3] = { 0x30b60000, 64 * KiB, "usdhc3" }, 102 [FSL_IMX8MP_USDHC2] = { 0x30b50000, 64 * KiB, "usdhc2" }, 103 [FSL_IMX8MP_USDHC1] = { 0x30b40000, 64 * KiB, "usdhc1" }, 104 [FSL_IMX8MP_I2C6] = { 0x30ae0000, 64 * KiB, "i2c6" }, 105 [FSL_IMX8MP_I2C5] = { 0x30ad0000, 64 * KiB, "i2c5" }, 106 [FSL_IMX8MP_SEMAPHORE_HS] = { 0x30ac0000, 64 * KiB, "semaphore_hs" }, 107 [FSL_IMX8MP_MU_1_B] = { 0x30ab0000, 64 * KiB, "mu_1_b" }, 108 [FSL_IMX8MP_MU_1_A] = { 0x30aa0000, 64 * KiB, "mu_1_a" }, 109 [FSL_IMX8MP_AUD_IRQ_STEER] = { 0x30a80000, 64 * KiB, "aud_irq_steer" }, 110 [FSL_IMX8MP_UART4] = { 0x30a60000, 64 * KiB, "uart4" }, 111 [FSL_IMX8MP_I2C4] = { 0x30a50000, 64 * KiB, "i2c4" }, 112 [FSL_IMX8MP_I2C3] = { 0x30a40000, 64 * KiB, "i2c3" }, 113 [FSL_IMX8MP_I2C2] = { 0x30a30000, 64 * KiB, "i2c2" }, 114 [FSL_IMX8MP_I2C1] = { 0x30a20000, 64 * KiB, "i2c1" }, 115 [FSL_IMX8MP_AIPS3_CONFIGURATION] = { 0x309f0000, 64 * KiB, "aips3_configuration" }, 116 [FSL_IMX8MP_CAAM] = { 0x30900000, 256 * KiB, "caam" }, 117 [FSL_IMX8MP_SPBA1] = { 0x308f0000, 64 * KiB, "spba1" }, 118 [FSL_IMX8MP_FLEXCAN2] = { 0x308d0000, 64 * KiB, "flexcan2" }, 119 [FSL_IMX8MP_FLEXCAN1] = { 0x308c0000, 64 * KiB, "flexcan1" }, 120 [FSL_IMX8MP_UART2] = { 0x30890000, 64 * KiB, "uart2" }, 121 [FSL_IMX8MP_UART3] = { 0x30880000, 64 * KiB, "uart3" }, 122 [FSL_IMX8MP_UART1] = { 0x30860000, 64 * KiB, "uart1" }, 123 [FSL_IMX8MP_ECSPI3] = { 0x30840000, 64 * KiB, "ecspi3" }, 124 [FSL_IMX8MP_ECSPI2] = { 0x30830000, 64 * KiB, "ecspi2" }, 125 [FSL_IMX8MP_ECSPI1] = { 0x30820000, 64 * KiB, "ecspi1" }, 126 /* AIPS-3 End */ 127 128 /* AIPS-2 Begin */ 129 [FSL_IMX8MP_QOSC] = { 0x307f0000, 64 * KiB, "qosc" }, 130 [FSL_IMX8MP_PERFMON2] = { 0x307d0000, 64 * KiB, "perfmon2" }, 131 [FSL_IMX8MP_PERFMON1] = { 0x307c0000, 64 * KiB, "perfmon1" }, 132 [FSL_IMX8MP_GPT4] = { 0x30700000, 64 * KiB, "gpt4" }, 133 [FSL_IMX8MP_GPT5] = { 0x306f0000, 64 * KiB, "gpt5" }, 134 [FSL_IMX8MP_GPT6] = { 0x306e0000, 64 * KiB, "gpt6" }, 135 [FSL_IMX8MP_SYSCNT_CTRL] = { 0x306c0000, 64 * KiB, "syscnt_ctrl" }, 136 [FSL_IMX8MP_SYSCNT_CMP] = { 0x306b0000, 64 * KiB, "syscnt_cmp" }, 137 [FSL_IMX8MP_SYSCNT_RD] = { 0x306a0000, 64 * KiB, "syscnt_rd" }, 138 [FSL_IMX8MP_PWM4] = { 0x30690000, 64 * KiB, "pwm4" }, 139 [FSL_IMX8MP_PWM3] = { 0x30680000, 64 * KiB, "pwm3" }, 140 [FSL_IMX8MP_PWM2] = { 0x30670000, 64 * KiB, "pwm2" }, 141 [FSL_IMX8MP_PWM1] = { 0x30660000, 64 * KiB, "pwm1" }, 142 [FSL_IMX8MP_AIPS2_CONFIGURATION] = { 0x305f0000, 64 * KiB, "aips2_configuration" }, 143 /* AIPS-2 End */ 144 145 /* AIPS-1 Begin */ 146 [FSL_IMX8MP_CSU] = { 0x303e0000, 64 * KiB, "csu" }, 147 [FSL_IMX8MP_RDC] = { 0x303d0000, 64 * KiB, "rdc" }, 148 [FSL_IMX8MP_SEMAPHORE2] = { 0x303c0000, 64 * KiB, "semaphore2" }, 149 [FSL_IMX8MP_SEMAPHORE1] = { 0x303b0000, 64 * KiB, "semaphore1" }, 150 [FSL_IMX8MP_GPC] = { 0x303a0000, 64 * KiB, "gpc" }, 151 [FSL_IMX8MP_SRC] = { 0x30390000, 64 * KiB, "src" }, 152 [FSL_IMX8MP_CCM] = { 0x30380000, 64 * KiB, "ccm" }, 153 [FSL_IMX8MP_SNVS_HP] = { 0x30370000, 64 * KiB, "snvs_hp" }, 154 [FSL_IMX8MP_ANA_PLL] = { 0x30360000, 64 * KiB, "ana_pll" }, 155 [FSL_IMX8MP_OCOTP_CTRL] = { 0x30350000, 64 * KiB, "ocotp_ctrl" }, 156 [FSL_IMX8MP_IOMUXC_GPR] = { 0x30340000, 64 * KiB, "iomuxc_gpr" }, 157 [FSL_IMX8MP_IOMUXC] = { 0x30330000, 64 * KiB, "iomuxc" }, 158 [FSL_IMX8MP_GPT3] = { 0x302f0000, 64 * KiB, "gpt3" }, 159 [FSL_IMX8MP_GPT2] = { 0x302e0000, 64 * KiB, "gpt2" }, 160 [FSL_IMX8MP_GPT1] = { 0x302d0000, 64 * KiB, "gpt1" }, 161 [FSL_IMX8MP_WDOG3] = { 0x302a0000, 64 * KiB, "wdog3" }, 162 [FSL_IMX8MP_WDOG2] = { 0x30290000, 64 * KiB, "wdog2" }, 163 [FSL_IMX8MP_WDOG1] = { 0x30280000, 64 * KiB, "wdog1" }, 164 [FSL_IMX8MP_ANA_OSC] = { 0x30270000, 64 * KiB, "ana_osc" }, 165 [FSL_IMX8MP_ANA_TSENSOR] = { 0x30260000, 64 * KiB, "ana_tsensor" }, 166 [FSL_IMX8MP_GPIO5] = { 0x30240000, 64 * KiB, "gpio5" }, 167 [FSL_IMX8MP_GPIO4] = { 0x30230000, 64 * KiB, "gpio4" }, 168 [FSL_IMX8MP_GPIO3] = { 0x30220000, 64 * KiB, "gpio3" }, 169 [FSL_IMX8MP_GPIO2] = { 0x30210000, 64 * KiB, "gpio2" }, 170 [FSL_IMX8MP_GPIO1] = { 0x30200000, 64 * KiB, "gpio1" }, 171 [FSL_IMX8MP_AIPS1_CONFIGURATION] = { 0x301f0000, 64 * KiB, "aips1_configuration" }, 172 /* AIPS-1 End */ 173 174 [FSL_IMX8MP_A53_DAP] = { 0x28000000, 16 * MiB, "a53_dap" }, 175 [FSL_IMX8MP_PCIE1_MEM] = { 0x18000000, 128 * MiB, "pcie1_mem" }, 176 [FSL_IMX8MP_QSPI_MEM] = { 0x08000000, 256 * MiB, "qspi_mem" }, 177 [FSL_IMX8MP_OCRAM] = { 0x00900000, 576 * KiB, "ocram" }, 178 [FSL_IMX8MP_TCM_DTCM] = { 0x00800000, 128 * KiB, "tcm_dtcm" }, 179 [FSL_IMX8MP_TCM_ITCM] = { 0x007e0000, 128 * KiB, "tcm_itcm" }, 180 [FSL_IMX8MP_OCRAM_S] = { 0x00180000, 36 * KiB, "ocram_s" }, 181 [FSL_IMX8MP_CAAM_MEM] = { 0x00100000, 32 * KiB, "caam_mem" }, 182 [FSL_IMX8MP_BOOT_ROM_PROTECTED] = { 0x0003f000, 4 * KiB, "boot_rom_protected" }, 183 [FSL_IMX8MP_BOOT_ROM] = { 0x00000000, 252 * KiB, "boot_rom" }, 184 }; 185 186 static void fsl_imx8mp_init(Object *obj) 187 { 188 MachineState *ms = MACHINE(qdev_get_machine()); 189 FslImx8mpState *s = FSL_IMX8MP(obj); 190 int i; 191 192 for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX8MP_NUM_CPUS); i++) { 193 g_autofree char *name = g_strdup_printf("cpu%d", i); 194 object_initialize_child(obj, name, &s->cpu[i], 195 ARM_CPU_TYPE_NAME("cortex-a53")); 196 } 197 198 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GICV3); 199 200 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX8MP_CCM); 201 202 object_initialize_child(obj, "analog", &s->analog, TYPE_IMX8MP_ANALOG); 203 204 object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); 205 206 for (i = 0; i < FSL_IMX8MP_NUM_UARTS; i++) { 207 g_autofree char *name = g_strdup_printf("uart%d", i + 1); 208 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); 209 } 210 211 for (i = 0; i < FSL_IMX8MP_NUM_I2CS; i++) { 212 g_autofree char *name = g_strdup_printf("i2c%d", i + 1); 213 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); 214 } 215 216 for (i = 0; i < FSL_IMX8MP_NUM_GPIOS; i++) { 217 g_autofree char *name = g_strdup_printf("gpio%d", i + 1); 218 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); 219 } 220 221 for (i = 0; i < FSL_IMX8MP_NUM_USDHCS; i++) { 222 g_autofree char *name = g_strdup_printf("usdhc%d", i + 1); 223 object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); 224 } 225 226 object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST); 227 object_initialize_child(obj, "pcie_phy", &s->pcie_phy, 228 TYPE_FSL_IMX8M_PCIE_PHY); 229 } 230 231 static void fsl_imx8mp_realize(DeviceState *dev, Error **errp) 232 { 233 MachineState *ms = MACHINE(qdev_get_machine()); 234 FslImx8mpState *s = FSL_IMX8MP(dev); 235 DeviceState *gicdev = DEVICE(&s->gic); 236 int i; 237 238 if (ms->smp.cpus > FSL_IMX8MP_NUM_CPUS) { 239 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", 240 TYPE_FSL_IMX8MP, FSL_IMX8MP_NUM_CPUS, ms->smp.cpus); 241 return; 242 } 243 244 /* CPUs */ 245 for (i = 0; i < ms->smp.cpus; i++) { 246 /* On uniprocessor, the CBAR is set to 0 */ 247 if (ms->smp.cpus > 1) { 248 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 249 fsl_imx8mp_memmap[FSL_IMX8MP_GIC_DIST].addr, 250 &error_abort); 251 } 252 253 /* 254 * CNTFID0 base frequency in Hz of system counter 255 */ 256 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 8000000, 257 &error_abort); 258 259 if (i) { 260 /* 261 * Secondary CPUs start in powered-down state (and can be 262 * powered up via the SRC system reset controller) 263 */ 264 object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-off", 265 true, &error_abort); 266 } 267 268 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 269 return; 270 } 271 } 272 273 /* GIC */ 274 { 275 SysBusDevice *gicsbd = SYS_BUS_DEVICE(&s->gic); 276 QList *redist_region_count; 277 278 qdev_prop_set_uint32(gicdev, "num-cpu", ms->smp.cpus); 279 qdev_prop_set_uint32(gicdev, "num-irq", 280 FSL_IMX8MP_NUM_IRQS + GIC_INTERNAL); 281 redist_region_count = qlist_new(); 282 qlist_append_int(redist_region_count, ms->smp.cpus); 283 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 284 object_property_set_link(OBJECT(&s->gic), "sysmem", 285 OBJECT(get_system_memory()), &error_fatal); 286 if (!sysbus_realize(gicsbd, errp)) { 287 return; 288 } 289 sysbus_mmio_map(gicsbd, 0, fsl_imx8mp_memmap[FSL_IMX8MP_GIC_DIST].addr); 290 sysbus_mmio_map(gicsbd, 1, fsl_imx8mp_memmap[FSL_IMX8MP_GIC_REDIST].addr); 291 292 /* 293 * Wire the outputs from each CPU's generic timer and the GICv3 294 * maintenance interrupt signal to the appropriate GIC PPI inputs, and 295 * the GIC's IRQ/FIQ interrupt outputs to the CPU's inputs. 296 */ 297 for (i = 0; i < ms->smp.cpus; i++) { 298 DeviceState *cpudev = DEVICE(&s->cpu[i]); 299 int intidbase = FSL_IMX8MP_NUM_IRQS + i * GIC_INTERNAL; 300 qemu_irq irq; 301 302 /* 303 * Mapping from the output timer irq lines from the CPU to the 304 * GIC PPI inputs. 305 */ 306 static const int timer_irqs[] = { 307 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 308 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 309 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 310 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 311 }; 312 313 for (int j = 0; j < ARRAY_SIZE(timer_irqs); j++) { 314 irq = qdev_get_gpio_in(gicdev, intidbase + timer_irqs[j]); 315 qdev_connect_gpio_out(cpudev, j, irq); 316 } 317 318 irq = qdev_get_gpio_in(gicdev, intidbase + ARCH_GIC_MAINT_IRQ); 319 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 320 0, irq); 321 322 irq = qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ); 323 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, irq); 324 325 sysbus_connect_irq(gicsbd, i, 326 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 327 sysbus_connect_irq(gicsbd, i + ms->smp.cpus, 328 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 329 } 330 } 331 332 /* CCM */ 333 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) { 334 return; 335 } 336 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, 337 fsl_imx8mp_memmap[FSL_IMX8MP_CCM].addr); 338 339 /* Analog */ 340 if (!sysbus_realize(SYS_BUS_DEVICE(&s->analog), errp)) { 341 return; 342 } 343 sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0, 344 fsl_imx8mp_memmap[FSL_IMX8MP_ANA_PLL].addr); 345 346 /* UARTs */ 347 for (i = 0; i < FSL_IMX8MP_NUM_UARTS; i++) { 348 struct { 349 hwaddr addr; 350 unsigned int irq; 351 } serial_table[FSL_IMX8MP_NUM_UARTS] = { 352 { fsl_imx8mp_memmap[FSL_IMX8MP_UART1].addr, FSL_IMX8MP_UART1_IRQ }, 353 { fsl_imx8mp_memmap[FSL_IMX8MP_UART2].addr, FSL_IMX8MP_UART2_IRQ }, 354 { fsl_imx8mp_memmap[FSL_IMX8MP_UART3].addr, FSL_IMX8MP_UART3_IRQ }, 355 { fsl_imx8mp_memmap[FSL_IMX8MP_UART4].addr, FSL_IMX8MP_UART4_IRQ }, 356 }; 357 358 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 359 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { 360 return; 361 } 362 363 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 364 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 365 qdev_get_gpio_in(gicdev, serial_table[i].irq)); 366 } 367 368 /* I2Cs */ 369 for (i = 0; i < FSL_IMX8MP_NUM_I2CS; i++) { 370 struct { 371 hwaddr addr; 372 unsigned int irq; 373 } i2c_table[FSL_IMX8MP_NUM_I2CS] = { 374 { fsl_imx8mp_memmap[FSL_IMX8MP_I2C1].addr, FSL_IMX8MP_I2C1_IRQ }, 375 { fsl_imx8mp_memmap[FSL_IMX8MP_I2C2].addr, FSL_IMX8MP_I2C2_IRQ }, 376 { fsl_imx8mp_memmap[FSL_IMX8MP_I2C3].addr, FSL_IMX8MP_I2C3_IRQ }, 377 { fsl_imx8mp_memmap[FSL_IMX8MP_I2C4].addr, FSL_IMX8MP_I2C4_IRQ }, 378 { fsl_imx8mp_memmap[FSL_IMX8MP_I2C5].addr, FSL_IMX8MP_I2C5_IRQ }, 379 { fsl_imx8mp_memmap[FSL_IMX8MP_I2C6].addr, FSL_IMX8MP_I2C6_IRQ }, 380 }; 381 382 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) { 383 return; 384 } 385 386 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 387 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 388 qdev_get_gpio_in(gicdev, i2c_table[i].irq)); 389 } 390 391 /* GPIOs */ 392 for (i = 0; i < FSL_IMX8MP_NUM_GPIOS; i++) { 393 struct { 394 hwaddr addr; 395 unsigned int irq_low; 396 unsigned int irq_high; 397 } gpio_table[FSL_IMX8MP_NUM_GPIOS] = { 398 { 399 fsl_imx8mp_memmap[FSL_IMX8MP_GPIO1].addr, 400 FSL_IMX8MP_GPIO1_LOW_IRQ, 401 FSL_IMX8MP_GPIO1_HIGH_IRQ 402 }, 403 { 404 fsl_imx8mp_memmap[FSL_IMX8MP_GPIO2].addr, 405 FSL_IMX8MP_GPIO2_LOW_IRQ, 406 FSL_IMX8MP_GPIO2_HIGH_IRQ 407 }, 408 { 409 fsl_imx8mp_memmap[FSL_IMX8MP_GPIO3].addr, 410 FSL_IMX8MP_GPIO3_LOW_IRQ, 411 FSL_IMX8MP_GPIO3_HIGH_IRQ 412 }, 413 { 414 fsl_imx8mp_memmap[FSL_IMX8MP_GPIO4].addr, 415 FSL_IMX8MP_GPIO4_LOW_IRQ, 416 FSL_IMX8MP_GPIO4_HIGH_IRQ 417 }, 418 { 419 fsl_imx8mp_memmap[FSL_IMX8MP_GPIO5].addr, 420 FSL_IMX8MP_GPIO5_LOW_IRQ, 421 FSL_IMX8MP_GPIO5_HIGH_IRQ 422 }, 423 }; 424 425 object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true, 426 &error_abort); 427 object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq", 428 true, &error_abort); 429 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) { 430 return; 431 } 432 433 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); 434 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 435 qdev_get_gpio_in(gicdev, gpio_table[i].irq_low)); 436 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, 437 qdev_get_gpio_in(gicdev, gpio_table[i].irq_high)); 438 } 439 440 /* USDHCs */ 441 for (i = 0; i < FSL_IMX8MP_NUM_USDHCS; i++) { 442 struct { 443 hwaddr addr; 444 unsigned int irq; 445 } usdhc_table[FSL_IMX8MP_NUM_USDHCS] = { 446 { fsl_imx8mp_memmap[FSL_IMX8MP_USDHC1].addr, FSL_IMX8MP_USDHC1_IRQ }, 447 { fsl_imx8mp_memmap[FSL_IMX8MP_USDHC2].addr, FSL_IMX8MP_USDHC2_IRQ }, 448 { fsl_imx8mp_memmap[FSL_IMX8MP_USDHC3].addr, FSL_IMX8MP_USDHC3_IRQ }, 449 }; 450 451 object_property_set_uint(OBJECT(&s->usdhc[i]), "vendor", 452 SDHCI_VENDOR_IMX, &error_abort); 453 if (!sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), errp)) { 454 return; 455 } 456 457 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, usdhc_table[i].addr); 458 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, 459 qdev_get_gpio_in(gicdev, usdhc_table[i].irq)); 460 } 461 462 /* SNVS */ 463 if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) { 464 return; 465 } 466 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, 467 fsl_imx8mp_memmap[FSL_IMX8MP_SNVS_HP].addr); 468 469 /* PCIe */ 470 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie), errp)) { 471 return; 472 } 473 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, 474 fsl_imx8mp_memmap[FSL_IMX8MP_PCIE1].addr); 475 476 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, 477 qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTA_IRQ)); 478 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, 479 qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTB_IRQ)); 480 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, 481 qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTC_IRQ)); 482 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, 483 qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTD_IRQ)); 484 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4, 485 qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_MSI_IRQ)); 486 487 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy), errp)) { 488 return; 489 } 490 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie_phy), 0, 491 fsl_imx8mp_memmap[FSL_IMX8MP_PCIE_PHY1].addr); 492 493 /* Unimplemented devices */ 494 for (i = 0; i < ARRAY_SIZE(fsl_imx8mp_memmap); i++) { 495 switch (i) { 496 case FSL_IMX8MP_ANA_PLL: 497 case FSL_IMX8MP_CCM: 498 case FSL_IMX8MP_GIC_DIST: 499 case FSL_IMX8MP_GIC_REDIST: 500 case FSL_IMX8MP_GPIO1 ... FSL_IMX8MP_GPIO5: 501 case FSL_IMX8MP_I2C1 ... FSL_IMX8MP_I2C6: 502 case FSL_IMX8MP_PCIE1: 503 case FSL_IMX8MP_PCIE_PHY1: 504 case FSL_IMX8MP_RAM: 505 case FSL_IMX8MP_SNVS_HP: 506 case FSL_IMX8MP_UART1 ... FSL_IMX8MP_UART4: 507 case FSL_IMX8MP_USDHC1 ... FSL_IMX8MP_USDHC3: 508 /* device implemented and treated above */ 509 break; 510 511 default: 512 create_unimplemented_device(fsl_imx8mp_memmap[i].name, 513 fsl_imx8mp_memmap[i].addr, 514 fsl_imx8mp_memmap[i].size); 515 break; 516 } 517 } 518 } 519 520 static void fsl_imx8mp_class_init(ObjectClass *oc, void *data) 521 { 522 DeviceClass *dc = DEVICE_CLASS(oc); 523 524 dc->realize = fsl_imx8mp_realize; 525 526 dc->desc = "i.MX 8M Plus SoC"; 527 } 528 529 static const TypeInfo fsl_imx8mp_types[] = { 530 { 531 .name = TYPE_FSL_IMX8MP, 532 .parent = TYPE_DEVICE, 533 .instance_size = sizeof(FslImx8mpState), 534 .instance_init = fsl_imx8mp_init, 535 .class_init = fsl_imx8mp_class_init, 536 }, 537 }; 538 539 DEFINE_TYPES(fsl_imx8mp_types) 540