1 /* 2 * Copyright (c) 2018, Impinj, Inc. 3 * 4 * i.MX7 SoC definitions 5 * 6 * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 7 * 8 * Based on hw/arm/fsl-imx6.c 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "hw/arm/fsl-imx7.h" 24 #include "hw/misc/unimp.h" 25 #include "hw/boards.h" 26 #include "sysemu/sysemu.h" 27 #include "qemu/error-report.h" 28 #include "qemu/module.h" 29 #include "target/arm/cpu-qom.h" 30 31 #define NAME_SIZE 20 32 33 static void fsl_imx7_init(Object *obj) 34 { 35 MachineState *ms = MACHINE(qdev_get_machine()); 36 FslIMX7State *s = FSL_IMX7(obj); 37 char name[NAME_SIZE]; 38 int i; 39 40 /* 41 * CPUs 42 */ 43 for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) { 44 snprintf(name, NAME_SIZE, "cpu%d", i); 45 object_initialize_child(obj, name, &s->cpu[i], 46 ARM_CPU_TYPE_NAME("cortex-a7")); 47 } 48 49 /* 50 * A7MPCORE 51 */ 52 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, 53 TYPE_A15MPCORE_PRIV); 54 55 /* 56 * GPIOs 57 */ 58 for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) { 59 snprintf(name, NAME_SIZE, "gpio%d", i); 60 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); 61 } 62 63 /* 64 * GPTs 65 */ 66 for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) { 67 snprintf(name, NAME_SIZE, "gpt%d", i); 68 object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT); 69 } 70 71 /* 72 * CCM 73 */ 74 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX7_CCM); 75 76 /* 77 * Analog 78 */ 79 object_initialize_child(obj, "analog", &s->analog, TYPE_IMX7_ANALOG); 80 81 /* 82 * GPCv2 83 */ 84 object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2); 85 86 /* 87 * SRC 88 */ 89 object_initialize_child(obj, "src", &s->src, TYPE_IMX7_SRC); 90 91 /* 92 * ECSPIs 93 */ 94 for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) { 95 snprintf(name, NAME_SIZE, "spi%d", i + 1); 96 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); 97 } 98 99 /* 100 * I2Cs 101 */ 102 for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) { 103 snprintf(name, NAME_SIZE, "i2c%d", i + 1); 104 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); 105 } 106 107 /* 108 * UARTs 109 */ 110 for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) { 111 snprintf(name, NAME_SIZE, "uart%d", i); 112 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); 113 } 114 115 /* 116 * Ethernets 117 */ 118 for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) { 119 snprintf(name, NAME_SIZE, "eth%d", i); 120 object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET); 121 } 122 123 /* 124 * SDHCIs 125 */ 126 for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) { 127 snprintf(name, NAME_SIZE, "usdhc%d", i); 128 object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); 129 } 130 131 /* 132 * SNVS 133 */ 134 object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); 135 136 /* 137 * Watchdogs 138 */ 139 for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) { 140 snprintf(name, NAME_SIZE, "wdt%d", i); 141 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT); 142 } 143 144 /* 145 * GPR 146 */ 147 object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR); 148 149 /* 150 * PCIE 151 */ 152 object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST); 153 154 /* 155 * USBs 156 */ 157 for (i = 0; i < FSL_IMX7_NUM_USBS; i++) { 158 snprintf(name, NAME_SIZE, "usb%d", i); 159 object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); 160 } 161 } 162 163 static void fsl_imx7_realize(DeviceState *dev, Error **errp) 164 { 165 MachineState *ms = MACHINE(qdev_get_machine()); 166 FslIMX7State *s = FSL_IMX7(dev); 167 Object *o; 168 int i; 169 qemu_irq irq; 170 char name[NAME_SIZE]; 171 unsigned int smp_cpus = ms->smp.cpus; 172 173 if (smp_cpus > FSL_IMX7_NUM_CPUS) { 174 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", 175 TYPE_FSL_IMX7, FSL_IMX7_NUM_CPUS, smp_cpus); 176 return; 177 } 178 179 /* 180 * CPUs 181 */ 182 for (i = 0; i < smp_cpus; i++) { 183 o = OBJECT(&s->cpu[i]); 184 185 /* On uniprocessor, the CBAR is set to 0 */ 186 if (smp_cpus > 1) { 187 object_property_set_int(o, "reset-cbar", FSL_IMX7_A7MPCORE_ADDR, 188 &error_abort); 189 } 190 191 if (i) { 192 /* 193 * Secondary CPUs start in powered-down state (and can be 194 * powered up via the SRC system reset controller) 195 */ 196 object_property_set_bool(o, "start-powered-off", true, 197 &error_abort); 198 } 199 200 qdev_realize(DEVICE(o), NULL, &error_abort); 201 } 202 203 /* 204 * A7MPCORE 205 */ 206 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", smp_cpus, 207 &error_abort); 208 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", 209 FSL_IMX7_MAX_IRQ + GIC_INTERNAL, &error_abort); 210 211 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 212 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR); 213 214 for (i = 0; i < smp_cpus; i++) { 215 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 216 DeviceState *d = DEVICE(qemu_get_cpu(i)); 217 218 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 219 sysbus_connect_irq(sbd, i, irq); 220 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 221 sysbus_connect_irq(sbd, i + smp_cpus, irq); 222 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 223 sysbus_connect_irq(sbd, i + 2 * smp_cpus, irq); 224 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 225 sysbus_connect_irq(sbd, i + 3 * smp_cpus, irq); 226 } 227 228 /* 229 * A7MPCORE DAP 230 */ 231 create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR, 232 FSL_IMX7_A7MPCORE_DAP_SIZE); 233 234 /* 235 * GPTs 236 */ 237 for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) { 238 static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = { 239 FSL_IMX7_GPT1_ADDR, 240 FSL_IMX7_GPT2_ADDR, 241 FSL_IMX7_GPT3_ADDR, 242 FSL_IMX7_GPT4_ADDR, 243 }; 244 245 static const int FSL_IMX7_GPTn_IRQ[FSL_IMX7_NUM_GPTS] = { 246 FSL_IMX7_GPT1_IRQ, 247 FSL_IMX7_GPT2_IRQ, 248 FSL_IMX7_GPT3_IRQ, 249 FSL_IMX7_GPT4_IRQ, 250 }; 251 252 s->gpt[i].ccm = IMX_CCM(&s->ccm); 253 sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort); 254 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]); 255 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, 256 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 257 FSL_IMX7_GPTn_IRQ[i])); 258 } 259 260 /* 261 * GPIOs 262 */ 263 for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) { 264 static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = { 265 FSL_IMX7_GPIO1_ADDR, 266 FSL_IMX7_GPIO2_ADDR, 267 FSL_IMX7_GPIO3_ADDR, 268 FSL_IMX7_GPIO4_ADDR, 269 FSL_IMX7_GPIO5_ADDR, 270 FSL_IMX7_GPIO6_ADDR, 271 FSL_IMX7_GPIO7_ADDR, 272 }; 273 274 static const int FSL_IMX7_GPIOn_LOW_IRQ[FSL_IMX7_NUM_GPIOS] = { 275 FSL_IMX7_GPIO1_LOW_IRQ, 276 FSL_IMX7_GPIO2_LOW_IRQ, 277 FSL_IMX7_GPIO3_LOW_IRQ, 278 FSL_IMX7_GPIO4_LOW_IRQ, 279 FSL_IMX7_GPIO5_LOW_IRQ, 280 FSL_IMX7_GPIO6_LOW_IRQ, 281 FSL_IMX7_GPIO7_LOW_IRQ, 282 }; 283 284 static const int FSL_IMX7_GPIOn_HIGH_IRQ[FSL_IMX7_NUM_GPIOS] = { 285 FSL_IMX7_GPIO1_HIGH_IRQ, 286 FSL_IMX7_GPIO2_HIGH_IRQ, 287 FSL_IMX7_GPIO3_HIGH_IRQ, 288 FSL_IMX7_GPIO4_HIGH_IRQ, 289 FSL_IMX7_GPIO5_HIGH_IRQ, 290 FSL_IMX7_GPIO6_HIGH_IRQ, 291 FSL_IMX7_GPIO7_HIGH_IRQ, 292 }; 293 294 sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort); 295 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, 296 FSL_IMX7_GPIOn_ADDR[i]); 297 298 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 299 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 300 FSL_IMX7_GPIOn_LOW_IRQ[i])); 301 302 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, 303 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 304 FSL_IMX7_GPIOn_HIGH_IRQ[i])); 305 } 306 307 /* 308 * IOMUXC and IOMUXC_LPSR 309 */ 310 create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR, 311 FSL_IMX7_IOMUXC_SIZE); 312 create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR, 313 FSL_IMX7_IOMUXC_LPSR_SIZE); 314 315 /* 316 * CCM 317 */ 318 sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_abort); 319 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX7_CCM_ADDR); 320 321 /* 322 * Analog 323 */ 324 sysbus_realize(SYS_BUS_DEVICE(&s->analog), &error_abort); 325 sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0, FSL_IMX7_ANALOG_ADDR); 326 327 /* 328 * GPCv2 329 */ 330 sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort); 331 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR); 332 333 /* 334 * ECSPIs 335 */ 336 for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) { 337 static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = { 338 FSL_IMX7_ECSPI1_ADDR, 339 FSL_IMX7_ECSPI2_ADDR, 340 FSL_IMX7_ECSPI3_ADDR, 341 FSL_IMX7_ECSPI4_ADDR, 342 }; 343 344 static const int FSL_IMX7_SPIn_IRQ[FSL_IMX7_NUM_ECSPIS] = { 345 FSL_IMX7_ECSPI1_IRQ, 346 FSL_IMX7_ECSPI2_IRQ, 347 FSL_IMX7_ECSPI3_IRQ, 348 FSL_IMX7_ECSPI4_IRQ, 349 }; 350 351 /* Initialize the SPI */ 352 sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &error_abort); 353 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 354 FSL_IMX7_SPIn_ADDR[i]); 355 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 356 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 357 FSL_IMX7_SPIn_IRQ[i])); 358 } 359 360 /* 361 * I2Cs 362 */ 363 for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) { 364 static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = { 365 FSL_IMX7_I2C1_ADDR, 366 FSL_IMX7_I2C2_ADDR, 367 FSL_IMX7_I2C3_ADDR, 368 FSL_IMX7_I2C4_ADDR, 369 }; 370 371 static const int FSL_IMX7_I2Cn_IRQ[FSL_IMX7_NUM_I2CS] = { 372 FSL_IMX7_I2C1_IRQ, 373 FSL_IMX7_I2C2_IRQ, 374 FSL_IMX7_I2C3_IRQ, 375 FSL_IMX7_I2C4_IRQ, 376 }; 377 378 sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_abort); 379 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]); 380 381 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 382 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 383 FSL_IMX7_I2Cn_IRQ[i])); 384 } 385 386 /* 387 * UARTs 388 */ 389 for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) { 390 static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = { 391 FSL_IMX7_UART1_ADDR, 392 FSL_IMX7_UART2_ADDR, 393 FSL_IMX7_UART3_ADDR, 394 FSL_IMX7_UART4_ADDR, 395 FSL_IMX7_UART5_ADDR, 396 FSL_IMX7_UART6_ADDR, 397 FSL_IMX7_UART7_ADDR, 398 }; 399 400 static const int FSL_IMX7_UARTn_IRQ[FSL_IMX7_NUM_UARTS] = { 401 FSL_IMX7_UART1_IRQ, 402 FSL_IMX7_UART2_IRQ, 403 FSL_IMX7_UART3_IRQ, 404 FSL_IMX7_UART4_IRQ, 405 FSL_IMX7_UART5_IRQ, 406 FSL_IMX7_UART6_IRQ, 407 FSL_IMX7_UART7_IRQ, 408 }; 409 410 411 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 412 413 sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &error_abort); 414 415 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]); 416 417 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_UARTn_IRQ[i]); 418 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq); 419 } 420 421 /* 422 * Ethernets 423 * 424 * We must use two loops since phy_connected affects the other interface 425 * and we have to set all properties before calling sysbus_realize(). 426 */ 427 for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) { 428 object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected", 429 s->phy_connected[i], &error_abort); 430 /* 431 * If the MDIO bus on this controller is not connected, assume the 432 * other controller provides support for it. 433 */ 434 if (!s->phy_connected[i]) { 435 object_property_set_link(OBJECT(&s->eth[1 - i]), "phy-consumer", 436 OBJECT(&s->eth[i]), &error_abort); 437 } 438 } 439 440 for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) { 441 static const hwaddr FSL_IMX7_ENETn_ADDR[FSL_IMX7_NUM_ETHS] = { 442 FSL_IMX7_ENET1_ADDR, 443 FSL_IMX7_ENET2_ADDR, 444 }; 445 446 object_property_set_uint(OBJECT(&s->eth[i]), "phy-num", 447 s->phy_num[i], &error_abort); 448 object_property_set_uint(OBJECT(&s->eth[i]), "tx-ring-num", 449 FSL_IMX7_ETH_NUM_TX_RINGS, &error_abort); 450 qemu_configure_nic_device(DEVICE(&s->eth[i]), true, NULL); 451 sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort); 452 453 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]); 454 455 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 0)); 456 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq); 457 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 3)); 458 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq); 459 } 460 461 /* 462 * USDHCs 463 */ 464 for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) { 465 static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = { 466 FSL_IMX7_USDHC1_ADDR, 467 FSL_IMX7_USDHC2_ADDR, 468 FSL_IMX7_USDHC3_ADDR, 469 }; 470 471 static const int FSL_IMX7_USDHCn_IRQ[FSL_IMX7_NUM_USDHCS] = { 472 FSL_IMX7_USDHC1_IRQ, 473 FSL_IMX7_USDHC2_IRQ, 474 FSL_IMX7_USDHC3_IRQ, 475 }; 476 477 object_property_set_uint(OBJECT(&s->usdhc[i]), "vendor", 478 SDHCI_VENDOR_IMX, &error_abort); 479 sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort); 480 481 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, 482 FSL_IMX7_USDHCn_ADDR[i]); 483 484 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USDHCn_IRQ[i]); 485 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq); 486 } 487 488 /* 489 * SNVS 490 */ 491 sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort); 492 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR); 493 494 /* 495 * SRC 496 */ 497 sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort); 498 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX7_SRC_ADDR); 499 500 /* 501 * Watchdogs 502 */ 503 for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) { 504 static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = { 505 FSL_IMX7_WDOG1_ADDR, 506 FSL_IMX7_WDOG2_ADDR, 507 FSL_IMX7_WDOG3_ADDR, 508 FSL_IMX7_WDOG4_ADDR, 509 }; 510 static const int FSL_IMX7_WDOGn_IRQ[FSL_IMX7_NUM_WDTS] = { 511 FSL_IMX7_WDOG1_IRQ, 512 FSL_IMX7_WDOG2_IRQ, 513 FSL_IMX7_WDOG3_IRQ, 514 FSL_IMX7_WDOG4_IRQ, 515 }; 516 517 object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", 518 true, &error_abort); 519 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); 520 521 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]); 522 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, 523 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 524 FSL_IMX7_WDOGn_IRQ[i])); 525 } 526 527 /* 528 * SDMA 529 */ 530 create_unimplemented_device("sdma", FSL_IMX7_SDMA_ADDR, FSL_IMX7_SDMA_SIZE); 531 532 /* 533 * CAAM 534 */ 535 create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE); 536 537 /* 538 * PWMs 539 */ 540 for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) { 541 static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = { 542 FSL_IMX7_PWM1_ADDR, 543 FSL_IMX7_PWM2_ADDR, 544 FSL_IMX7_PWM3_ADDR, 545 FSL_IMX7_PWM4_ADDR, 546 }; 547 548 snprintf(name, NAME_SIZE, "pwm%d", i); 549 create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i], 550 FSL_IMX7_PWMn_SIZE); 551 } 552 553 /* 554 * CANs 555 */ 556 for (i = 0; i < FSL_IMX7_NUM_CANS; i++) { 557 static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = { 558 FSL_IMX7_CAN1_ADDR, 559 FSL_IMX7_CAN2_ADDR, 560 }; 561 562 snprintf(name, NAME_SIZE, "can%d", i); 563 create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i], 564 FSL_IMX7_CANn_SIZE); 565 } 566 567 /* 568 * SAIs (Audio SSI (Synchronous Serial Interface)) 569 */ 570 for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) { 571 static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = { 572 FSL_IMX7_SAI1_ADDR, 573 FSL_IMX7_SAI2_ADDR, 574 FSL_IMX7_SAI3_ADDR, 575 }; 576 577 snprintf(name, NAME_SIZE, "sai%d", i); 578 create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i], 579 FSL_IMX7_SAIn_SIZE); 580 } 581 582 /* 583 * OCOTP 584 */ 585 create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR, 586 FSL_IMX7_OCOTP_SIZE); 587 588 /* 589 * GPR 590 */ 591 sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort); 592 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR); 593 594 /* 595 * PCIE 596 */ 597 sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort); 598 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR); 599 600 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ); 601 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq); 602 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTB_IRQ); 603 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq); 604 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTC_IRQ); 605 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq); 606 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ); 607 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); 608 609 /* 610 * USBs 611 */ 612 for (i = 0; i < FSL_IMX7_NUM_USBS; i++) { 613 static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = { 614 FSL_IMX7_USBMISC1_ADDR, 615 FSL_IMX7_USBMISC2_ADDR, 616 FSL_IMX7_USBMISC3_ADDR, 617 }; 618 619 static const hwaddr FSL_IMX7_USBn_ADDR[FSL_IMX7_NUM_USBS] = { 620 FSL_IMX7_USB1_ADDR, 621 FSL_IMX7_USB2_ADDR, 622 FSL_IMX7_USB3_ADDR, 623 }; 624 625 static const int FSL_IMX7_USBn_IRQ[FSL_IMX7_NUM_USBS] = { 626 FSL_IMX7_USB1_IRQ, 627 FSL_IMX7_USB2_IRQ, 628 FSL_IMX7_USB3_IRQ, 629 }; 630 631 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); 632 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, 633 FSL_IMX7_USBn_ADDR[i]); 634 635 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USBn_IRQ[i]); 636 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, irq); 637 638 snprintf(name, NAME_SIZE, "usbmisc%d", i); 639 create_unimplemented_device(name, FSL_IMX7_USBMISCn_ADDR[i], 640 FSL_IMX7_USBMISCn_SIZE); 641 } 642 643 /* 644 * ADCs 645 */ 646 for (i = 0; i < FSL_IMX7_NUM_ADCS; i++) { 647 static const hwaddr FSL_IMX7_ADCn_ADDR[FSL_IMX7_NUM_ADCS] = { 648 FSL_IMX7_ADC1_ADDR, 649 FSL_IMX7_ADC2_ADDR, 650 }; 651 652 snprintf(name, NAME_SIZE, "adc%d", i); 653 create_unimplemented_device(name, FSL_IMX7_ADCn_ADDR[i], 654 FSL_IMX7_ADCn_SIZE); 655 } 656 657 /* 658 * LCD 659 */ 660 create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR, 661 FSL_IMX7_LCDIF_SIZE); 662 663 /* 664 * DMA APBH 665 */ 666 create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR, 667 FSL_IMX7_DMA_APBH_SIZE); 668 /* 669 * PCIe PHY 670 */ 671 create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR, 672 FSL_IMX7_PCIE_PHY_SIZE); 673 674 /* 675 * CSU 676 */ 677 create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR, 678 FSL_IMX7_CSU_SIZE); 679 680 /* 681 * TZASC 682 */ 683 create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR, 684 FSL_IMX7_TZASC_SIZE); 685 686 /* 687 * OCRAM memory 688 */ 689 memory_region_init_ram(&s->ocram, NULL, "imx7.ocram", 690 FSL_IMX7_OCRAM_MEM_SIZE, 691 &error_abort); 692 memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR, 693 &s->ocram); 694 695 /* 696 * OCRAM EPDC memory 697 */ 698 memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc", 699 FSL_IMX7_OCRAM_EPDC_SIZE, 700 &error_abort); 701 memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR, 702 &s->ocram_epdc); 703 704 /* 705 * OCRAM PXP memory 706 */ 707 memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp", 708 FSL_IMX7_OCRAM_PXP_SIZE, 709 &error_abort); 710 memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR, 711 &s->ocram_pxp); 712 713 /* 714 * OCRAM_S memory 715 */ 716 memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s", 717 FSL_IMX7_OCRAM_S_SIZE, 718 &error_abort); 719 memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR, 720 &s->ocram_s); 721 722 /* 723 * ROM memory 724 */ 725 memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom", 726 FSL_IMX7_ROM_SIZE, &error_abort); 727 memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR, 728 &s->rom); 729 730 /* 731 * CAAM memory 732 */ 733 memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam", 734 FSL_IMX7_CAAM_MEM_SIZE, &error_abort); 735 memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR, 736 &s->caam); 737 } 738 739 static Property fsl_imx7_properties[] = { 740 DEFINE_PROP_UINT32("fec1-phy-num", FslIMX7State, phy_num[0], 0), 741 DEFINE_PROP_UINT32("fec2-phy-num", FslIMX7State, phy_num[1], 1), 742 DEFINE_PROP_BOOL("fec1-phy-connected", FslIMX7State, phy_connected[0], 743 true), 744 DEFINE_PROP_BOOL("fec2-phy-connected", FslIMX7State, phy_connected[1], 745 true), 746 DEFINE_PROP_END_OF_LIST(), 747 }; 748 749 static void fsl_imx7_class_init(ObjectClass *oc, void *data) 750 { 751 DeviceClass *dc = DEVICE_CLASS(oc); 752 753 device_class_set_props(dc, fsl_imx7_properties); 754 dc->realize = fsl_imx7_realize; 755 756 /* Reason: Uses serial_hds and nd_table in realize() directly */ 757 dc->user_creatable = false; 758 dc->desc = "i.MX7 SOC"; 759 } 760 761 static const TypeInfo fsl_imx7_type_info = { 762 .name = TYPE_FSL_IMX7, 763 .parent = TYPE_DEVICE, 764 .instance_size = sizeof(FslIMX7State), 765 .instance_init = fsl_imx7_init, 766 .class_init = fsl_imx7_class_init, 767 }; 768 769 static void fsl_imx7_register_types(void) 770 { 771 type_register_static(&fsl_imx7_type_info); 772 } 773 type_init(fsl_imx7_register_types) 774