1 /* 2 * Copyright (c) 2018, Impinj, Inc. 3 * 4 * i.MX7 SoC definitions 5 * 6 * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 7 * 8 * Based on hw/arm/fsl-imx6.c 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu-common.h" 24 #include "hw/arm/fsl-imx7.h" 25 #include "hw/misc/unimp.h" 26 #include "sysemu/sysemu.h" 27 #include "qemu/error-report.h" 28 29 #define NAME_SIZE 20 30 31 static void fsl_imx7_init(Object *obj) 32 { 33 BusState *sysbus = sysbus_get_default(); 34 FslIMX7State *s = FSL_IMX7(obj); 35 char name[NAME_SIZE]; 36 int i; 37 38 if (smp_cpus > FSL_IMX7_NUM_CPUS) { 39 error_report("%s: Only %d CPUs are supported (%d requested)", 40 TYPE_FSL_IMX7, FSL_IMX7_NUM_CPUS, smp_cpus); 41 exit(1); 42 } 43 44 for (i = 0; i < smp_cpus; i++) { 45 object_initialize(&s->cpu[i], sizeof(s->cpu[i]), 46 ARM_CPU_TYPE_NAME("cortex-a7")); 47 snprintf(name, NAME_SIZE, "cpu%d", i); 48 object_property_add_child(obj, name, OBJECT(&s->cpu[i]), 49 &error_fatal); 50 } 51 52 /* 53 * A7MPCORE 54 */ 55 object_initialize(&s->a7mpcore, sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV); 56 qdev_set_parent_bus(DEVICE(&s->a7mpcore), sysbus); 57 object_property_add_child(obj, "a7mpcore", 58 OBJECT(&s->a7mpcore), &error_fatal); 59 60 /* 61 * GPIOs 1 to 7 62 */ 63 for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) { 64 object_initialize(&s->gpio[i], sizeof(s->gpio[i]), 65 TYPE_IMX_GPIO); 66 qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus); 67 snprintf(name, NAME_SIZE, "gpio%d", i); 68 object_property_add_child(obj, name, 69 OBJECT(&s->gpio[i]), &error_fatal); 70 } 71 72 /* 73 * GPT1, 2, 3, 4 74 */ 75 for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) { 76 object_initialize(&s->gpt[i], sizeof(s->gpt[i]), TYPE_IMX7_GPT); 77 qdev_set_parent_bus(DEVICE(&s->gpt[i]), sysbus); 78 snprintf(name, NAME_SIZE, "gpt%d", i); 79 object_property_add_child(obj, name, OBJECT(&s->gpt[i]), 80 &error_fatal); 81 } 82 83 /* 84 * CCM 85 */ 86 object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX7_CCM); 87 qdev_set_parent_bus(DEVICE(&s->ccm), sysbus); 88 object_property_add_child(obj, "ccm", OBJECT(&s->ccm), &error_fatal); 89 90 /* 91 * Analog 92 */ 93 object_initialize(&s->analog, sizeof(s->analog), TYPE_IMX7_ANALOG); 94 qdev_set_parent_bus(DEVICE(&s->analog), sysbus); 95 object_property_add_child(obj, "analog", OBJECT(&s->analog), &error_fatal); 96 97 /* 98 * GPCv2 99 */ 100 object_initialize(&s->gpcv2, sizeof(s->gpcv2), TYPE_IMX_GPCV2); 101 qdev_set_parent_bus(DEVICE(&s->gpcv2), sysbus); 102 object_property_add_child(obj, "gpcv2", OBJECT(&s->gpcv2), &error_fatal); 103 104 for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) { 105 object_initialize(&s->spi[i], sizeof(s->spi[i]), TYPE_IMX_SPI); 106 qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); 107 snprintf(name, NAME_SIZE, "spi%d", i + 1); 108 object_property_add_child(obj, name, OBJECT(&s->spi[i]), NULL); 109 } 110 111 112 for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) { 113 object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C); 114 qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default()); 115 snprintf(name, NAME_SIZE, "i2c%d", i + 1); 116 object_property_add_child(obj, name, OBJECT(&s->i2c[i]), NULL); 117 } 118 119 /* 120 * UART 121 */ 122 for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) { 123 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL); 124 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus); 125 snprintf(name, NAME_SIZE, "uart%d", i); 126 object_property_add_child(obj, name, OBJECT(&s->uart[i]), 127 &error_fatal); 128 } 129 130 /* 131 * Ethernet 132 */ 133 for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) { 134 object_initialize(&s->eth[i], sizeof(s->eth[i]), TYPE_IMX_ENET); 135 qdev_set_parent_bus(DEVICE(&s->eth[i]), sysbus); 136 snprintf(name, NAME_SIZE, "eth%d", i); 137 object_property_add_child(obj, name, OBJECT(&s->eth[i]), 138 &error_fatal); 139 } 140 141 /* 142 * SDHCI 143 */ 144 for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) { 145 object_initialize(&s->usdhc[i], sizeof(s->usdhc[i]), 146 TYPE_IMX_USDHC); 147 qdev_set_parent_bus(DEVICE(&s->usdhc[i]), sysbus); 148 snprintf(name, NAME_SIZE, "usdhc%d", i); 149 object_property_add_child(obj, name, OBJECT(&s->usdhc[i]), 150 &error_fatal); 151 } 152 153 /* 154 * SNVS 155 */ 156 object_initialize(&s->snvs, sizeof(s->snvs), TYPE_IMX7_SNVS); 157 qdev_set_parent_bus(DEVICE(&s->snvs), sysbus); 158 object_property_add_child(obj, "snvs", OBJECT(&s->snvs), &error_fatal); 159 160 /* 161 * Watchdog 162 */ 163 for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) { 164 object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_IMX2_WDT); 165 qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus); 166 snprintf(name, NAME_SIZE, "wdt%d", i); 167 object_property_add_child(obj, name, OBJECT(&s->wdt[i]), 168 &error_fatal); 169 } 170 171 /* 172 * GPR 173 */ 174 object_initialize(&s->gpr, sizeof(s->gpr), TYPE_IMX7_GPR); 175 qdev_set_parent_bus(DEVICE(&s->gpr), sysbus); 176 object_property_add_child(obj, "gpr", OBJECT(&s->gpr), &error_fatal); 177 178 object_initialize(&s->pcie, sizeof(s->pcie), TYPE_DESIGNWARE_PCIE_HOST); 179 qdev_set_parent_bus(DEVICE(&s->pcie), sysbus); 180 object_property_add_child(obj, "pcie", OBJECT(&s->pcie), &error_fatal); 181 182 for (i = 0; i < FSL_IMX7_NUM_USBS; i++) { 183 object_initialize(&s->usb[i], 184 sizeof(s->usb[i]), TYPE_CHIPIDEA); 185 qdev_set_parent_bus(DEVICE(&s->usb[i]), sysbus); 186 snprintf(name, NAME_SIZE, "usb%d", i); 187 object_property_add_child(obj, name, 188 OBJECT(&s->usb[i]), &error_fatal); 189 } 190 } 191 192 static void fsl_imx7_realize(DeviceState *dev, Error **errp) 193 { 194 FslIMX7State *s = FSL_IMX7(dev); 195 Object *o; 196 int i; 197 qemu_irq irq; 198 char name[NAME_SIZE]; 199 200 for (i = 0; i < smp_cpus; i++) { 201 o = OBJECT(&s->cpu[i]); 202 203 object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC, 204 "psci-conduit", &error_abort); 205 206 /* On uniprocessor, the CBAR is set to 0 */ 207 if (smp_cpus > 1) { 208 object_property_set_int(o, FSL_IMX7_A7MPCORE_ADDR, 209 "reset-cbar", &error_abort); 210 } 211 212 if (i) { 213 /* Secondary CPUs start in PSCI powered-down state */ 214 object_property_set_bool(o, true, 215 "start-powered-off", &error_abort); 216 } 217 218 object_property_set_bool(o, true, "realized", &error_abort); 219 } 220 221 /* 222 * A7MPCORE 223 */ 224 object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu", 225 &error_abort); 226 object_property_set_int(OBJECT(&s->a7mpcore), 227 FSL_IMX7_MAX_IRQ + GIC_INTERNAL, 228 "num-irq", &error_abort); 229 230 object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized", 231 &error_abort); 232 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR); 233 234 for (i = 0; i < smp_cpus; i++) { 235 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 236 DeviceState *d = DEVICE(qemu_get_cpu(i)); 237 238 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 239 sysbus_connect_irq(sbd, i, irq); 240 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 241 sysbus_connect_irq(sbd, i + smp_cpus, irq); 242 } 243 244 /* 245 * A7MPCORE DAP 246 */ 247 create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR, 248 0x100000); 249 250 /* 251 * GPT1, 2, 3, 4 252 */ 253 for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) { 254 static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = { 255 FSL_IMX7_GPT1_ADDR, 256 FSL_IMX7_GPT2_ADDR, 257 FSL_IMX7_GPT3_ADDR, 258 FSL_IMX7_GPT4_ADDR, 259 }; 260 261 s->gpt[i].ccm = IMX_CCM(&s->ccm); 262 object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", 263 &error_abort); 264 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]); 265 } 266 267 for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) { 268 static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = { 269 FSL_IMX7_GPIO1_ADDR, 270 FSL_IMX7_GPIO2_ADDR, 271 FSL_IMX7_GPIO3_ADDR, 272 FSL_IMX7_GPIO4_ADDR, 273 FSL_IMX7_GPIO5_ADDR, 274 FSL_IMX7_GPIO6_ADDR, 275 FSL_IMX7_GPIO7_ADDR, 276 }; 277 278 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", 279 &error_abort); 280 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, FSL_IMX7_GPIOn_ADDR[i]); 281 } 282 283 /* 284 * IOMUXC and IOMUXC_LPSR 285 */ 286 for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) { 287 static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = { 288 FSL_IMX7_IOMUXC_ADDR, 289 FSL_IMX7_IOMUXC_LPSR_ADDR, 290 }; 291 292 snprintf(name, NAME_SIZE, "iomuxc%d", i); 293 create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i], 294 FSL_IMX7_IOMUXCn_SIZE); 295 } 296 297 /* 298 * CCM 299 */ 300 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &error_abort); 301 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX7_CCM_ADDR); 302 303 /* 304 * Analog 305 */ 306 object_property_set_bool(OBJECT(&s->analog), true, "realized", 307 &error_abort); 308 sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0, FSL_IMX7_ANALOG_ADDR); 309 310 /* 311 * GPCv2 312 */ 313 object_property_set_bool(OBJECT(&s->gpcv2), true, 314 "realized", &error_abort); 315 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR); 316 317 /* Initialize all ECSPI */ 318 for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) { 319 static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = { 320 FSL_IMX7_ECSPI1_ADDR, 321 FSL_IMX7_ECSPI2_ADDR, 322 FSL_IMX7_ECSPI3_ADDR, 323 FSL_IMX7_ECSPI4_ADDR, 324 }; 325 326 static const hwaddr FSL_IMX7_SPIn_IRQ[FSL_IMX7_NUM_ECSPIS] = { 327 FSL_IMX7_ECSPI1_IRQ, 328 FSL_IMX7_ECSPI2_IRQ, 329 FSL_IMX7_ECSPI3_IRQ, 330 FSL_IMX7_ECSPI4_IRQ, 331 }; 332 333 /* Initialize the SPI */ 334 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", 335 &error_abort); 336 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 337 FSL_IMX7_SPIn_ADDR[i]); 338 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 339 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 340 FSL_IMX7_SPIn_IRQ[i])); 341 } 342 343 for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) { 344 static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = { 345 FSL_IMX7_I2C1_ADDR, 346 FSL_IMX7_I2C2_ADDR, 347 FSL_IMX7_I2C3_ADDR, 348 FSL_IMX7_I2C4_ADDR, 349 }; 350 351 static const hwaddr FSL_IMX7_I2Cn_IRQ[FSL_IMX7_NUM_I2CS] = { 352 FSL_IMX7_I2C1_IRQ, 353 FSL_IMX7_I2C2_IRQ, 354 FSL_IMX7_I2C3_IRQ, 355 FSL_IMX7_I2C4_IRQ, 356 }; 357 358 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", 359 &error_abort); 360 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]); 361 362 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 363 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 364 FSL_IMX7_I2Cn_IRQ[i])); 365 } 366 367 /* 368 * UART 369 */ 370 for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) { 371 static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = { 372 FSL_IMX7_UART1_ADDR, 373 FSL_IMX7_UART2_ADDR, 374 FSL_IMX7_UART3_ADDR, 375 FSL_IMX7_UART4_ADDR, 376 FSL_IMX7_UART5_ADDR, 377 FSL_IMX7_UART6_ADDR, 378 FSL_IMX7_UART7_ADDR, 379 }; 380 381 static const int FSL_IMX7_UARTn_IRQ[FSL_IMX7_NUM_UARTS] = { 382 FSL_IMX7_UART1_IRQ, 383 FSL_IMX7_UART2_IRQ, 384 FSL_IMX7_UART3_IRQ, 385 FSL_IMX7_UART4_IRQ, 386 FSL_IMX7_UART5_IRQ, 387 FSL_IMX7_UART6_IRQ, 388 FSL_IMX7_UART7_IRQ, 389 }; 390 391 392 if (i < MAX_SERIAL_PORTS) { 393 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]); 394 } 395 396 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", 397 &error_abort); 398 399 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]); 400 401 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_UARTn_IRQ[i]); 402 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq); 403 } 404 405 /* 406 * Ethernet 407 */ 408 for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) { 409 static const hwaddr FSL_IMX7_ENETn_ADDR[FSL_IMX7_NUM_ETHS] = { 410 FSL_IMX7_ENET1_ADDR, 411 FSL_IMX7_ENET2_ADDR, 412 }; 413 414 object_property_set_uint(OBJECT(&s->eth[i]), FSL_IMX7_ETH_NUM_TX_RINGS, 415 "tx-ring-num", &error_abort); 416 qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]); 417 object_property_set_bool(OBJECT(&s->eth[i]), true, "realized", 418 &error_abort); 419 420 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]); 421 422 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 0)); 423 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq); 424 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 3)); 425 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq); 426 } 427 428 /* 429 * USDHC 430 */ 431 for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) { 432 static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = { 433 FSL_IMX7_USDHC1_ADDR, 434 FSL_IMX7_USDHC2_ADDR, 435 FSL_IMX7_USDHC3_ADDR, 436 }; 437 438 static const int FSL_IMX7_USDHCn_IRQ[FSL_IMX7_NUM_USDHCS] = { 439 FSL_IMX7_USDHC1_IRQ, 440 FSL_IMX7_USDHC2_IRQ, 441 FSL_IMX7_USDHC3_IRQ, 442 }; 443 444 object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized", 445 &error_abort); 446 447 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, 448 FSL_IMX7_USDHCn_ADDR[i]); 449 450 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USDHCn_IRQ[i]); 451 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq); 452 } 453 454 /* 455 * SNVS 456 */ 457 object_property_set_bool(OBJECT(&s->snvs), true, "realized", &error_abort); 458 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR); 459 460 /* 461 * SRC 462 */ 463 create_unimplemented_device("sdma", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE); 464 465 /* 466 * Watchdog 467 */ 468 for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) { 469 static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = { 470 FSL_IMX7_WDOG1_ADDR, 471 FSL_IMX7_WDOG2_ADDR, 472 FSL_IMX7_WDOG3_ADDR, 473 FSL_IMX7_WDOG4_ADDR, 474 }; 475 476 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", 477 &error_abort); 478 479 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]); 480 } 481 482 /* 483 * SDMA 484 */ 485 create_unimplemented_device("sdma", FSL_IMX7_SDMA_ADDR, FSL_IMX7_SDMA_SIZE); 486 487 488 object_property_set_bool(OBJECT(&s->gpr), true, "realized", 489 &error_abort); 490 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR); 491 492 object_property_set_bool(OBJECT(&s->pcie), true, 493 "realized", &error_abort); 494 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR); 495 496 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ); 497 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq); 498 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTB_IRQ); 499 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq); 500 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTC_IRQ); 501 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq); 502 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ); 503 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); 504 505 506 for (i = 0; i < FSL_IMX7_NUM_USBS; i++) { 507 static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = { 508 FSL_IMX7_USBMISC1_ADDR, 509 FSL_IMX7_USBMISC2_ADDR, 510 FSL_IMX7_USBMISC3_ADDR, 511 }; 512 513 static const hwaddr FSL_IMX7_USBn_ADDR[FSL_IMX7_NUM_USBS] = { 514 FSL_IMX7_USB1_ADDR, 515 FSL_IMX7_USB2_ADDR, 516 FSL_IMX7_USB3_ADDR, 517 }; 518 519 static const hwaddr FSL_IMX7_USBn_IRQ[FSL_IMX7_NUM_USBS] = { 520 FSL_IMX7_USB1_IRQ, 521 FSL_IMX7_USB2_IRQ, 522 FSL_IMX7_USB3_IRQ, 523 }; 524 525 object_property_set_bool(OBJECT(&s->usb[i]), true, "realized", 526 &error_abort); 527 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, 528 FSL_IMX7_USBn_ADDR[i]); 529 530 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USBn_IRQ[i]); 531 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, irq); 532 533 snprintf(name, NAME_SIZE, "usbmisc%d", i); 534 create_unimplemented_device(name, FSL_IMX7_USBMISCn_ADDR[i], 535 FSL_IMX7_USBMISCn_SIZE); 536 } 537 538 /* 539 * ADCs 540 */ 541 for (i = 0; i < FSL_IMX7_NUM_ADCS; i++) { 542 static const hwaddr FSL_IMX7_ADCn_ADDR[FSL_IMX7_NUM_ADCS] = { 543 FSL_IMX7_ADC1_ADDR, 544 FSL_IMX7_ADC2_ADDR, 545 }; 546 547 snprintf(name, NAME_SIZE, "adc%d", i); 548 create_unimplemented_device(name, FSL_IMX7_ADCn_ADDR[i], 549 FSL_IMX7_ADCn_SIZE); 550 } 551 552 /* 553 * LCD 554 */ 555 create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR, 556 FSL_IMX7_LCDIF_SIZE); 557 } 558 559 static void fsl_imx7_class_init(ObjectClass *oc, void *data) 560 { 561 DeviceClass *dc = DEVICE_CLASS(oc); 562 563 dc->realize = fsl_imx7_realize; 564 565 /* Reason: Uses serial_hds and nd_table in realize() directly */ 566 dc->user_creatable = false; 567 dc->desc = "i.MX7 SOC"; 568 } 569 570 static const TypeInfo fsl_imx7_type_info = { 571 .name = TYPE_FSL_IMX7, 572 .parent = TYPE_DEVICE, 573 .instance_size = sizeof(FslIMX7State), 574 .instance_init = fsl_imx7_init, 575 .class_init = fsl_imx7_class_init, 576 }; 577 578 static void fsl_imx7_register_types(void) 579 { 580 type_register_static(&fsl_imx7_type_info); 581 } 582 type_init(fsl_imx7_register_types) 583