xref: /openbmc/qemu/hw/arm/fsl-imx7.c (revision b21e2380)
1  /*
2   * Copyright (c) 2018, Impinj, Inc.
3   *
4   * i.MX7 SoC definitions
5   *
6   * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
7   *
8   * Based on hw/arm/fsl-imx6.c
9   *
10   * This program is free software; you can redistribute it and/or modify
11   * it under the terms of the GNU General Public License as published by
12   * the Free Software Foundation; either version 2 of the License, or
13   * (at your option) any later version.
14   *
15   * This program is distributed in the hope that it will be useful,
16   * but WITHOUT ANY WARRANTY; without even the implied warranty of
17   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18   * GNU General Public License for more details.
19   */
20  
21  #include "qemu/osdep.h"
22  #include "qapi/error.h"
23  #include "hw/arm/fsl-imx7.h"
24  #include "hw/misc/unimp.h"
25  #include "hw/boards.h"
26  #include "sysemu/sysemu.h"
27  #include "qemu/error-report.h"
28  #include "qemu/module.h"
29  
30  #define NAME_SIZE 20
31  
32  static void fsl_imx7_init(Object *obj)
33  {
34      MachineState *ms = MACHINE(qdev_get_machine());
35      FslIMX7State *s = FSL_IMX7(obj);
36      char name[NAME_SIZE];
37      int i;
38  
39      for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
40          snprintf(name, NAME_SIZE, "cpu%d", i);
41          object_initialize_child(obj, name, &s->cpu[i],
42                                  ARM_CPU_TYPE_NAME("cortex-a7"));
43      }
44  
45      /*
46       * A7MPCORE
47       */
48      object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
49                              TYPE_A15MPCORE_PRIV);
50  
51      /*
52       * GPIOs 1 to 7
53       */
54      for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
55          snprintf(name, NAME_SIZE, "gpio%d", i);
56          object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
57      }
58  
59      /*
60       * GPT1, 2, 3, 4
61       */
62      for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
63          snprintf(name, NAME_SIZE, "gpt%d", i);
64          object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT);
65      }
66  
67      /*
68       * CCM
69       */
70      object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX7_CCM);
71  
72      /*
73       * Analog
74       */
75      object_initialize_child(obj, "analog", &s->analog, TYPE_IMX7_ANALOG);
76  
77      /*
78       * GPCv2
79       */
80      object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
81  
82      for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
83          snprintf(name, NAME_SIZE, "spi%d", i + 1);
84          object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
85      }
86  
87  
88      for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
89          snprintf(name, NAME_SIZE, "i2c%d", i + 1);
90          object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
91      }
92  
93      /*
94       * UART
95       */
96      for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
97              snprintf(name, NAME_SIZE, "uart%d", i);
98              object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
99      }
100  
101      /*
102       * Ethernet
103       */
104      for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
105              snprintf(name, NAME_SIZE, "eth%d", i);
106              object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
107      }
108  
109      /*
110       * SDHCI
111       */
112      for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
113              snprintf(name, NAME_SIZE, "usdhc%d", i);
114              object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
115      }
116  
117      /*
118       * SNVS
119       */
120      object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
121  
122      /*
123       * Watchdog
124       */
125      for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
126              snprintf(name, NAME_SIZE, "wdt%d", i);
127              object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
128      }
129  
130      /*
131       * GPR
132       */
133      object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
134  
135      object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
136  
137      for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
138          snprintf(name, NAME_SIZE, "usb%d", i);
139          object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
140      }
141  }
142  
143  static void fsl_imx7_realize(DeviceState *dev, Error **errp)
144  {
145      MachineState *ms = MACHINE(qdev_get_machine());
146      FslIMX7State *s = FSL_IMX7(dev);
147      Object *o;
148      int i;
149      qemu_irq irq;
150      char name[NAME_SIZE];
151      unsigned int smp_cpus = ms->smp.cpus;
152  
153      if (smp_cpus > FSL_IMX7_NUM_CPUS) {
154          error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
155                     TYPE_FSL_IMX7, FSL_IMX7_NUM_CPUS, smp_cpus);
156          return;
157      }
158  
159      for (i = 0; i < smp_cpus; i++) {
160          o = OBJECT(&s->cpu[i]);
161  
162          /* On uniprocessor, the CBAR is set to 0 */
163          if (smp_cpus > 1) {
164              object_property_set_int(o, "reset-cbar", FSL_IMX7_A7MPCORE_ADDR,
165                                      &error_abort);
166          }
167  
168          if (i) {
169              /*
170               * Secondary CPUs start in powered-down state (and can be
171               * powered up via the SRC system reset controller)
172               */
173              object_property_set_bool(o, "start-powered-off", true,
174                                       &error_abort);
175          }
176  
177          qdev_realize(DEVICE(o), NULL, &error_abort);
178      }
179  
180      /*
181       * A7MPCORE
182       */
183      object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", smp_cpus,
184                              &error_abort);
185      object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
186                              FSL_IMX7_MAX_IRQ + GIC_INTERNAL, &error_abort);
187  
188      sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
189      sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR);
190  
191      for (i = 0; i < smp_cpus; i++) {
192          SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
193          DeviceState  *d   = DEVICE(qemu_get_cpu(i));
194  
195          irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
196          sysbus_connect_irq(sbd, i, irq);
197          irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
198          sysbus_connect_irq(sbd, i + smp_cpus, irq);
199          irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
200          sysbus_connect_irq(sbd, i + 2 * smp_cpus, irq);
201          irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
202          sysbus_connect_irq(sbd, i + 3 * smp_cpus, irq);
203      }
204  
205      /*
206       * A7MPCORE DAP
207       */
208      create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR,
209                                  0x100000);
210  
211      /*
212       * GPT1, 2, 3, 4
213       */
214      for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
215          static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
216              FSL_IMX7_GPT1_ADDR,
217              FSL_IMX7_GPT2_ADDR,
218              FSL_IMX7_GPT3_ADDR,
219              FSL_IMX7_GPT4_ADDR,
220          };
221  
222          s->gpt[i].ccm = IMX_CCM(&s->ccm);
223          sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort);
224          sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]);
225      }
226  
227      for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
228          static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
229              FSL_IMX7_GPIO1_ADDR,
230              FSL_IMX7_GPIO2_ADDR,
231              FSL_IMX7_GPIO3_ADDR,
232              FSL_IMX7_GPIO4_ADDR,
233              FSL_IMX7_GPIO5_ADDR,
234              FSL_IMX7_GPIO6_ADDR,
235              FSL_IMX7_GPIO7_ADDR,
236          };
237  
238          sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort);
239          sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, FSL_IMX7_GPIOn_ADDR[i]);
240      }
241  
242      /*
243       * IOMUXC and IOMUXC_LPSR
244       */
245      for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
246          static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {
247              FSL_IMX7_IOMUXC_ADDR,
248              FSL_IMX7_IOMUXC_LPSR_ADDR,
249          };
250  
251          snprintf(name, NAME_SIZE, "iomuxc%d", i);
252          create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
253                                      FSL_IMX7_IOMUXCn_SIZE);
254      }
255  
256      /*
257       * CCM
258       */
259      sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_abort);
260      sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX7_CCM_ADDR);
261  
262      /*
263       * Analog
264       */
265      sysbus_realize(SYS_BUS_DEVICE(&s->analog), &error_abort);
266      sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0, FSL_IMX7_ANALOG_ADDR);
267  
268      /*
269       * GPCv2
270       */
271      sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
272      sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
273  
274      /* Initialize all ECSPI */
275      for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
276          static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
277              FSL_IMX7_ECSPI1_ADDR,
278              FSL_IMX7_ECSPI2_ADDR,
279              FSL_IMX7_ECSPI3_ADDR,
280              FSL_IMX7_ECSPI4_ADDR,
281          };
282  
283          static const int FSL_IMX7_SPIn_IRQ[FSL_IMX7_NUM_ECSPIS] = {
284              FSL_IMX7_ECSPI1_IRQ,
285              FSL_IMX7_ECSPI2_IRQ,
286              FSL_IMX7_ECSPI3_IRQ,
287              FSL_IMX7_ECSPI4_IRQ,
288          };
289  
290          /* Initialize the SPI */
291          sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &error_abort);
292          sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
293                          FSL_IMX7_SPIn_ADDR[i]);
294          sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
295                             qdev_get_gpio_in(DEVICE(&s->a7mpcore),
296                                              FSL_IMX7_SPIn_IRQ[i]));
297      }
298  
299      for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
300          static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
301              FSL_IMX7_I2C1_ADDR,
302              FSL_IMX7_I2C2_ADDR,
303              FSL_IMX7_I2C3_ADDR,
304              FSL_IMX7_I2C4_ADDR,
305          };
306  
307          static const int FSL_IMX7_I2Cn_IRQ[FSL_IMX7_NUM_I2CS] = {
308              FSL_IMX7_I2C1_IRQ,
309              FSL_IMX7_I2C2_IRQ,
310              FSL_IMX7_I2C3_IRQ,
311              FSL_IMX7_I2C4_IRQ,
312          };
313  
314          sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_abort);
315          sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]);
316  
317          sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
318                             qdev_get_gpio_in(DEVICE(&s->a7mpcore),
319                                              FSL_IMX7_I2Cn_IRQ[i]));
320      }
321  
322      /*
323       * UART
324       */
325      for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
326          static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
327              FSL_IMX7_UART1_ADDR,
328              FSL_IMX7_UART2_ADDR,
329              FSL_IMX7_UART3_ADDR,
330              FSL_IMX7_UART4_ADDR,
331              FSL_IMX7_UART5_ADDR,
332              FSL_IMX7_UART6_ADDR,
333              FSL_IMX7_UART7_ADDR,
334          };
335  
336          static const int FSL_IMX7_UARTn_IRQ[FSL_IMX7_NUM_UARTS] = {
337              FSL_IMX7_UART1_IRQ,
338              FSL_IMX7_UART2_IRQ,
339              FSL_IMX7_UART3_IRQ,
340              FSL_IMX7_UART4_IRQ,
341              FSL_IMX7_UART5_IRQ,
342              FSL_IMX7_UART6_IRQ,
343              FSL_IMX7_UART7_IRQ,
344          };
345  
346  
347          qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
348  
349          sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &error_abort);
350  
351          sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]);
352  
353          irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_UARTn_IRQ[i]);
354          sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq);
355      }
356  
357      /*
358       * Ethernet
359       */
360      for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
361          static const hwaddr FSL_IMX7_ENETn_ADDR[FSL_IMX7_NUM_ETHS] = {
362              FSL_IMX7_ENET1_ADDR,
363              FSL_IMX7_ENET2_ADDR,
364          };
365  
366          object_property_set_uint(OBJECT(&s->eth[i]), "phy-num",
367                                   s->phy_num[i], &error_abort);
368          object_property_set_uint(OBJECT(&s->eth[i]), "tx-ring-num",
369                                   FSL_IMX7_ETH_NUM_TX_RINGS, &error_abort);
370          qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
371          sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort);
372  
373          sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]);
374  
375          irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 0));
376          sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq);
377          irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 3));
378          sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq);
379      }
380  
381      /*
382       * USDHC
383       */
384      for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
385          static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
386              FSL_IMX7_USDHC1_ADDR,
387              FSL_IMX7_USDHC2_ADDR,
388              FSL_IMX7_USDHC3_ADDR,
389          };
390  
391          static const int FSL_IMX7_USDHCn_IRQ[FSL_IMX7_NUM_USDHCS] = {
392              FSL_IMX7_USDHC1_IRQ,
393              FSL_IMX7_USDHC2_IRQ,
394              FSL_IMX7_USDHC3_IRQ,
395          };
396  
397          object_property_set_uint(OBJECT(&s->usdhc[i]), "vendor",
398                                   SDHCI_VENDOR_IMX, &error_abort);
399          sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort);
400  
401          sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
402                          FSL_IMX7_USDHCn_ADDR[i]);
403  
404          irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USDHCn_IRQ[i]);
405          sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq);
406      }
407  
408      /*
409       * SNVS
410       */
411      sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
412      sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
413  
414      /*
415       * SRC
416       */
417      create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
418  
419      /*
420       * Watchdog
421       */
422      for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
423          static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
424              FSL_IMX7_WDOG1_ADDR,
425              FSL_IMX7_WDOG2_ADDR,
426              FSL_IMX7_WDOG3_ADDR,
427              FSL_IMX7_WDOG4_ADDR,
428          };
429          static const int FSL_IMX7_WDOGn_IRQ[FSL_IMX7_NUM_WDTS] = {
430              FSL_IMX7_WDOG1_IRQ,
431              FSL_IMX7_WDOG2_IRQ,
432              FSL_IMX7_WDOG3_IRQ,
433              FSL_IMX7_WDOG4_IRQ,
434          };
435  
436          object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support",
437                                   true, &error_abort);
438          sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
439  
440          sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]);
441          sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
442                             qdev_get_gpio_in(DEVICE(&s->a7mpcore),
443                                              FSL_IMX7_WDOGn_IRQ[i]));
444      }
445  
446      /*
447       * SDMA
448       */
449      create_unimplemented_device("sdma", FSL_IMX7_SDMA_ADDR, FSL_IMX7_SDMA_SIZE);
450  
451      /*
452       * CAAM
453       */
454      create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
455  
456      /*
457       * PWM
458       */
459      create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
460      create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
461      create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
462      create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
463  
464      /*
465       * CAN
466       */
467      create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
468      create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
469  
470      /*
471       * SAI (Audio SSI (Synchronous Serial Interface))
472       */
473      create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE);
474      create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE);
475      create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE);
476  
477      /*
478       * OCOTP
479       */
480      create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
481                                  FSL_IMX7_OCOTP_SIZE);
482  
483      sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
484      sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
485  
486      sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
487      sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
488  
489      irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ);
490      sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq);
491      irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTB_IRQ);
492      sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq);
493      irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTC_IRQ);
494      sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq);
495      irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
496      sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
497  
498  
499      for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
500          static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = {
501              FSL_IMX7_USBMISC1_ADDR,
502              FSL_IMX7_USBMISC2_ADDR,
503              FSL_IMX7_USBMISC3_ADDR,
504          };
505  
506          static const hwaddr FSL_IMX7_USBn_ADDR[FSL_IMX7_NUM_USBS] = {
507              FSL_IMX7_USB1_ADDR,
508              FSL_IMX7_USB2_ADDR,
509              FSL_IMX7_USB3_ADDR,
510          };
511  
512          static const int FSL_IMX7_USBn_IRQ[FSL_IMX7_NUM_USBS] = {
513              FSL_IMX7_USB1_IRQ,
514              FSL_IMX7_USB2_IRQ,
515              FSL_IMX7_USB3_IRQ,
516          };
517  
518          sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
519          sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
520                          FSL_IMX7_USBn_ADDR[i]);
521  
522          irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USBn_IRQ[i]);
523          sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, irq);
524  
525          snprintf(name, NAME_SIZE, "usbmisc%d", i);
526          create_unimplemented_device(name, FSL_IMX7_USBMISCn_ADDR[i],
527                                      FSL_IMX7_USBMISCn_SIZE);
528      }
529  
530      /*
531       * ADCs
532       */
533      for (i = 0; i < FSL_IMX7_NUM_ADCS; i++) {
534          static const hwaddr FSL_IMX7_ADCn_ADDR[FSL_IMX7_NUM_ADCS] = {
535              FSL_IMX7_ADC1_ADDR,
536              FSL_IMX7_ADC2_ADDR,
537          };
538  
539          snprintf(name, NAME_SIZE, "adc%d", i);
540          create_unimplemented_device(name, FSL_IMX7_ADCn_ADDR[i],
541                                      FSL_IMX7_ADCn_SIZE);
542      }
543  
544      /*
545       * LCD
546       */
547      create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR,
548                                  FSL_IMX7_LCDIF_SIZE);
549  
550      /*
551       * DMA APBH
552       */
553      create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR,
554                                  FSL_IMX7_DMA_APBH_SIZE);
555      /*
556       * PCIe PHY
557       */
558      create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
559                                  FSL_IMX7_PCIE_PHY_SIZE);
560  }
561  
562  static Property fsl_imx7_properties[] = {
563      DEFINE_PROP_UINT32("fec1-phy-num", FslIMX7State, phy_num[0], 0),
564      DEFINE_PROP_UINT32("fec2-phy-num", FslIMX7State, phy_num[1], 1),
565      DEFINE_PROP_END_OF_LIST(),
566  };
567  
568  static void fsl_imx7_class_init(ObjectClass *oc, void *data)
569  {
570      DeviceClass *dc = DEVICE_CLASS(oc);
571  
572      device_class_set_props(dc, fsl_imx7_properties);
573      dc->realize = fsl_imx7_realize;
574  
575      /* Reason: Uses serial_hds and nd_table in realize() directly */
576      dc->user_creatable = false;
577      dc->desc = "i.MX7 SOC";
578  }
579  
580  static const TypeInfo fsl_imx7_type_info = {
581      .name = TYPE_FSL_IMX7,
582      .parent = TYPE_DEVICE,
583      .instance_size = sizeof(FslIMX7State),
584      .instance_init = fsl_imx7_init,
585      .class_init = fsl_imx7_class_init,
586  };
587  
588  static void fsl_imx7_register_types(void)
589  {
590      type_register_static(&fsl_imx7_type_info);
591  }
592  type_init(fsl_imx7_register_types)
593