1 /* 2 * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX6UL SOC emulation. 5 * 6 * Based on hw/arm/fsl-imx7.c 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qapi/error.h" 21 #include "hw/arm/fsl-imx6ul.h" 22 #include "hw/misc/unimp.h" 23 #include "hw/usb/imx-usb-phy.h" 24 #include "hw/boards.h" 25 #include "sysemu/sysemu.h" 26 #include "qemu/error-report.h" 27 #include "qemu/module.h" 28 #include "target/arm/cpu-qom.h" 29 30 #define NAME_SIZE 20 31 32 static void fsl_imx6ul_init(Object *obj) 33 { 34 FslIMX6ULState *s = FSL_IMX6UL(obj); 35 char name[NAME_SIZE]; 36 int i; 37 38 object_initialize_child(obj, "cpu0", &s->cpu, 39 ARM_CPU_TYPE_NAME("cortex-a7")); 40 41 /* 42 * A7MPCORE 43 */ 44 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, 45 TYPE_A15MPCORE_PRIV); 46 47 /* 48 * CCM 49 */ 50 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6UL_CCM); 51 52 /* 53 * SRC 54 */ 55 object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC); 56 57 /* 58 * GPCv2 59 */ 60 object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2); 61 62 /* 63 * SNVS 64 */ 65 object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); 66 67 /* 68 * GPIOs 69 */ 70 for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { 71 snprintf(name, NAME_SIZE, "gpio%d", i); 72 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); 73 } 74 75 /* 76 * GPTs 77 */ 78 for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { 79 snprintf(name, NAME_SIZE, "gpt%d", i); 80 object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX6UL_GPT); 81 } 82 83 /* 84 * EPITs 85 */ 86 for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) { 87 snprintf(name, NAME_SIZE, "epit%d", i + 1); 88 object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT); 89 } 90 91 /* 92 * eCSPIs 93 */ 94 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { 95 snprintf(name, NAME_SIZE, "spi%d", i + 1); 96 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); 97 } 98 99 /* 100 * I2Cs 101 */ 102 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { 103 snprintf(name, NAME_SIZE, "i2c%d", i + 1); 104 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); 105 } 106 107 /* 108 * UARTs 109 */ 110 for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) { 111 snprintf(name, NAME_SIZE, "uart%d", i); 112 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); 113 } 114 115 /* 116 * Ethernets 117 */ 118 for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { 119 snprintf(name, NAME_SIZE, "eth%d", i); 120 object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET); 121 } 122 123 /* 124 * USB PHYs 125 */ 126 for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { 127 snprintf(name, NAME_SIZE, "usbphy%d", i); 128 object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY); 129 } 130 131 /* 132 * USBs 133 */ 134 for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) { 135 snprintf(name, NAME_SIZE, "usb%d", i); 136 object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); 137 } 138 139 /* 140 * SDHCIs 141 */ 142 for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { 143 snprintf(name, NAME_SIZE, "usdhc%d", i); 144 object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); 145 } 146 147 /* 148 * Watchdogs 149 */ 150 for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) { 151 snprintf(name, NAME_SIZE, "wdt%d", i); 152 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT); 153 } 154 } 155 156 static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) 157 { 158 MachineState *ms = MACHINE(qdev_get_machine()); 159 FslIMX6ULState *s = FSL_IMX6UL(dev); 160 int i; 161 char name[NAME_SIZE]; 162 SysBusDevice *sbd; 163 DeviceState *d; 164 165 if (ms->smp.cpus > 1) { 166 error_setg(errp, "%s: Only a single CPU is supported (%d requested)", 167 TYPE_FSL_IMX6UL, ms->smp.cpus); 168 return; 169 } 170 171 qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); 172 173 /* 174 * A7MPCORE 175 */ 176 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", 1, &error_abort); 177 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", 178 FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL, &error_abort); 179 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 180 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR); 181 182 sbd = SYS_BUS_DEVICE(&s->a7mpcore); 183 d = DEVICE(&s->cpu); 184 185 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ)); 186 sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ)); 187 sysbus_connect_irq(sbd, 2, qdev_get_gpio_in(d, ARM_CPU_VIRQ)); 188 sysbus_connect_irq(sbd, 3, qdev_get_gpio_in(d, ARM_CPU_VFIQ)); 189 190 /* 191 * A7MPCORE DAP 192 */ 193 create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR, 194 FSL_IMX6UL_A7MPCORE_DAP_SIZE); 195 196 /* 197 * GPTs 198 */ 199 for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { 200 static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = { 201 FSL_IMX6UL_GPT1_ADDR, 202 FSL_IMX6UL_GPT2_ADDR, 203 }; 204 205 static const int FSL_IMX6UL_GPTn_IRQ[FSL_IMX6UL_NUM_GPTS] = { 206 FSL_IMX6UL_GPT1_IRQ, 207 FSL_IMX6UL_GPT2_IRQ, 208 }; 209 210 s->gpt[i].ccm = IMX_CCM(&s->ccm); 211 sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort); 212 213 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, 214 FSL_IMX6UL_GPTn_ADDR[i]); 215 216 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, 217 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 218 FSL_IMX6UL_GPTn_IRQ[i])); 219 } 220 221 /* 222 * EPITs 223 */ 224 for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) { 225 static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = { 226 FSL_IMX6UL_EPIT1_ADDR, 227 FSL_IMX6UL_EPIT2_ADDR, 228 }; 229 230 static const int FSL_IMX6UL_EPITn_IRQ[FSL_IMX6UL_NUM_EPITS] = { 231 FSL_IMX6UL_EPIT1_IRQ, 232 FSL_IMX6UL_EPIT2_IRQ, 233 }; 234 235 s->epit[i].ccm = IMX_CCM(&s->ccm); 236 sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &error_abort); 237 238 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, 239 FSL_IMX6UL_EPITn_ADDR[i]); 240 241 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 242 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 243 FSL_IMX6UL_EPITn_IRQ[i])); 244 } 245 246 /* 247 * GPIOs 248 */ 249 for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { 250 static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = { 251 FSL_IMX6UL_GPIO1_ADDR, 252 FSL_IMX6UL_GPIO2_ADDR, 253 FSL_IMX6UL_GPIO3_ADDR, 254 FSL_IMX6UL_GPIO4_ADDR, 255 FSL_IMX6UL_GPIO5_ADDR, 256 }; 257 258 static const int FSL_IMX6UL_GPIOn_LOW_IRQ[FSL_IMX6UL_NUM_GPIOS] = { 259 FSL_IMX6UL_GPIO1_LOW_IRQ, 260 FSL_IMX6UL_GPIO2_LOW_IRQ, 261 FSL_IMX6UL_GPIO3_LOW_IRQ, 262 FSL_IMX6UL_GPIO4_LOW_IRQ, 263 FSL_IMX6UL_GPIO5_LOW_IRQ, 264 }; 265 266 static const int FSL_IMX6UL_GPIOn_HIGH_IRQ[FSL_IMX6UL_NUM_GPIOS] = { 267 FSL_IMX6UL_GPIO1_HIGH_IRQ, 268 FSL_IMX6UL_GPIO2_HIGH_IRQ, 269 FSL_IMX6UL_GPIO3_HIGH_IRQ, 270 FSL_IMX6UL_GPIO4_HIGH_IRQ, 271 FSL_IMX6UL_GPIO5_HIGH_IRQ, 272 }; 273 274 sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort); 275 276 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, 277 FSL_IMX6UL_GPIOn_ADDR[i]); 278 279 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 280 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 281 FSL_IMX6UL_GPIOn_LOW_IRQ[i])); 282 283 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, 284 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 285 FSL_IMX6UL_GPIOn_HIGH_IRQ[i])); 286 } 287 288 /* 289 * IOMUXC 290 */ 291 create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR, 292 FSL_IMX6UL_IOMUXC_SIZE); 293 create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR, 294 FSL_IMX6UL_IOMUXC_GPR_SIZE); 295 296 /* 297 * CCM 298 */ 299 sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_abort); 300 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6UL_CCM_ADDR); 301 302 /* 303 * SRC 304 */ 305 sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort); 306 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6UL_SRC_ADDR); 307 308 /* 309 * GPCv2 310 */ 311 sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort); 312 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR); 313 314 /* 315 * ECSPIs 316 */ 317 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { 318 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { 319 FSL_IMX6UL_ECSPI1_ADDR, 320 FSL_IMX6UL_ECSPI2_ADDR, 321 FSL_IMX6UL_ECSPI3_ADDR, 322 FSL_IMX6UL_ECSPI4_ADDR, 323 }; 324 325 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { 326 FSL_IMX6UL_ECSPI1_IRQ, 327 FSL_IMX6UL_ECSPI2_IRQ, 328 FSL_IMX6UL_ECSPI3_IRQ, 329 FSL_IMX6UL_ECSPI4_IRQ, 330 }; 331 332 /* Initialize the SPI */ 333 sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &error_abort); 334 335 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 336 FSL_IMX6UL_SPIn_ADDR[i]); 337 338 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 339 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 340 FSL_IMX6UL_SPIn_IRQ[i])); 341 } 342 343 /* 344 * I2Cs 345 */ 346 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { 347 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { 348 FSL_IMX6UL_I2C1_ADDR, 349 FSL_IMX6UL_I2C2_ADDR, 350 FSL_IMX6UL_I2C3_ADDR, 351 FSL_IMX6UL_I2C4_ADDR, 352 }; 353 354 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { 355 FSL_IMX6UL_I2C1_IRQ, 356 FSL_IMX6UL_I2C2_IRQ, 357 FSL_IMX6UL_I2C3_IRQ, 358 FSL_IMX6UL_I2C4_IRQ, 359 }; 360 361 sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_abort); 362 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]); 363 364 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 365 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 366 FSL_IMX6UL_I2Cn_IRQ[i])); 367 } 368 369 /* 370 * UARTs 371 */ 372 for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) { 373 static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = { 374 FSL_IMX6UL_UART1_ADDR, 375 FSL_IMX6UL_UART2_ADDR, 376 FSL_IMX6UL_UART3_ADDR, 377 FSL_IMX6UL_UART4_ADDR, 378 FSL_IMX6UL_UART5_ADDR, 379 FSL_IMX6UL_UART6_ADDR, 380 FSL_IMX6UL_UART7_ADDR, 381 FSL_IMX6UL_UART8_ADDR, 382 }; 383 384 static const int FSL_IMX6UL_UARTn_IRQ[FSL_IMX6UL_NUM_UARTS] = { 385 FSL_IMX6UL_UART1_IRQ, 386 FSL_IMX6UL_UART2_IRQ, 387 FSL_IMX6UL_UART3_IRQ, 388 FSL_IMX6UL_UART4_IRQ, 389 FSL_IMX6UL_UART5_IRQ, 390 FSL_IMX6UL_UART6_IRQ, 391 FSL_IMX6UL_UART7_IRQ, 392 FSL_IMX6UL_UART8_IRQ, 393 }; 394 395 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 396 397 sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &error_abort); 398 399 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, 400 FSL_IMX6UL_UARTn_ADDR[i]); 401 402 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 403 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 404 FSL_IMX6UL_UARTn_IRQ[i])); 405 } 406 407 /* 408 * Ethernets 409 * 410 * We must use two loops since phy_connected affects the other interface 411 * and we have to set all properties before calling sysbus_realize(). 412 */ 413 for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { 414 object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected", 415 s->phy_connected[i], &error_abort); 416 /* 417 * If the MDIO bus on this controller is not connected, assume the 418 * other controller provides support for it. 419 */ 420 if (!s->phy_connected[i]) { 421 object_property_set_link(OBJECT(&s->eth[1 - i]), "phy-consumer", 422 OBJECT(&s->eth[i]), &error_abort); 423 } 424 } 425 426 for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { 427 static const hwaddr FSL_IMX6UL_ENETn_ADDR[FSL_IMX6UL_NUM_ETHS] = { 428 FSL_IMX6UL_ENET1_ADDR, 429 FSL_IMX6UL_ENET2_ADDR, 430 }; 431 432 static const int FSL_IMX6UL_ENETn_IRQ[FSL_IMX6UL_NUM_ETHS] = { 433 FSL_IMX6UL_ENET1_IRQ, 434 FSL_IMX6UL_ENET2_IRQ, 435 }; 436 437 static const int FSL_IMX6UL_ENETn_TIMER_IRQ[FSL_IMX6UL_NUM_ETHS] = { 438 FSL_IMX6UL_ENET1_TIMER_IRQ, 439 FSL_IMX6UL_ENET2_TIMER_IRQ, 440 }; 441 442 object_property_set_uint(OBJECT(&s->eth[i]), "phy-num", 443 s->phy_num[i], &error_abort); 444 object_property_set_uint(OBJECT(&s->eth[i]), "tx-ring-num", 445 FSL_IMX6UL_ETH_NUM_TX_RINGS, &error_abort); 446 qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]); 447 sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort); 448 449 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, 450 FSL_IMX6UL_ENETn_ADDR[i]); 451 452 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, 453 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 454 FSL_IMX6UL_ENETn_IRQ[i])); 455 456 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, 457 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 458 FSL_IMX6UL_ENETn_TIMER_IRQ[i])); 459 } 460 461 /* 462 * USB PHYs 463 */ 464 for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { 465 static const hwaddr 466 FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = { 467 FSL_IMX6UL_USBPHY1_ADDR, 468 FSL_IMX6UL_USBPHY2_ADDR, 469 }; 470 471 sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort); 472 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0, 473 FSL_IMX6UL_USB_PHYn_ADDR[i]); 474 } 475 476 /* 477 * USBs 478 */ 479 for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) { 480 static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = { 481 FSL_IMX6UL_USBO2_USB1_ADDR, 482 FSL_IMX6UL_USBO2_USB2_ADDR, 483 }; 484 485 static const int FSL_IMX6UL_USBn_IRQ[] = { 486 FSL_IMX6UL_USB1_IRQ, 487 FSL_IMX6UL_USB2_IRQ, 488 }; 489 490 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); 491 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, 492 FSL_IMX6UL_USB02_USBn_ADDR[i]); 493 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, 494 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 495 FSL_IMX6UL_USBn_IRQ[i])); 496 } 497 498 /* 499 * USDHCs 500 */ 501 for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { 502 static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = { 503 FSL_IMX6UL_USDHC1_ADDR, 504 FSL_IMX6UL_USDHC2_ADDR, 505 }; 506 507 static const int FSL_IMX6UL_USDHCn_IRQ[FSL_IMX6UL_NUM_USDHCS] = { 508 FSL_IMX6UL_USDHC1_IRQ, 509 FSL_IMX6UL_USDHC2_IRQ, 510 }; 511 512 object_property_set_uint(OBJECT(&s->usdhc[i]), "vendor", 513 SDHCI_VENDOR_IMX, &error_abort); 514 sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort); 515 516 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, 517 FSL_IMX6UL_USDHCn_ADDR[i]); 518 519 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, 520 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 521 FSL_IMX6UL_USDHCn_IRQ[i])); 522 } 523 524 /* 525 * SNVS 526 */ 527 sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort); 528 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR); 529 530 /* 531 * Watchdogs 532 */ 533 for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) { 534 static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = { 535 FSL_IMX6UL_WDOG1_ADDR, 536 FSL_IMX6UL_WDOG2_ADDR, 537 FSL_IMX6UL_WDOG3_ADDR, 538 }; 539 540 static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = { 541 FSL_IMX6UL_WDOG1_IRQ, 542 FSL_IMX6UL_WDOG2_IRQ, 543 FSL_IMX6UL_WDOG3_IRQ, 544 }; 545 546 object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", 547 true, &error_abort); 548 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); 549 550 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 551 FSL_IMX6UL_WDOGn_ADDR[i]); 552 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, 553 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 554 FSL_IMX6UL_WDOGn_IRQ[i])); 555 } 556 557 /* 558 * SDMA 559 */ 560 create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 561 FSL_IMX6UL_SDMA_SIZE); 562 563 /* 564 * SAIs (Audio SSI (Synchronous Serial Interface)) 565 */ 566 for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) { 567 static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = { 568 FSL_IMX6UL_SAI1_ADDR, 569 FSL_IMX6UL_SAI2_ADDR, 570 FSL_IMX6UL_SAI3_ADDR, 571 }; 572 573 snprintf(name, NAME_SIZE, "sai%d", i); 574 create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i], 575 FSL_IMX6UL_SAIn_SIZE); 576 } 577 578 /* 579 * PWMs 580 */ 581 for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) { 582 static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = { 583 FSL_IMX6UL_PWM1_ADDR, 584 FSL_IMX6UL_PWM2_ADDR, 585 FSL_IMX6UL_PWM3_ADDR, 586 FSL_IMX6UL_PWM4_ADDR, 587 FSL_IMX6UL_PWM5_ADDR, 588 FSL_IMX6UL_PWM6_ADDR, 589 FSL_IMX6UL_PWM7_ADDR, 590 FSL_IMX6UL_PWM8_ADDR, 591 }; 592 593 snprintf(name, NAME_SIZE, "pwm%d", i); 594 create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i], 595 FSL_IMX6UL_PWMn_SIZE); 596 } 597 598 /* 599 * Audio ASRC (asynchronous sample rate converter) 600 */ 601 create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 602 FSL_IMX6UL_ASRC_SIZE); 603 604 /* 605 * CANs 606 */ 607 for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) { 608 static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = { 609 FSL_IMX6UL_CAN1_ADDR, 610 FSL_IMX6UL_CAN2_ADDR, 611 }; 612 613 snprintf(name, NAME_SIZE, "can%d", i); 614 create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i], 615 FSL_IMX6UL_CANn_SIZE); 616 } 617 618 /* 619 * APHB_DMA 620 */ 621 create_unimplemented_device("aphb_dma", FSL_IMX6UL_APBH_DMA_ADDR, 622 FSL_IMX6UL_APBH_DMA_SIZE); 623 624 /* 625 * ADCs 626 */ 627 for (i = 0; i < FSL_IMX6UL_NUM_ADCS; i++) { 628 static const hwaddr FSL_IMX6UL_ADCn_ADDR[FSL_IMX6UL_NUM_ADCS] = { 629 FSL_IMX6UL_ADC1_ADDR, 630 FSL_IMX6UL_ADC2_ADDR, 631 }; 632 633 snprintf(name, NAME_SIZE, "adc%d", i); 634 create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 635 FSL_IMX6UL_ADCn_SIZE); 636 } 637 638 /* 639 * LCD 640 */ 641 create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 642 FSL_IMX6UL_LCDIF_SIZE); 643 644 /* 645 * CSU 646 */ 647 create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR, 648 FSL_IMX6UL_CSU_SIZE); 649 650 /* 651 * TZASC 652 */ 653 create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR, 654 FSL_IMX6UL_TZASC_SIZE); 655 656 /* 657 * ROM memory 658 */ 659 memory_region_init_rom(&s->rom, OBJECT(dev), "imx6ul.rom", 660 FSL_IMX6UL_ROM_SIZE, &error_abort); 661 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_ROM_ADDR, 662 &s->rom); 663 664 /* 665 * CAAM memory 666 */ 667 memory_region_init_rom(&s->caam, OBJECT(dev), "imx6ul.caam", 668 FSL_IMX6UL_CAAM_MEM_SIZE, &error_abort); 669 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_CAAM_MEM_ADDR, 670 &s->caam); 671 672 /* 673 * OCRAM memory 674 */ 675 memory_region_init_ram(&s->ocram, NULL, "imx6ul.ocram", 676 FSL_IMX6UL_OCRAM_MEM_SIZE, 677 &error_abort); 678 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_OCRAM_MEM_ADDR, 679 &s->ocram); 680 681 /* 682 * internal OCRAM (128 KB) is aliased over 512 KB 683 */ 684 memory_region_init_alias(&s->ocram_alias, OBJECT(dev), 685 "imx6ul.ocram_alias", &s->ocram, 0, 686 FSL_IMX6UL_OCRAM_ALIAS_SIZE); 687 memory_region_add_subregion(get_system_memory(), 688 FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias); 689 } 690 691 static Property fsl_imx6ul_properties[] = { 692 DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0), 693 DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1), 694 DEFINE_PROP_BOOL("fec1-phy-connected", FslIMX6ULState, phy_connected[0], 695 true), 696 DEFINE_PROP_BOOL("fec2-phy-connected", FslIMX6ULState, phy_connected[1], 697 true), 698 DEFINE_PROP_END_OF_LIST(), 699 }; 700 701 static void fsl_imx6ul_class_init(ObjectClass *oc, void *data) 702 { 703 DeviceClass *dc = DEVICE_CLASS(oc); 704 705 device_class_set_props(dc, fsl_imx6ul_properties); 706 dc->realize = fsl_imx6ul_realize; 707 dc->desc = "i.MX6UL SOC"; 708 /* Reason: Uses serial_hds and nd_table in realize() directly */ 709 dc->user_creatable = false; 710 } 711 712 static const TypeInfo fsl_imx6ul_type_info = { 713 .name = TYPE_FSL_IMX6UL, 714 .parent = TYPE_DEVICE, 715 .instance_size = sizeof(FslIMX6ULState), 716 .instance_init = fsl_imx6ul_init, 717 .class_init = fsl_imx6ul_class_init, 718 }; 719 720 static void fsl_imx6ul_register_types(void) 721 { 722 type_register_static(&fsl_imx6ul_type_info); 723 } 724 type_init(fsl_imx6ul_register_types) 725