1 /* 2 * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX6UL SOC emulation. 5 * 6 * Based on hw/arm/fsl-imx7.c 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qapi/error.h" 21 #include "hw/arm/fsl-imx6ul.h" 22 #include "hw/misc/unimp.h" 23 #include "hw/usb/imx-usb-phy.h" 24 #include "hw/boards.h" 25 #include "sysemu/sysemu.h" 26 #include "qemu/error-report.h" 27 #include "qemu/module.h" 28 29 #define NAME_SIZE 20 30 31 static void fsl_imx6ul_init(Object *obj) 32 { 33 FslIMX6ULState *s = FSL_IMX6UL(obj); 34 char name[NAME_SIZE]; 35 int i; 36 37 object_initialize_child(obj, "cpu0", &s->cpu, 38 ARM_CPU_TYPE_NAME("cortex-a7")); 39 40 /* 41 * A7MPCORE 42 */ 43 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, 44 TYPE_A15MPCORE_PRIV); 45 46 /* 47 * CCM 48 */ 49 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6UL_CCM); 50 51 /* 52 * SRC 53 */ 54 object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC); 55 56 /* 57 * GPCv2 58 */ 59 object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2); 60 61 /* 62 * SNVS 63 */ 64 object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); 65 66 /* 67 * GPR 68 */ 69 object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR); 70 71 /* 72 * GPIOs 1 to 5 73 */ 74 for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { 75 snprintf(name, NAME_SIZE, "gpio%d", i); 76 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); 77 } 78 79 /* 80 * GPT 1, 2 81 */ 82 for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { 83 snprintf(name, NAME_SIZE, "gpt%d", i); 84 object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT); 85 } 86 87 /* 88 * EPIT 1, 2 89 */ 90 for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) { 91 snprintf(name, NAME_SIZE, "epit%d", i + 1); 92 object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT); 93 } 94 95 /* 96 * eCSPI 97 */ 98 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { 99 snprintf(name, NAME_SIZE, "spi%d", i + 1); 100 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); 101 } 102 103 /* 104 * I2C 105 */ 106 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { 107 snprintf(name, NAME_SIZE, "i2c%d", i + 1); 108 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); 109 } 110 111 /* 112 * UART 113 */ 114 for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) { 115 snprintf(name, NAME_SIZE, "uart%d", i); 116 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); 117 } 118 119 /* 120 * Ethernet 121 */ 122 for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { 123 snprintf(name, NAME_SIZE, "eth%d", i); 124 object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET); 125 } 126 127 /* USB */ 128 for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { 129 snprintf(name, NAME_SIZE, "usbphy%d", i); 130 object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY); 131 } 132 for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) { 133 snprintf(name, NAME_SIZE, "usb%d", i); 134 object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); 135 } 136 137 /* 138 * SDHCI 139 */ 140 for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { 141 snprintf(name, NAME_SIZE, "usdhc%d", i); 142 object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); 143 } 144 145 /* 146 * Watchdog 147 */ 148 for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) { 149 snprintf(name, NAME_SIZE, "wdt%d", i); 150 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT); 151 } 152 } 153 154 static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) 155 { 156 MachineState *ms = MACHINE(qdev_get_machine()); 157 FslIMX6ULState *s = FSL_IMX6UL(dev); 158 int i; 159 char name[NAME_SIZE]; 160 SysBusDevice *sbd; 161 DeviceState *d; 162 163 if (ms->smp.cpus > 1) { 164 error_setg(errp, "%s: Only a single CPU is supported (%d requested)", 165 TYPE_FSL_IMX6UL, ms->smp.cpus); 166 return; 167 } 168 169 object_property_set_int(OBJECT(&s->cpu), QEMU_PSCI_CONDUIT_SMC, 170 "psci-conduit", &error_abort); 171 qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); 172 173 /* 174 * A7MPCORE 175 */ 176 object_property_set_int(OBJECT(&s->a7mpcore), 1, "num-cpu", &error_abort); 177 object_property_set_int(OBJECT(&s->a7mpcore), 178 FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL, 179 "num-irq", &error_abort); 180 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 181 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR); 182 183 sbd = SYS_BUS_DEVICE(&s->a7mpcore); 184 d = DEVICE(&s->cpu); 185 186 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ)); 187 sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ)); 188 sysbus_connect_irq(sbd, 2, qdev_get_gpio_in(d, ARM_CPU_VIRQ)); 189 sysbus_connect_irq(sbd, 3, qdev_get_gpio_in(d, ARM_CPU_VFIQ)); 190 191 /* 192 * A7MPCORE DAP 193 */ 194 create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR, 195 0x100000); 196 197 /* 198 * GPT 1, 2 199 */ 200 for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { 201 static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = { 202 FSL_IMX6UL_GPT1_ADDR, 203 FSL_IMX6UL_GPT2_ADDR, 204 }; 205 206 static const int FSL_IMX6UL_GPTn_IRQ[FSL_IMX6UL_NUM_GPTS] = { 207 FSL_IMX6UL_GPT1_IRQ, 208 FSL_IMX6UL_GPT2_IRQ, 209 }; 210 211 s->gpt[i].ccm = IMX_CCM(&s->ccm); 212 sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort); 213 214 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, 215 FSL_IMX6UL_GPTn_ADDR[i]); 216 217 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, 218 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 219 FSL_IMX6UL_GPTn_IRQ[i])); 220 } 221 222 /* 223 * EPIT 1, 2 224 */ 225 for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) { 226 static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = { 227 FSL_IMX6UL_EPIT1_ADDR, 228 FSL_IMX6UL_EPIT2_ADDR, 229 }; 230 231 static const int FSL_IMX6UL_EPITn_IRQ[FSL_IMX6UL_NUM_EPITS] = { 232 FSL_IMX6UL_EPIT1_IRQ, 233 FSL_IMX6UL_EPIT2_IRQ, 234 }; 235 236 s->epit[i].ccm = IMX_CCM(&s->ccm); 237 sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &error_abort); 238 239 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, 240 FSL_IMX6UL_EPITn_ADDR[i]); 241 242 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 243 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 244 FSL_IMX6UL_EPITn_IRQ[i])); 245 } 246 247 /* 248 * GPIO 249 */ 250 for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { 251 static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = { 252 FSL_IMX6UL_GPIO1_ADDR, 253 FSL_IMX6UL_GPIO2_ADDR, 254 FSL_IMX6UL_GPIO3_ADDR, 255 FSL_IMX6UL_GPIO4_ADDR, 256 FSL_IMX6UL_GPIO5_ADDR, 257 }; 258 259 static const int FSL_IMX6UL_GPIOn_LOW_IRQ[FSL_IMX6UL_NUM_GPIOS] = { 260 FSL_IMX6UL_GPIO1_LOW_IRQ, 261 FSL_IMX6UL_GPIO2_LOW_IRQ, 262 FSL_IMX6UL_GPIO3_LOW_IRQ, 263 FSL_IMX6UL_GPIO4_LOW_IRQ, 264 FSL_IMX6UL_GPIO5_LOW_IRQ, 265 }; 266 267 static const int FSL_IMX6UL_GPIOn_HIGH_IRQ[FSL_IMX6UL_NUM_GPIOS] = { 268 FSL_IMX6UL_GPIO1_HIGH_IRQ, 269 FSL_IMX6UL_GPIO2_HIGH_IRQ, 270 FSL_IMX6UL_GPIO3_HIGH_IRQ, 271 FSL_IMX6UL_GPIO4_HIGH_IRQ, 272 FSL_IMX6UL_GPIO5_HIGH_IRQ, 273 }; 274 275 sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort); 276 277 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, 278 FSL_IMX6UL_GPIOn_ADDR[i]); 279 280 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 281 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 282 FSL_IMX6UL_GPIOn_LOW_IRQ[i])); 283 284 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, 285 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 286 FSL_IMX6UL_GPIOn_HIGH_IRQ[i])); 287 } 288 289 /* 290 * IOMUXC and IOMUXC_GPR 291 */ 292 for (i = 0; i < 1; i++) { 293 static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = { 294 FSL_IMX6UL_IOMUXC_ADDR, 295 FSL_IMX6UL_IOMUXC_GPR_ADDR, 296 }; 297 298 snprintf(name, NAME_SIZE, "iomuxc%d", i); 299 create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000); 300 } 301 302 /* 303 * CCM 304 */ 305 sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_abort); 306 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6UL_CCM_ADDR); 307 308 /* 309 * SRC 310 */ 311 sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort); 312 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6UL_SRC_ADDR); 313 314 /* 315 * GPCv2 316 */ 317 sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort); 318 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR); 319 320 /* Initialize all ECSPI */ 321 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { 322 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { 323 FSL_IMX6UL_ECSPI1_ADDR, 324 FSL_IMX6UL_ECSPI2_ADDR, 325 FSL_IMX6UL_ECSPI3_ADDR, 326 FSL_IMX6UL_ECSPI4_ADDR, 327 }; 328 329 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { 330 FSL_IMX6UL_ECSPI1_IRQ, 331 FSL_IMX6UL_ECSPI2_IRQ, 332 FSL_IMX6UL_ECSPI3_IRQ, 333 FSL_IMX6UL_ECSPI4_IRQ, 334 }; 335 336 /* Initialize the SPI */ 337 sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &error_abort); 338 339 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 340 FSL_IMX6UL_SPIn_ADDR[i]); 341 342 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 343 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 344 FSL_IMX6UL_SPIn_IRQ[i])); 345 } 346 347 /* 348 * I2C 349 */ 350 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { 351 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { 352 FSL_IMX6UL_I2C1_ADDR, 353 FSL_IMX6UL_I2C2_ADDR, 354 FSL_IMX6UL_I2C3_ADDR, 355 FSL_IMX6UL_I2C4_ADDR, 356 }; 357 358 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { 359 FSL_IMX6UL_I2C1_IRQ, 360 FSL_IMX6UL_I2C2_IRQ, 361 FSL_IMX6UL_I2C3_IRQ, 362 FSL_IMX6UL_I2C4_IRQ, 363 }; 364 365 sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_abort); 366 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]); 367 368 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 369 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 370 FSL_IMX6UL_I2Cn_IRQ[i])); 371 } 372 373 /* 374 * UART 375 */ 376 for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) { 377 static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = { 378 FSL_IMX6UL_UART1_ADDR, 379 FSL_IMX6UL_UART2_ADDR, 380 FSL_IMX6UL_UART3_ADDR, 381 FSL_IMX6UL_UART4_ADDR, 382 FSL_IMX6UL_UART5_ADDR, 383 FSL_IMX6UL_UART6_ADDR, 384 FSL_IMX6UL_UART7_ADDR, 385 FSL_IMX6UL_UART8_ADDR, 386 }; 387 388 static const int FSL_IMX6UL_UARTn_IRQ[FSL_IMX6UL_NUM_UARTS] = { 389 FSL_IMX6UL_UART1_IRQ, 390 FSL_IMX6UL_UART2_IRQ, 391 FSL_IMX6UL_UART3_IRQ, 392 FSL_IMX6UL_UART4_IRQ, 393 FSL_IMX6UL_UART5_IRQ, 394 FSL_IMX6UL_UART6_IRQ, 395 FSL_IMX6UL_UART7_IRQ, 396 FSL_IMX6UL_UART8_IRQ, 397 }; 398 399 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 400 401 sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &error_abort); 402 403 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, 404 FSL_IMX6UL_UARTn_ADDR[i]); 405 406 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 407 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 408 FSL_IMX6UL_UARTn_IRQ[i])); 409 } 410 411 /* 412 * Ethernet 413 */ 414 for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { 415 static const hwaddr FSL_IMX6UL_ENETn_ADDR[FSL_IMX6UL_NUM_ETHS] = { 416 FSL_IMX6UL_ENET1_ADDR, 417 FSL_IMX6UL_ENET2_ADDR, 418 }; 419 420 static const int FSL_IMX6UL_ENETn_IRQ[FSL_IMX6UL_NUM_ETHS] = { 421 FSL_IMX6UL_ENET1_IRQ, 422 FSL_IMX6UL_ENET2_IRQ, 423 }; 424 425 static const int FSL_IMX6UL_ENETn_TIMER_IRQ[FSL_IMX6UL_NUM_ETHS] = { 426 FSL_IMX6UL_ENET1_TIMER_IRQ, 427 FSL_IMX6UL_ENET2_TIMER_IRQ, 428 }; 429 430 object_property_set_uint(OBJECT(&s->eth[i]), 431 s->phy_num[i], 432 "phy-num", &error_abort); 433 object_property_set_uint(OBJECT(&s->eth[i]), 434 FSL_IMX6UL_ETH_NUM_TX_RINGS, 435 "tx-ring-num", &error_abort); 436 qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]); 437 sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort); 438 439 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, 440 FSL_IMX6UL_ENETn_ADDR[i]); 441 442 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, 443 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 444 FSL_IMX6UL_ENETn_IRQ[i])); 445 446 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, 447 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 448 FSL_IMX6UL_ENETn_TIMER_IRQ[i])); 449 } 450 451 /* USB */ 452 for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { 453 sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort); 454 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0, 455 FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000); 456 } 457 458 for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) { 459 static const int FSL_IMX6UL_USBn_IRQ[] = { 460 FSL_IMX6UL_USB1_IRQ, 461 FSL_IMX6UL_USB2_IRQ, 462 }; 463 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); 464 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, 465 FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200); 466 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, 467 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 468 FSL_IMX6UL_USBn_IRQ[i])); 469 } 470 471 /* 472 * USDHC 473 */ 474 for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { 475 static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = { 476 FSL_IMX6UL_USDHC1_ADDR, 477 FSL_IMX6UL_USDHC2_ADDR, 478 }; 479 480 static const int FSL_IMX6UL_USDHCn_IRQ[FSL_IMX6UL_NUM_USDHCS] = { 481 FSL_IMX6UL_USDHC1_IRQ, 482 FSL_IMX6UL_USDHC2_IRQ, 483 }; 484 485 object_property_set_uint(OBJECT(&s->usdhc[i]), SDHCI_VENDOR_IMX, 486 "vendor", &error_abort); 487 sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort); 488 489 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, 490 FSL_IMX6UL_USDHCn_ADDR[i]); 491 492 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, 493 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 494 FSL_IMX6UL_USDHCn_IRQ[i])); 495 } 496 497 /* 498 * SNVS 499 */ 500 sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort); 501 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR); 502 503 /* 504 * Watchdog 505 */ 506 for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) { 507 static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = { 508 FSL_IMX6UL_WDOG1_ADDR, 509 FSL_IMX6UL_WDOG2_ADDR, 510 FSL_IMX6UL_WDOG3_ADDR, 511 }; 512 static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = { 513 FSL_IMX6UL_WDOG1_IRQ, 514 FSL_IMX6UL_WDOG2_IRQ, 515 FSL_IMX6UL_WDOG3_IRQ, 516 }; 517 518 object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support", 519 &error_abort); 520 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); 521 522 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 523 FSL_IMX6UL_WDOGn_ADDR[i]); 524 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, 525 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 526 FSL_IMX6UL_WDOGn_IRQ[i])); 527 } 528 529 /* 530 * GPR 531 */ 532 sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort); 533 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR); 534 535 /* 536 * SDMA 537 */ 538 create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000); 539 540 /* 541 * PWM 542 */ 543 create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000); 544 create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000); 545 create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000); 546 create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000); 547 548 /* 549 * CAN 550 */ 551 create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000); 552 create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000); 553 554 /* 555 * APHB_DMA 556 */ 557 create_unimplemented_device("aphb_dma", FSL_IMX6UL_APBH_DMA_ADDR, 558 FSL_IMX6UL_APBH_DMA_SIZE); 559 560 /* 561 * ADCs 562 */ 563 for (i = 0; i < FSL_IMX6UL_NUM_ADCS; i++) { 564 static const hwaddr FSL_IMX6UL_ADCn_ADDR[FSL_IMX6UL_NUM_ADCS] = { 565 FSL_IMX6UL_ADC1_ADDR, 566 FSL_IMX6UL_ADC2_ADDR, 567 }; 568 569 snprintf(name, NAME_SIZE, "adc%d", i); 570 create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000); 571 } 572 573 /* 574 * LCD 575 */ 576 create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000); 577 578 /* 579 * ROM memory 580 */ 581 memory_region_init_rom(&s->rom, OBJECT(dev), "imx6ul.rom", 582 FSL_IMX6UL_ROM_SIZE, &error_abort); 583 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_ROM_ADDR, 584 &s->rom); 585 586 /* 587 * CAAM memory 588 */ 589 memory_region_init_rom(&s->caam, OBJECT(dev), "imx6ul.caam", 590 FSL_IMX6UL_CAAM_MEM_SIZE, &error_abort); 591 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_CAAM_MEM_ADDR, 592 &s->caam); 593 594 /* 595 * OCRAM memory 596 */ 597 memory_region_init_ram(&s->ocram, NULL, "imx6ul.ocram", 598 FSL_IMX6UL_OCRAM_MEM_SIZE, 599 &error_abort); 600 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_OCRAM_MEM_ADDR, 601 &s->ocram); 602 603 /* 604 * internal OCRAM (128 KB) is aliased over 512 KB 605 */ 606 memory_region_init_alias(&s->ocram_alias, OBJECT(dev), 607 "imx6ul.ocram_alias", &s->ocram, 0, 608 FSL_IMX6UL_OCRAM_ALIAS_SIZE); 609 memory_region_add_subregion(get_system_memory(), 610 FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias); 611 } 612 613 static Property fsl_imx6ul_properties[] = { 614 DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0), 615 DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1), 616 DEFINE_PROP_END_OF_LIST(), 617 }; 618 619 static void fsl_imx6ul_class_init(ObjectClass *oc, void *data) 620 { 621 DeviceClass *dc = DEVICE_CLASS(oc); 622 623 device_class_set_props(dc, fsl_imx6ul_properties); 624 dc->realize = fsl_imx6ul_realize; 625 dc->desc = "i.MX6UL SOC"; 626 /* Reason: Uses serial_hds and nd_table in realize() directly */ 627 dc->user_creatable = false; 628 } 629 630 static const TypeInfo fsl_imx6ul_type_info = { 631 .name = TYPE_FSL_IMX6UL, 632 .parent = TYPE_DEVICE, 633 .instance_size = sizeof(FslIMX6ULState), 634 .instance_init = fsl_imx6ul_init, 635 .class_init = fsl_imx6ul_class_init, 636 }; 637 638 static void fsl_imx6ul_register_types(void) 639 { 640 type_register_static(&fsl_imx6ul_type_info); 641 } 642 type_init(fsl_imx6ul_register_types) 643