1 /* 2 * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX6UL SOC emulation. 5 * 6 * Based on hw/arm/fsl-imx7.c 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qapi/error.h" 21 #include "hw/arm/fsl-imx6ul.h" 22 #include "hw/misc/unimp.h" 23 #include "hw/usb/imx-usb-phy.h" 24 #include "hw/boards.h" 25 #include "sysemu/sysemu.h" 26 #include "qemu/error-report.h" 27 #include "qemu/module.h" 28 29 #define NAME_SIZE 20 30 31 static void fsl_imx6ul_init(Object *obj) 32 { 33 FslIMX6ULState *s = FSL_IMX6UL(obj); 34 char name[NAME_SIZE]; 35 int i; 36 37 object_initialize_child(obj, "cpu0", &s->cpu, 38 ARM_CPU_TYPE_NAME("cortex-a7")); 39 40 /* 41 * A7MPCORE 42 */ 43 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, 44 TYPE_A15MPCORE_PRIV); 45 46 /* 47 * CCM 48 */ 49 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6UL_CCM); 50 51 /* 52 * SRC 53 */ 54 object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC); 55 56 /* 57 * GPCv2 58 */ 59 object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2); 60 61 /* 62 * SNVS 63 */ 64 object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); 65 66 /* 67 * GPR 68 */ 69 object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR); 70 71 /* 72 * GPIOs 1 to 5 73 */ 74 for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { 75 snprintf(name, NAME_SIZE, "gpio%d", i); 76 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); 77 } 78 79 /* 80 * GPT 1, 2 81 */ 82 for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { 83 snprintf(name, NAME_SIZE, "gpt%d", i); 84 object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT); 85 } 86 87 /* 88 * EPIT 1, 2 89 */ 90 for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) { 91 snprintf(name, NAME_SIZE, "epit%d", i + 1); 92 object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT); 93 } 94 95 /* 96 * eCSPI 97 */ 98 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { 99 snprintf(name, NAME_SIZE, "spi%d", i + 1); 100 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); 101 } 102 103 /* 104 * I2C 105 */ 106 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { 107 snprintf(name, NAME_SIZE, "i2c%d", i + 1); 108 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); 109 } 110 111 /* 112 * UART 113 */ 114 for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) { 115 snprintf(name, NAME_SIZE, "uart%d", i); 116 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); 117 } 118 119 /* 120 * Ethernet 121 */ 122 for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { 123 snprintf(name, NAME_SIZE, "eth%d", i); 124 object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET); 125 } 126 127 /* USB */ 128 for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { 129 snprintf(name, NAME_SIZE, "usbphy%d", i); 130 object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY); 131 } 132 for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) { 133 snprintf(name, NAME_SIZE, "usb%d", i); 134 object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); 135 } 136 137 /* 138 * SDHCI 139 */ 140 for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { 141 snprintf(name, NAME_SIZE, "usdhc%d", i); 142 object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); 143 } 144 145 /* 146 * Watchdog 147 */ 148 for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) { 149 snprintf(name, NAME_SIZE, "wdt%d", i); 150 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT); 151 } 152 } 153 154 static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) 155 { 156 MachineState *ms = MACHINE(qdev_get_machine()); 157 FslIMX6ULState *s = FSL_IMX6UL(dev); 158 int i; 159 char name[NAME_SIZE]; 160 SysBusDevice *sbd; 161 DeviceState *d; 162 163 if (ms->smp.cpus > 1) { 164 error_setg(errp, "%s: Only a single CPU is supported (%d requested)", 165 TYPE_FSL_IMX6UL, ms->smp.cpus); 166 return; 167 } 168 169 object_property_set_int(OBJECT(&s->cpu), QEMU_PSCI_CONDUIT_SMC, 170 "psci-conduit", &error_abort); 171 object_property_set_bool(OBJECT(&s->cpu), true, 172 "realized", &error_abort); 173 174 /* 175 * A7MPCORE 176 */ 177 object_property_set_int(OBJECT(&s->a7mpcore), 1, "num-cpu", &error_abort); 178 object_property_set_int(OBJECT(&s->a7mpcore), 179 FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL, 180 "num-irq", &error_abort); 181 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 182 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR); 183 184 sbd = SYS_BUS_DEVICE(&s->a7mpcore); 185 d = DEVICE(&s->cpu); 186 187 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ)); 188 sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ)); 189 sysbus_connect_irq(sbd, 2, qdev_get_gpio_in(d, ARM_CPU_VIRQ)); 190 sysbus_connect_irq(sbd, 3, qdev_get_gpio_in(d, ARM_CPU_VFIQ)); 191 192 /* 193 * A7MPCORE DAP 194 */ 195 create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR, 196 0x100000); 197 198 /* 199 * GPT 1, 2 200 */ 201 for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { 202 static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = { 203 FSL_IMX6UL_GPT1_ADDR, 204 FSL_IMX6UL_GPT2_ADDR, 205 }; 206 207 static const int FSL_IMX6UL_GPTn_IRQ[FSL_IMX6UL_NUM_GPTS] = { 208 FSL_IMX6UL_GPT1_IRQ, 209 FSL_IMX6UL_GPT2_IRQ, 210 }; 211 212 s->gpt[i].ccm = IMX_CCM(&s->ccm); 213 sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort); 214 215 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, 216 FSL_IMX6UL_GPTn_ADDR[i]); 217 218 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, 219 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 220 FSL_IMX6UL_GPTn_IRQ[i])); 221 } 222 223 /* 224 * EPIT 1, 2 225 */ 226 for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) { 227 static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = { 228 FSL_IMX6UL_EPIT1_ADDR, 229 FSL_IMX6UL_EPIT2_ADDR, 230 }; 231 232 static const int FSL_IMX6UL_EPITn_IRQ[FSL_IMX6UL_NUM_EPITS] = { 233 FSL_IMX6UL_EPIT1_IRQ, 234 FSL_IMX6UL_EPIT2_IRQ, 235 }; 236 237 s->epit[i].ccm = IMX_CCM(&s->ccm); 238 sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &error_abort); 239 240 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, 241 FSL_IMX6UL_EPITn_ADDR[i]); 242 243 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 244 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 245 FSL_IMX6UL_EPITn_IRQ[i])); 246 } 247 248 /* 249 * GPIO 250 */ 251 for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { 252 static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = { 253 FSL_IMX6UL_GPIO1_ADDR, 254 FSL_IMX6UL_GPIO2_ADDR, 255 FSL_IMX6UL_GPIO3_ADDR, 256 FSL_IMX6UL_GPIO4_ADDR, 257 FSL_IMX6UL_GPIO5_ADDR, 258 }; 259 260 static const int FSL_IMX6UL_GPIOn_LOW_IRQ[FSL_IMX6UL_NUM_GPIOS] = { 261 FSL_IMX6UL_GPIO1_LOW_IRQ, 262 FSL_IMX6UL_GPIO2_LOW_IRQ, 263 FSL_IMX6UL_GPIO3_LOW_IRQ, 264 FSL_IMX6UL_GPIO4_LOW_IRQ, 265 FSL_IMX6UL_GPIO5_LOW_IRQ, 266 }; 267 268 static const int FSL_IMX6UL_GPIOn_HIGH_IRQ[FSL_IMX6UL_NUM_GPIOS] = { 269 FSL_IMX6UL_GPIO1_HIGH_IRQ, 270 FSL_IMX6UL_GPIO2_HIGH_IRQ, 271 FSL_IMX6UL_GPIO3_HIGH_IRQ, 272 FSL_IMX6UL_GPIO4_HIGH_IRQ, 273 FSL_IMX6UL_GPIO5_HIGH_IRQ, 274 }; 275 276 sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort); 277 278 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, 279 FSL_IMX6UL_GPIOn_ADDR[i]); 280 281 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 282 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 283 FSL_IMX6UL_GPIOn_LOW_IRQ[i])); 284 285 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, 286 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 287 FSL_IMX6UL_GPIOn_HIGH_IRQ[i])); 288 } 289 290 /* 291 * IOMUXC and IOMUXC_GPR 292 */ 293 for (i = 0; i < 1; i++) { 294 static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = { 295 FSL_IMX6UL_IOMUXC_ADDR, 296 FSL_IMX6UL_IOMUXC_GPR_ADDR, 297 }; 298 299 snprintf(name, NAME_SIZE, "iomuxc%d", i); 300 create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000); 301 } 302 303 /* 304 * CCM 305 */ 306 sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_abort); 307 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6UL_CCM_ADDR); 308 309 /* 310 * SRC 311 */ 312 sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort); 313 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6UL_SRC_ADDR); 314 315 /* 316 * GPCv2 317 */ 318 sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort); 319 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR); 320 321 /* Initialize all ECSPI */ 322 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { 323 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { 324 FSL_IMX6UL_ECSPI1_ADDR, 325 FSL_IMX6UL_ECSPI2_ADDR, 326 FSL_IMX6UL_ECSPI3_ADDR, 327 FSL_IMX6UL_ECSPI4_ADDR, 328 }; 329 330 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { 331 FSL_IMX6UL_ECSPI1_IRQ, 332 FSL_IMX6UL_ECSPI2_IRQ, 333 FSL_IMX6UL_ECSPI3_IRQ, 334 FSL_IMX6UL_ECSPI4_IRQ, 335 }; 336 337 /* Initialize the SPI */ 338 sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &error_abort); 339 340 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 341 FSL_IMX6UL_SPIn_ADDR[i]); 342 343 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 344 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 345 FSL_IMX6UL_SPIn_IRQ[i])); 346 } 347 348 /* 349 * I2C 350 */ 351 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { 352 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { 353 FSL_IMX6UL_I2C1_ADDR, 354 FSL_IMX6UL_I2C2_ADDR, 355 FSL_IMX6UL_I2C3_ADDR, 356 FSL_IMX6UL_I2C4_ADDR, 357 }; 358 359 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { 360 FSL_IMX6UL_I2C1_IRQ, 361 FSL_IMX6UL_I2C2_IRQ, 362 FSL_IMX6UL_I2C3_IRQ, 363 FSL_IMX6UL_I2C4_IRQ, 364 }; 365 366 sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_abort); 367 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]); 368 369 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 370 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 371 FSL_IMX6UL_I2Cn_IRQ[i])); 372 } 373 374 /* 375 * UART 376 */ 377 for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) { 378 static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = { 379 FSL_IMX6UL_UART1_ADDR, 380 FSL_IMX6UL_UART2_ADDR, 381 FSL_IMX6UL_UART3_ADDR, 382 FSL_IMX6UL_UART4_ADDR, 383 FSL_IMX6UL_UART5_ADDR, 384 FSL_IMX6UL_UART6_ADDR, 385 FSL_IMX6UL_UART7_ADDR, 386 FSL_IMX6UL_UART8_ADDR, 387 }; 388 389 static const int FSL_IMX6UL_UARTn_IRQ[FSL_IMX6UL_NUM_UARTS] = { 390 FSL_IMX6UL_UART1_IRQ, 391 FSL_IMX6UL_UART2_IRQ, 392 FSL_IMX6UL_UART3_IRQ, 393 FSL_IMX6UL_UART4_IRQ, 394 FSL_IMX6UL_UART5_IRQ, 395 FSL_IMX6UL_UART6_IRQ, 396 FSL_IMX6UL_UART7_IRQ, 397 FSL_IMX6UL_UART8_IRQ, 398 }; 399 400 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 401 402 sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &error_abort); 403 404 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, 405 FSL_IMX6UL_UARTn_ADDR[i]); 406 407 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 408 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 409 FSL_IMX6UL_UARTn_IRQ[i])); 410 } 411 412 /* 413 * Ethernet 414 */ 415 for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { 416 static const hwaddr FSL_IMX6UL_ENETn_ADDR[FSL_IMX6UL_NUM_ETHS] = { 417 FSL_IMX6UL_ENET1_ADDR, 418 FSL_IMX6UL_ENET2_ADDR, 419 }; 420 421 static const int FSL_IMX6UL_ENETn_IRQ[FSL_IMX6UL_NUM_ETHS] = { 422 FSL_IMX6UL_ENET1_IRQ, 423 FSL_IMX6UL_ENET2_IRQ, 424 }; 425 426 static const int FSL_IMX6UL_ENETn_TIMER_IRQ[FSL_IMX6UL_NUM_ETHS] = { 427 FSL_IMX6UL_ENET1_TIMER_IRQ, 428 FSL_IMX6UL_ENET2_TIMER_IRQ, 429 }; 430 431 object_property_set_uint(OBJECT(&s->eth[i]), 432 FSL_IMX6UL_ETH_NUM_TX_RINGS, 433 "tx-ring-num", &error_abort); 434 qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]); 435 sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort); 436 437 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, 438 FSL_IMX6UL_ENETn_ADDR[i]); 439 440 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, 441 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 442 FSL_IMX6UL_ENETn_IRQ[i])); 443 444 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, 445 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 446 FSL_IMX6UL_ENETn_TIMER_IRQ[i])); 447 } 448 449 /* USB */ 450 for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { 451 sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort); 452 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0, 453 FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000); 454 } 455 456 for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) { 457 static const int FSL_IMX6UL_USBn_IRQ[] = { 458 FSL_IMX6UL_USB1_IRQ, 459 FSL_IMX6UL_USB2_IRQ, 460 }; 461 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); 462 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, 463 FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200); 464 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, 465 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 466 FSL_IMX6UL_USBn_IRQ[i])); 467 } 468 469 /* 470 * USDHC 471 */ 472 for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { 473 static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = { 474 FSL_IMX6UL_USDHC1_ADDR, 475 FSL_IMX6UL_USDHC2_ADDR, 476 }; 477 478 static const int FSL_IMX6UL_USDHCn_IRQ[FSL_IMX6UL_NUM_USDHCS] = { 479 FSL_IMX6UL_USDHC1_IRQ, 480 FSL_IMX6UL_USDHC2_IRQ, 481 }; 482 483 sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort); 484 485 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, 486 FSL_IMX6UL_USDHCn_ADDR[i]); 487 488 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, 489 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 490 FSL_IMX6UL_USDHCn_IRQ[i])); 491 } 492 493 /* 494 * SNVS 495 */ 496 sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort); 497 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR); 498 499 /* 500 * Watchdog 501 */ 502 for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) { 503 static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = { 504 FSL_IMX6UL_WDOG1_ADDR, 505 FSL_IMX6UL_WDOG2_ADDR, 506 FSL_IMX6UL_WDOG3_ADDR, 507 }; 508 static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = { 509 FSL_IMX6UL_WDOG1_IRQ, 510 FSL_IMX6UL_WDOG2_IRQ, 511 FSL_IMX6UL_WDOG3_IRQ, 512 }; 513 514 object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support", 515 &error_abort); 516 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); 517 518 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 519 FSL_IMX6UL_WDOGn_ADDR[i]); 520 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, 521 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 522 FSL_IMX6UL_WDOGn_IRQ[i])); 523 } 524 525 /* 526 * GPR 527 */ 528 sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort); 529 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR); 530 531 /* 532 * SDMA 533 */ 534 create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000); 535 536 /* 537 * PWM 538 */ 539 create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000); 540 create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000); 541 create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000); 542 create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000); 543 544 /* 545 * CAN 546 */ 547 create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000); 548 create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000); 549 550 /* 551 * APHB_DMA 552 */ 553 create_unimplemented_device("aphb_dma", FSL_IMX6UL_APBH_DMA_ADDR, 554 FSL_IMX6UL_APBH_DMA_SIZE); 555 556 /* 557 * ADCs 558 */ 559 for (i = 0; i < FSL_IMX6UL_NUM_ADCS; i++) { 560 static const hwaddr FSL_IMX6UL_ADCn_ADDR[FSL_IMX6UL_NUM_ADCS] = { 561 FSL_IMX6UL_ADC1_ADDR, 562 FSL_IMX6UL_ADC2_ADDR, 563 }; 564 565 snprintf(name, NAME_SIZE, "adc%d", i); 566 create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000); 567 } 568 569 /* 570 * LCD 571 */ 572 create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000); 573 574 /* 575 * ROM memory 576 */ 577 memory_region_init_rom(&s->rom, OBJECT(dev), "imx6ul.rom", 578 FSL_IMX6UL_ROM_SIZE, &error_abort); 579 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_ROM_ADDR, 580 &s->rom); 581 582 /* 583 * CAAM memory 584 */ 585 memory_region_init_rom(&s->caam, OBJECT(dev), "imx6ul.caam", 586 FSL_IMX6UL_CAAM_MEM_SIZE, &error_abort); 587 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_CAAM_MEM_ADDR, 588 &s->caam); 589 590 /* 591 * OCRAM memory 592 */ 593 memory_region_init_ram(&s->ocram, NULL, "imx6ul.ocram", 594 FSL_IMX6UL_OCRAM_MEM_SIZE, 595 &error_abort); 596 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_OCRAM_MEM_ADDR, 597 &s->ocram); 598 599 /* 600 * internal OCRAM (128 KB) is aliased over 512 KB 601 */ 602 memory_region_init_alias(&s->ocram_alias, OBJECT(dev), 603 "imx6ul.ocram_alias", &s->ocram, 0, 604 FSL_IMX6UL_OCRAM_ALIAS_SIZE); 605 memory_region_add_subregion(get_system_memory(), 606 FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias); 607 } 608 609 static void fsl_imx6ul_class_init(ObjectClass *oc, void *data) 610 { 611 DeviceClass *dc = DEVICE_CLASS(oc); 612 613 dc->realize = fsl_imx6ul_realize; 614 dc->desc = "i.MX6UL SOC"; 615 /* Reason: Uses serial_hds and nd_table in realize() directly */ 616 dc->user_creatable = false; 617 } 618 619 static const TypeInfo fsl_imx6ul_type_info = { 620 .name = TYPE_FSL_IMX6UL, 621 .parent = TYPE_DEVICE, 622 .instance_size = sizeof(FslIMX6ULState), 623 .instance_init = fsl_imx6ul_init, 624 .class_init = fsl_imx6ul_class_init, 625 }; 626 627 static void fsl_imx6ul_register_types(void) 628 { 629 type_register_static(&fsl_imx6ul_type_info); 630 } 631 type_init(fsl_imx6ul_register_types) 632