1 /* 2 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX6 SOC emulation. 5 * 6 * Based on hw/arm/fsl-imx31.c 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "hw/arm/fsl-imx6.h" 25 #include "hw/usb/imx-usb-phy.h" 26 #include "hw/boards.h" 27 #include "hw/qdev-properties.h" 28 #include "sysemu/sysemu.h" 29 #include "chardev/char.h" 30 #include "qemu/error-report.h" 31 #include "qemu/module.h" 32 33 #define IMX6_ESDHC_CAPABILITIES 0x057834b4 34 35 #define NAME_SIZE 20 36 37 static void fsl_imx6_init(Object *obj) 38 { 39 MachineState *ms = MACHINE(qdev_get_machine()); 40 FslIMX6State *s = FSL_IMX6(obj); 41 char name[NAME_SIZE]; 42 int i; 43 44 for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) { 45 snprintf(name, NAME_SIZE, "cpu%d", i); 46 object_initialize_child(obj, name, &s->cpu[i], 47 ARM_CPU_TYPE_NAME("cortex-a9")); 48 } 49 50 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); 51 52 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6_CCM); 53 54 object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC); 55 56 object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); 57 58 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { 59 snprintf(name, NAME_SIZE, "uart%d", i + 1); 60 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); 61 } 62 63 object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX6_GPT); 64 65 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { 66 snprintf(name, NAME_SIZE, "epit%d", i + 1); 67 object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT); 68 } 69 70 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { 71 snprintf(name, NAME_SIZE, "i2c%d", i + 1); 72 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); 73 } 74 75 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { 76 snprintf(name, NAME_SIZE, "gpio%d", i + 1); 77 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); 78 } 79 80 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { 81 snprintf(name, NAME_SIZE, "sdhc%d", i + 1); 82 object_initialize_child(obj, name, &s->esdhc[i], TYPE_IMX_USDHC); 83 } 84 85 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) { 86 snprintf(name, NAME_SIZE, "usbphy%d", i); 87 object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY); 88 } 89 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) { 90 snprintf(name, NAME_SIZE, "usb%d", i); 91 object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); 92 } 93 94 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { 95 snprintf(name, NAME_SIZE, "spi%d", i + 1); 96 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); 97 } 98 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) { 99 snprintf(name, NAME_SIZE, "wdt%d", i); 100 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT); 101 } 102 103 104 object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET); 105 } 106 107 static void fsl_imx6_realize(DeviceState *dev, Error **errp) 108 { 109 MachineState *ms = MACHINE(qdev_get_machine()); 110 FslIMX6State *s = FSL_IMX6(dev); 111 uint16_t i; 112 unsigned int smp_cpus = ms->smp.cpus; 113 114 if (smp_cpus > FSL_IMX6_NUM_CPUS) { 115 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", 116 TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus); 117 return; 118 } 119 120 for (i = 0; i < smp_cpus; i++) { 121 122 /* On uniprocessor, the CBAR is set to 0 */ 123 if (smp_cpus > 1) { 124 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 125 FSL_IMX6_A9MPCORE_ADDR, &error_abort); 126 } 127 128 /* All CPU but CPU 0 start in power off mode */ 129 if (i) { 130 object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-off", 131 true, &error_abort); 132 } 133 134 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 135 return; 136 } 137 } 138 139 object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", smp_cpus, 140 &error_abort); 141 142 object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", 143 FSL_IMX6_MAX_IRQ + GIC_INTERNAL, &error_abort); 144 145 if (!sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), errp)) { 146 return; 147 } 148 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR); 149 150 for (i = 0; i < smp_cpus; i++) { 151 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, 152 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); 153 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus, 154 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); 155 } 156 157 /* L2 cache controller */ 158 sysbus_create_simple("l2x0", FSL_IMX6_PL310_ADDR, NULL); 159 160 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) { 161 return; 162 } 163 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR); 164 165 if (!sysbus_realize(SYS_BUS_DEVICE(&s->src), errp)) { 166 return; 167 } 168 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR); 169 170 /* Initialize all UARTs */ 171 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { 172 static const struct { 173 hwaddr addr; 174 unsigned int irq; 175 } serial_table[FSL_IMX6_NUM_UARTS] = { 176 { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ }, 177 { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ }, 178 { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ }, 179 { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ }, 180 { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ }, 181 }; 182 183 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 184 185 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { 186 return; 187 } 188 189 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 190 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 191 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 192 serial_table[i].irq)); 193 } 194 195 s->gpt.ccm = IMX_CCM(&s->ccm); 196 197 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), errp)) { 198 return; 199 } 200 201 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR); 202 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, 203 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 204 FSL_IMX6_GPT_IRQ)); 205 206 /* Initialize all EPIT timers */ 207 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { 208 static const struct { 209 hwaddr addr; 210 unsigned int irq; 211 } epit_table[FSL_IMX6_NUM_EPITS] = { 212 { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ }, 213 { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ }, 214 }; 215 216 s->epit[i].ccm = IMX_CCM(&s->ccm); 217 218 if (!sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), errp)) { 219 return; 220 } 221 222 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 223 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 224 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 225 epit_table[i].irq)); 226 } 227 228 /* Initialize all I2C */ 229 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { 230 static const struct { 231 hwaddr addr; 232 unsigned int irq; 233 } i2c_table[FSL_IMX6_NUM_I2CS] = { 234 { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ }, 235 { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ }, 236 { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ } 237 }; 238 239 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) { 240 return; 241 } 242 243 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 244 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 245 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 246 i2c_table[i].irq)); 247 } 248 249 /* Initialize all GPIOs */ 250 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { 251 static const struct { 252 hwaddr addr; 253 unsigned int irq_low; 254 unsigned int irq_high; 255 } gpio_table[FSL_IMX6_NUM_GPIOS] = { 256 { 257 FSL_IMX6_GPIO1_ADDR, 258 FSL_IMX6_GPIO1_LOW_IRQ, 259 FSL_IMX6_GPIO1_HIGH_IRQ 260 }, 261 { 262 FSL_IMX6_GPIO2_ADDR, 263 FSL_IMX6_GPIO2_LOW_IRQ, 264 FSL_IMX6_GPIO2_HIGH_IRQ 265 }, 266 { 267 FSL_IMX6_GPIO3_ADDR, 268 FSL_IMX6_GPIO3_LOW_IRQ, 269 FSL_IMX6_GPIO3_HIGH_IRQ 270 }, 271 { 272 FSL_IMX6_GPIO4_ADDR, 273 FSL_IMX6_GPIO4_LOW_IRQ, 274 FSL_IMX6_GPIO4_HIGH_IRQ 275 }, 276 { 277 FSL_IMX6_GPIO5_ADDR, 278 FSL_IMX6_GPIO5_LOW_IRQ, 279 FSL_IMX6_GPIO5_HIGH_IRQ 280 }, 281 { 282 FSL_IMX6_GPIO6_ADDR, 283 FSL_IMX6_GPIO6_LOW_IRQ, 284 FSL_IMX6_GPIO6_HIGH_IRQ 285 }, 286 { 287 FSL_IMX6_GPIO7_ADDR, 288 FSL_IMX6_GPIO7_LOW_IRQ, 289 FSL_IMX6_GPIO7_HIGH_IRQ 290 }, 291 }; 292 293 object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true, 294 &error_abort); 295 object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq", 296 true, &error_abort); 297 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) { 298 return; 299 } 300 301 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); 302 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 303 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 304 gpio_table[i].irq_low)); 305 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, 306 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 307 gpio_table[i].irq_high)); 308 } 309 310 /* Initialize all SDHC */ 311 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { 312 static const struct { 313 hwaddr addr; 314 unsigned int irq; 315 } esdhc_table[FSL_IMX6_NUM_ESDHCS] = { 316 { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ }, 317 { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ }, 318 { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ }, 319 { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ }, 320 }; 321 322 /* UHS-I SDIO3.0 SDR104 1.8V ADMA */ 323 object_property_set_uint(OBJECT(&s->esdhc[i]), "sd-spec-version", 3, 324 &error_abort); 325 object_property_set_uint(OBJECT(&s->esdhc[i]), "capareg", 326 IMX6_ESDHC_CAPABILITIES, &error_abort); 327 object_property_set_uint(OBJECT(&s->esdhc[i]), "vendor", 328 SDHCI_VENDOR_IMX, &error_abort); 329 if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), errp)) { 330 return; 331 } 332 sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); 333 sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, 334 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 335 esdhc_table[i].irq)); 336 } 337 338 /* USB */ 339 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) { 340 sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort); 341 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0, 342 FSL_IMX6_USBPHY1_ADDR + i * 0x1000); 343 } 344 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) { 345 static const int FSL_IMX6_USBn_IRQ[] = { 346 FSL_IMX6_USB_OTG_IRQ, 347 FSL_IMX6_USB_HOST1_IRQ, 348 FSL_IMX6_USB_HOST2_IRQ, 349 FSL_IMX6_USB_HOST3_IRQ, 350 }; 351 352 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); 353 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, 354 FSL_IMX6_USBOH3_USB_ADDR + i * 0x200); 355 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, 356 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 357 FSL_IMX6_USBn_IRQ[i])); 358 } 359 360 /* Initialize all ECSPI */ 361 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { 362 static const struct { 363 hwaddr addr; 364 unsigned int irq; 365 } spi_table[FSL_IMX6_NUM_ECSPIS] = { 366 { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ }, 367 { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ }, 368 { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ }, 369 { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ }, 370 { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ }, 371 }; 372 373 /* Initialize the SPI */ 374 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 375 return; 376 } 377 378 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr); 379 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 380 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 381 spi_table[i].irq)); 382 } 383 384 object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, 385 &error_abort); 386 qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]); 387 if (!sysbus_realize(SYS_BUS_DEVICE(&s->eth), errp)) { 388 return; 389 } 390 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR); 391 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0, 392 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 393 FSL_IMX6_ENET_MAC_IRQ)); 394 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1, 395 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 396 FSL_IMX6_ENET_MAC_1588_IRQ)); 397 398 /* 399 * SNVS 400 */ 401 sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort); 402 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6_SNVSHP_ADDR); 403 404 /* 405 * Watchdog 406 */ 407 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) { 408 static const hwaddr FSL_IMX6_WDOGn_ADDR[FSL_IMX6_NUM_WDTS] = { 409 FSL_IMX6_WDOG1_ADDR, 410 FSL_IMX6_WDOG2_ADDR, 411 }; 412 static const int FSL_IMX6_WDOGn_IRQ[FSL_IMX6_NUM_WDTS] = { 413 FSL_IMX6_WDOG1_IRQ, 414 FSL_IMX6_WDOG2_IRQ, 415 }; 416 417 object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", 418 true, &error_abort); 419 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); 420 421 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]); 422 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, 423 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 424 FSL_IMX6_WDOGn_IRQ[i])); 425 } 426 427 /* ROM memory */ 428 if (!memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom", 429 FSL_IMX6_ROM_SIZE, errp)) { 430 return; 431 } 432 memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR, 433 &s->rom); 434 435 /* CAAM memory */ 436 if (!memory_region_init_rom(&s->caam, OBJECT(dev), "imx6.caam", 437 FSL_IMX6_CAAM_MEM_SIZE, errp)) { 438 return; 439 } 440 memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR, 441 &s->caam); 442 443 /* OCRAM memory */ 444 if (!memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", 445 FSL_IMX6_OCRAM_SIZE, errp)) { 446 return; 447 } 448 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR, 449 &s->ocram); 450 451 /* internal OCRAM (256 KB) is aliased over 1 MB */ 452 memory_region_init_alias(&s->ocram_alias, OBJECT(dev), "imx6.ocram_alias", 453 &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE); 454 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR, 455 &s->ocram_alias); 456 } 457 458 static Property fsl_imx6_properties[] = { 459 DEFINE_PROP_UINT32("fec-phy-num", FslIMX6State, phy_num, 0), 460 DEFINE_PROP_END_OF_LIST(), 461 }; 462 463 static void fsl_imx6_class_init(ObjectClass *oc, void *data) 464 { 465 DeviceClass *dc = DEVICE_CLASS(oc); 466 467 device_class_set_props(dc, fsl_imx6_properties); 468 dc->realize = fsl_imx6_realize; 469 dc->desc = "i.MX6 SOC"; 470 /* Reason: Uses serial_hd() in the realize() function */ 471 dc->user_creatable = false; 472 } 473 474 static const TypeInfo fsl_imx6_type_info = { 475 .name = TYPE_FSL_IMX6, 476 .parent = TYPE_DEVICE, 477 .instance_size = sizeof(FslIMX6State), 478 .instance_init = fsl_imx6_init, 479 .class_init = fsl_imx6_class_init, 480 }; 481 482 static void fsl_imx6_register_types(void) 483 { 484 type_register_static(&fsl_imx6_type_info); 485 } 486 487 type_init(fsl_imx6_register_types) 488