1 /* 2 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX6 SOC emulation. 5 * 6 * Based on hw/arm/fsl-imx31.c 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "qemu-common.h" 25 #include "hw/arm/fsl-imx6.h" 26 #include "sysemu/sysemu.h" 27 #include "chardev/char.h" 28 #include "qemu/error-report.h" 29 30 #define IMX6_ESDHC_CAPABILITIES 0x057834b4 31 32 #define NAME_SIZE 20 33 34 static void fsl_imx6_init(Object *obj) 35 { 36 FslIMX6State *s = FSL_IMX6(obj); 37 char name[NAME_SIZE]; 38 int i; 39 40 if (smp_cpus > FSL_IMX6_NUM_CPUS) { 41 error_report("%s: Only %d CPUs are supported (%d requested)", 42 TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus); 43 exit(1); 44 } 45 46 for (i = 0; i < smp_cpus; i++) { 47 object_initialize(&s->cpu[i], sizeof(s->cpu[i]), 48 "cortex-a9-" TYPE_ARM_CPU); 49 snprintf(name, NAME_SIZE, "cpu%d", i); 50 object_property_add_child(obj, name, OBJECT(&s->cpu[i]), NULL); 51 } 52 53 object_initialize(&s->a9mpcore, sizeof(s->a9mpcore), TYPE_A9MPCORE_PRIV); 54 qdev_set_parent_bus(DEVICE(&s->a9mpcore), sysbus_get_default()); 55 object_property_add_child(obj, "a9mpcore", OBJECT(&s->a9mpcore), NULL); 56 57 object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX6_CCM); 58 qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default()); 59 object_property_add_child(obj, "ccm", OBJECT(&s->ccm), NULL); 60 61 object_initialize(&s->src, sizeof(s->src), TYPE_IMX6_SRC); 62 qdev_set_parent_bus(DEVICE(&s->src), sysbus_get_default()); 63 object_property_add_child(obj, "src", OBJECT(&s->src), NULL); 64 65 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { 66 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL); 67 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); 68 snprintf(name, NAME_SIZE, "uart%d", i + 1); 69 object_property_add_child(obj, name, OBJECT(&s->uart[i]), NULL); 70 } 71 72 object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX6_GPT); 73 qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default()); 74 object_property_add_child(obj, "gpt", OBJECT(&s->gpt), NULL); 75 76 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { 77 object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT); 78 qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default()); 79 snprintf(name, NAME_SIZE, "epit%d", i + 1); 80 object_property_add_child(obj, name, OBJECT(&s->epit[i]), NULL); 81 } 82 83 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { 84 object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C); 85 qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default()); 86 snprintf(name, NAME_SIZE, "i2c%d", i + 1); 87 object_property_add_child(obj, name, OBJECT(&s->i2c[i]), NULL); 88 } 89 90 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { 91 object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO); 92 qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default()); 93 snprintf(name, NAME_SIZE, "gpio%d", i + 1); 94 object_property_add_child(obj, name, OBJECT(&s->gpio[i]), NULL); 95 } 96 97 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { 98 object_initialize(&s->esdhc[i], sizeof(s->esdhc[i]), TYPE_IMX_USDHC); 99 qdev_set_parent_bus(DEVICE(&s->esdhc[i]), sysbus_get_default()); 100 snprintf(name, NAME_SIZE, "sdhc%d", i + 1); 101 object_property_add_child(obj, name, OBJECT(&s->esdhc[i]), NULL); 102 } 103 104 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { 105 object_initialize(&s->spi[i], sizeof(s->spi[i]), TYPE_IMX_SPI); 106 qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); 107 snprintf(name, NAME_SIZE, "spi%d", i + 1); 108 object_property_add_child(obj, name, OBJECT(&s->spi[i]), NULL); 109 } 110 111 object_initialize(&s->eth, sizeof(s->eth), TYPE_IMX_ENET); 112 qdev_set_parent_bus(DEVICE(&s->eth), sysbus_get_default()); 113 object_property_add_child(obj, "eth", OBJECT(&s->eth), NULL); 114 } 115 116 static void fsl_imx6_realize(DeviceState *dev, Error **errp) 117 { 118 FslIMX6State *s = FSL_IMX6(dev); 119 uint16_t i; 120 Error *err = NULL; 121 122 for (i = 0; i < smp_cpus; i++) { 123 124 /* On uniprocessor, the CBAR is set to 0 */ 125 if (smp_cpus > 1) { 126 object_property_set_int(OBJECT(&s->cpu[i]), FSL_IMX6_A9MPCORE_ADDR, 127 "reset-cbar", &error_abort); 128 } 129 130 /* All CPU but CPU 0 start in power off mode */ 131 if (i) { 132 object_property_set_bool(OBJECT(&s->cpu[i]), true, 133 "start-powered-off", &error_abort); 134 } 135 136 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); 137 if (err) { 138 error_propagate(errp, err); 139 return; 140 } 141 } 142 143 object_property_set_int(OBJECT(&s->a9mpcore), smp_cpus, "num-cpu", 144 &error_abort); 145 146 object_property_set_int(OBJECT(&s->a9mpcore), 147 FSL_IMX6_MAX_IRQ + GIC_INTERNAL, "num-irq", 148 &error_abort); 149 150 object_property_set_bool(OBJECT(&s->a9mpcore), true, "realized", &err); 151 if (err) { 152 error_propagate(errp, err); 153 return; 154 } 155 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR); 156 157 for (i = 0; i < smp_cpus; i++) { 158 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, 159 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); 160 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus, 161 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); 162 } 163 164 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err); 165 if (err) { 166 error_propagate(errp, err); 167 return; 168 } 169 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR); 170 171 object_property_set_bool(OBJECT(&s->src), true, "realized", &err); 172 if (err) { 173 error_propagate(errp, err); 174 return; 175 } 176 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR); 177 178 /* Initialize all UARTs */ 179 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { 180 static const struct { 181 hwaddr addr; 182 unsigned int irq; 183 } serial_table[FSL_IMX6_NUM_UARTS] = { 184 { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ }, 185 { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ }, 186 { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ }, 187 { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ }, 188 { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ }, 189 }; 190 191 if (i < MAX_SERIAL_PORTS) { 192 Chardev *chr; 193 194 chr = serial_hds[i]; 195 196 if (!chr) { 197 char *label = g_strdup_printf("imx6.uart%d", i + 1); 198 chr = qemu_chr_new(label, "null"); 199 g_free(label); 200 serial_hds[i] = chr; 201 } 202 203 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); 204 } 205 206 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 207 if (err) { 208 error_propagate(errp, err); 209 return; 210 } 211 212 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 213 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 214 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 215 serial_table[i].irq)); 216 } 217 218 s->gpt.ccm = IMX_CCM(&s->ccm); 219 220 object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err); 221 if (err) { 222 error_propagate(errp, err); 223 return; 224 } 225 226 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR); 227 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, 228 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 229 FSL_IMX6_GPT_IRQ)); 230 231 /* Initialize all EPIT timers */ 232 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { 233 static const struct { 234 hwaddr addr; 235 unsigned int irq; 236 } epit_table[FSL_IMX6_NUM_EPITS] = { 237 { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ }, 238 { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ }, 239 }; 240 241 s->epit[i].ccm = IMX_CCM(&s->ccm); 242 243 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err); 244 if (err) { 245 error_propagate(errp, err); 246 return; 247 } 248 249 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 250 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 251 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 252 epit_table[i].irq)); 253 } 254 255 /* Initialize all I2C */ 256 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { 257 static const struct { 258 hwaddr addr; 259 unsigned int irq; 260 } i2c_table[FSL_IMX6_NUM_I2CS] = { 261 { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ }, 262 { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ }, 263 { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ } 264 }; 265 266 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err); 267 if (err) { 268 error_propagate(errp, err); 269 return; 270 } 271 272 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 273 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 274 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 275 i2c_table[i].irq)); 276 } 277 278 /* Initialize all GPIOs */ 279 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { 280 static const struct { 281 hwaddr addr; 282 unsigned int irq_low; 283 unsigned int irq_high; 284 } gpio_table[FSL_IMX6_NUM_GPIOS] = { 285 { 286 FSL_IMX6_GPIO1_ADDR, 287 FSL_IMX6_GPIO1_LOW_IRQ, 288 FSL_IMX6_GPIO1_HIGH_IRQ 289 }, 290 { 291 FSL_IMX6_GPIO2_ADDR, 292 FSL_IMX6_GPIO2_LOW_IRQ, 293 FSL_IMX6_GPIO2_HIGH_IRQ 294 }, 295 { 296 FSL_IMX6_GPIO3_ADDR, 297 FSL_IMX6_GPIO3_LOW_IRQ, 298 FSL_IMX6_GPIO3_HIGH_IRQ 299 }, 300 { 301 FSL_IMX6_GPIO4_ADDR, 302 FSL_IMX6_GPIO4_LOW_IRQ, 303 FSL_IMX6_GPIO4_HIGH_IRQ 304 }, 305 { 306 FSL_IMX6_GPIO5_ADDR, 307 FSL_IMX6_GPIO5_LOW_IRQ, 308 FSL_IMX6_GPIO5_HIGH_IRQ 309 }, 310 { 311 FSL_IMX6_GPIO6_ADDR, 312 FSL_IMX6_GPIO6_LOW_IRQ, 313 FSL_IMX6_GPIO6_HIGH_IRQ 314 }, 315 { 316 FSL_IMX6_GPIO7_ADDR, 317 FSL_IMX6_GPIO7_LOW_IRQ, 318 FSL_IMX6_GPIO7_HIGH_IRQ 319 }, 320 }; 321 322 object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-edge-sel", 323 &error_abort); 324 object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-upper-pin-irq", 325 &error_abort); 326 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err); 327 if (err) { 328 error_propagate(errp, err); 329 return; 330 } 331 332 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); 333 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 334 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 335 gpio_table[i].irq_low)); 336 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, 337 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 338 gpio_table[i].irq_high)); 339 } 340 341 /* Initialize all SDHC */ 342 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { 343 static const struct { 344 hwaddr addr; 345 unsigned int irq; 346 } esdhc_table[FSL_IMX6_NUM_ESDHCS] = { 347 { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ }, 348 { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ }, 349 { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ }, 350 { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ }, 351 }; 352 353 /* UHS-I SDIO3.0 SDR104 1.8V ADMA */ 354 object_property_set_uint(OBJECT(&s->esdhc[i]), 3, "sd-spec-version", 355 &err); 356 object_property_set_uint(OBJECT(&s->esdhc[i]), IMX6_ESDHC_CAPABILITIES, 357 "capareg", &err); 358 object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err); 359 if (err) { 360 error_propagate(errp, err); 361 return; 362 } 363 sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); 364 sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, 365 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 366 esdhc_table[i].irq)); 367 } 368 369 /* Initialize all ECSPI */ 370 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { 371 static const struct { 372 hwaddr addr; 373 unsigned int irq; 374 } spi_table[FSL_IMX6_NUM_ECSPIS] = { 375 { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ }, 376 { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ }, 377 { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ }, 378 { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ }, 379 { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ }, 380 }; 381 382 /* Initialize the SPI */ 383 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); 384 if (err) { 385 error_propagate(errp, err); 386 return; 387 } 388 389 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr); 390 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 391 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 392 spi_table[i].irq)); 393 } 394 395 qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]); 396 object_property_set_bool(OBJECT(&s->eth), true, "realized", &err); 397 if (err) { 398 error_propagate(errp, err); 399 return; 400 } 401 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR); 402 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0, 403 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 404 FSL_IMX6_ENET_MAC_IRQ)); 405 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1, 406 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 407 FSL_IMX6_ENET_MAC_1588_IRQ)); 408 409 /* ROM memory */ 410 memory_region_init_rom(&s->rom, NULL, "imx6.rom", 411 FSL_IMX6_ROM_SIZE, &err); 412 if (err) { 413 error_propagate(errp, err); 414 return; 415 } 416 memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR, 417 &s->rom); 418 419 /* CAAM memory */ 420 memory_region_init_rom(&s->caam, NULL, "imx6.caam", 421 FSL_IMX6_CAAM_MEM_SIZE, &err); 422 if (err) { 423 error_propagate(errp, err); 424 return; 425 } 426 memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR, 427 &s->caam); 428 429 /* OCRAM memory */ 430 memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE, 431 &err); 432 if (err) { 433 error_propagate(errp, err); 434 return; 435 } 436 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR, 437 &s->ocram); 438 439 /* internal OCRAM (256 KB) is aliased over 1 MB */ 440 memory_region_init_alias(&s->ocram_alias, NULL, "imx6.ocram_alias", 441 &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE); 442 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR, 443 &s->ocram_alias); 444 } 445 446 static void fsl_imx6_class_init(ObjectClass *oc, void *data) 447 { 448 DeviceClass *dc = DEVICE_CLASS(oc); 449 450 dc->realize = fsl_imx6_realize; 451 dc->desc = "i.MX6 SOC"; 452 /* Reason: Uses serial_hds[] in the realize() function */ 453 dc->user_creatable = false; 454 } 455 456 static const TypeInfo fsl_imx6_type_info = { 457 .name = TYPE_FSL_IMX6, 458 .parent = TYPE_DEVICE, 459 .instance_size = sizeof(FslIMX6State), 460 .instance_init = fsl_imx6_init, 461 .class_init = fsl_imx6_class_init, 462 }; 463 464 static void fsl_imx6_register_types(void) 465 { 466 type_register_static(&fsl_imx6_type_info); 467 } 468 469 type_init(fsl_imx6_register_types) 470